SM5837AF
Variable-length 1H Delay Line LSI
OVERVIEW
The SM5837AF is a variable-length delay line LSI. It has 12-bit input/output signal which can be set to
undergo a delay in the range of 31 to 2078 delay bits. Maximum operating frequency is 40MHz, making it
ideal for use in video signal processing applications.
RSTN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
41
40
39
38
37
36
35
34
9
25
DO10
DL8
10
24
DO9
DL9
11
23
DO8
22
DO11
DL7
NC
26
21
8
DO8
VDD
DL6
20
27
DO7
7
19
CLK
DL5
DO5
28
18
6
DO4
OE
VSS1
17
29
VSS2
5
16
DI11
DL4
PACKAGE DIMENSIONS
(Unit: mm)
12.80 ± 0.30
0 to 10 °
10.00
10.00
0.60 ± 0.20
0.35 ± 0.10
1.75MAX
1.45
0.80
0 to 0.20
12.80 ± 0.30
44-pin QFP
PARA
30
0.17 ± 0.05
SM5837AF
42
4
ORDERING INFORMATION
Package
NC
DI10
DL3
Video signal image processing
Device
43
31
APPLICATIONS
■
44
3
DO3
■
DI9
DL2/LEN
15
■
DI8
32
DO2
■
33
2
14
■
1
DO1
■
DL0/SDI
DL1/SICK
13
■
■
(Top view)
12
■
Variable-length 1H delay
12-bit input/output signal width
31 to 2078- bit delay length range
40MHz maximum operating frequency
Selectable delay setting method
• 11-bit parallel input
• 3-line serial input
TTL-compatible input/outputs
Tristate outputs
4.75 to 5.25V operating voltage
Molybenum-gate CMOS process
Package: 44-pin QFP
DO0
■
■
PINOUT
DL10
FEATURES
SEIKO NPC CORPORATION —1
SM5837AF
12
12
Variable-length
12-bit
1H Delay
DI0 - 11
CLK
Output Buffer
BLOCK DIAGRAM
12
DO0 - 11
OE
Delay Length Control
RSTN
11
PARA
Parallel/Serial Select
11
VDD
SDI
SICK
SIPO
VSS2
11
LEN
VSS1
DL0 - 10
PIN DESCRIPTION
Number
Name
I/O1
Function
1
DL0/SDI
Ip
Delay length set parallel data bit DL0 (LSB) when PARA is HIGH, and SDI serial data input when PARA is LOW.
2
DL1/SICK
Ip
Delay length set parallel data bit DL1 (bit 1) when PARA is HIGH, and SICK shift clock when PARA is LOW.
3
DL2/LEN
Ip
Delay length set parallel data bit DL2 (bit 2) when PARA is HIGH, and LEN latch clock when PARA is LOW.
4
DL3
Ip
Delay length set data bit 3
5
DL4
Ip
Delay length set data bit 4
6
VSS1
–
Ground (0V) pin 1
7
DL5
Ip
Delay length set data bit 5
8
DL6
Ip
Delay length set data bit 6
9
DL7
Ip
Delay length set data bit 7
10
DL8
Ip
Delay length set data bit 8
11
DL9
Ip
Delay length set data bit 9
12
DL10
Ip
Delay length set data bit 10
13
DO0
O
Signal output data bit 0
14
DO1
O
Signal output data bit 1
15
DO2
O
Signal output data bit 2
16
DO3
O
Signal output data bit 3
17
VSS2
–
Ground (0V) pin 2
18
DO4
O
Signal output data bit 4
19
DO5
O
Signal output data bit 5
20
DO6
O
Signal output data bit 6
21
DO7
O
Signal output data bit 7
SEIKO NPC CORPORATION —2
SM5837AF
Number
Name
I/O1
22
NC
–
No connection
23
DO8
O
Signal output data bit 8
24
DO9
O
Signal output data bit 9
25
DO10
O
Signal output data bit 10
26
DO11
O
Signal output data bit 11
27
VDD
–
Supply (5V) pin
28
CLK
I
Clock input
29
OE
Ip
Tristate output enable. Enable when HIGH, and disable when LOW.
30
DI11
Ip
Signal input data bit 11
31
DI10
Ip
Signal input data bit 10
32
DI9
Ip
Signal input data bit 9
33
DI8
Ip
Signal input data bit 8
34
DI7
Ip
Signal input data bit 7
35
DI6
Ip
Signal input data bit 6
36
DI5
Ip
Signal input data bit 5
37
DI4
Ip
Signal input data bit 4
38
DI3
Ip
Signal input data bit 3
39
DI2
Ip
Signal input data bit 2
40
DI1
Ip
Signal input data bit 1
41
DI0
Ip
Signal input data bit 0
42
RSTN
Ip
Reset pin. Normal operation when HIGH, and reset operation when LOW.
43
PARA
Ip
Delay length setting method select.
Parallel data (DL0 to DL10) when HIGH, and serial input (SDI, SICK, LEN) when LOW.
44
NC
–
No connection
Function
1. Ip = input pin with built-in pull-up resistor, O = output.
SEIKO NPC CORPORATION —3
SM5837AF
SPECIFICATIONS
Absolute Maximum Ratings
VSS = VSS1 = VSS2 = 0V
Parameter
Symbol
Condition
Rating
Unit
Supply voltage range
VDD
−0.3 to 7.0
V
Input voltage range
VIN
VSS − 0.3 to VDD + 0.3
V
Storage temperature range
Tstg
−40 to 125
°C
Power dissipation
PD
450
mW
Rating
Unit
Recommended Operating Conditions
VSS = 0V
Parameter
Symbol
Condition
Supply voltage range
VDD
4.75 to 5.25
V
Operating temperature
Topr
−20 to 70
°C
DC Characteristics
VDD = 4.75 to 5.25V, VSS = 0V, Ta = −20 to 70°C unless otherwise noted.
Rating
Parameter
Current consumption
Input voltage1, 2
Output voltage3
Symbol
Condition
Unit
min
typ
max
–
–
85
mA
VIH
2.4
–
–
V
VIL
–
–
0.5
V
4.0
–
–
V
IDD
VDD = 5.0V, CLK frequency
fC = 40MHz, OE = 0V
VOH
IOH = −0.4mA
VOL
IOL = 1.6mA
–
–
0.4
V
Input current2
IIL
VIN = 0V
–
10
20
µA
Input leakage current1, 2
ILH
VIN = VDD
–
–
1
µA
Input leakage current1
ILL
VIN = 0V
–
–
1
µA
Output high-impedance leakage
current3
IZH
VOUT = VDD
–
–
5
µA
IZL
VOUT = 0V
–
–
5
µA
1. Pin CLK
2. Pins DI0 to DI11, PARA, DL0/SDI, DL1/SICK, DL2/LEN, DL3 to DL10, OE and RSTN
3. Pins DO0 to DO11
SEIKO NPC CORPORATION —4
SM5837AF
AC Characteristics
VDD = 4.75 to 5.25V, VSS = 0V, Ta = −20 to 70°C unless otherwise noted.
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
CLK clock cycle
tCP1
25
–
–
ns
CLK clock HIGH-level pulsewidth
tCH1
10
–
–
ns
CLK clock LOW-level pulsewidth
tCL1
10
–
–
ns
SICK clock cycle
tCP2
50
–
–
ns
SICK clock HIGH-level pulsewidth
tCH2
20
–
–
ns
SICK clock LOW-level pulsewidth
tCL2
20
–
–
ns
CLK, SICK and LEN rise time
tCR
1.0 to 2.0V
–
–
10
ns
CLK, SICK and LEN fall time
tCF
1.0 to 2.0V
–
–
10
ns
DI0 to DI11, DL0 to DL10 and RSTN
setup time
tS1
10
–
–
ns
DI0 to DI11, DL0 to DL10 and RSTN
hold time
tH1
0
–
–
ns
SDI setup time
tS2
25
–
–
ns
SD1 hold time
tH2
25
–
–
ns
SICK rising edge → LEN rising edge
tCE
25
–
–
ns
LEN rising edge → SICK rising edge
tEC
25
–
–
ns
CLK → DO0 to D011 output delay
tPD
–
–
20
ns
CLK → DO0 to D011 output hold time
tOH
5
–
–
ns
OE HIGH-level pulsewidth
tOEH
50
–
–
ns
OE LOW-level pulsewidth
tOEL
50
–
–
ns
OE → DO0 to DO11 output enable
delay
tPZL
–
–
25
ns
–
–
25
ns
tPLZ
–
–
25
ns
tPHZ
–
–
25
ns
f = 1MHz
–
–
10
pF
f = 1MHz, OE = VIL
–
–
15
pF
OE → DO0 to DO11 output disable
delay
tPZH
Input capacitance
CIN
Output capacitance
COUT
Load conditions 1
See “Load conditions 1”.
See “Load conditions 2”.
Load conditions 2
OUTPUT
OUTPUT
40pF
500Ω
40pF
0V( t PHZ , t PZH )
2.6V( t PLZ , t PZL )
SEIKO NPC CORPORATION —5
SM5837AF
t CR
CLK
t CF
2.4V Min
1.5V
0.5V Max
2.0V
1.0V
t CH1
t CL1
t CP1
CLK
1.5V
t H1
t S1
DI0 - 11
1.5V
t H1
t S1
DL0 - 10
1.5V
t H1
t S1
RSTN
1.5V
CLK
1.5V
t PD
t OH
VALID
VALID
DO0 - 11
t OEH
1.5V
t OEL
OE
1.5V
t PZH
t PHZ
0.5V
1.5V
Hi-Z
DO0 - 11
t PZL
t PLZ
Hi-Z
1.5V
0.5V
t CL2
t CP2
t CH2
SICK
1.5V
t S2
t H2
SDI
1.5V
t CE
LEN
t EC
1.5V
SEIKO NPC CORPORATION —6
SM5837AF
FUNCTIONAL DESCRIPTION
The SM5837AF provides a built-in 1H delay for video signal processing. The delay can be set to a length of 31
to 2078 clock delay bits. The delay length (LH) can be set using 2 methods, selected by the state of PARA.
When PARA is HIGH, the delay length is set by parallel input data on DL0 to DL10. When PARA is LOW, the
delay length is set by serial input data using SDI, SICK and LEN. Accordingly, the function of DL0/SDI,
DL1/SICK and DL2/LEN is determined by PARA.
Parallel Input Set Method (PARA, DL0 to DL10)
When PARA is HIGH, parallel input data is used to set the delay length. The delay length (LH) is determined
by the input data on DL0 to DL10 as shown in equation 1 and table 1.
10
LH = 31 + Σ {DLk × 2 k }
(1)
k=0
Table 1. Delay bit length setting
DL10
DL9
DL8
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DL0
Delay length
0
0
0
0
0
0
0
0
0
0
0
31
0
0
0
0
0
0
0
0
0
0
1
32
0
0
0
0
0
0
0
0
0
1
0
33
0
0
0
0
0
0
0
0
0
1
1
34
0
0
0
0
0
0
0
0
1
0
0
35
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
0
0
1
1
1
1
0
0
0
0
1
512
0
0
1
1
1
1
0
0
0
1
0
513
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
0
1
1
1
1
1
0
0
0
0
1
1024
0
1
1
1
1
1
0
0
0
1
0
1025
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
1
1
1
1
1
1
0
0
0
0
1
2048
1
1
1
1
1
1
0
0
0
1
0
2049
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
1
1
1
1
1
1
1
1
1
1
0
2077
1
1
1
1
1
1
1
1
1
1
1
2078
SEIKO NPC CORPORATION —7
SM5837AF
Serial Input Set Method (PARA, SDI, SICK, LEN)
When PARA goes LOW, 3-input serial data set method is used to set the delay length. Inputs DL3 to DL10 are
ignored. SDI, SICK and LEN function as the serial data input, serial data shift clock and latch clock enable,
respectively.
The serial input data format, shown in figure XREF, comprises 11-bit serial data (S0 to S10) input on SDI in
sync with SICK. The data on SDI is clocked into the serial-to-parallel converter shift register on the rising edge
of SICK, and 11-bit parallel data is then latched into the delay length set register on the rising edge of LEN.
The delay length (LH) is determined by the input data S0 to S10 (just as for parallel input data DL0 to DL10) as
shown in equation 2. See also table 1.
Note that SICK and CLK can be asynchronous.
10
LH = 31 + Σ {Sk × 2 k }
(2)
k=0
SDI
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
SICK
LEN
Dotted lines indicate possible SICK and LEN states.
Figure 1. Serial input data format
Delay Clock Input (CLK)
All 1H delay registers operate in sync with the delay clock CLK. The maximum clock frequency is 40MHz.
Input Data (DI0 to DI11)
DI0 to DI11 are the 12-bit data inputs.
Output Data (DO0 to DO11, OE)
DO0 to DO11 are the 12-bit data outputs. They are tristate outputs, with the output state selected by OE. When
OE is HIGH, the outputs are enabled. When OE is LOW, the outputs are disabled (high-impedance state).
Reset (RSTN)
At power-ON, the internal timing generator circuits must be initialized by a LOW-level input on RSTN. After
RSTN goes HIGH, the set delay length becomes active.
SEIKO NPC CORPORATION —8
SM5837AF
TIMING DIAGRAMS
Parallel Set Data (Delay Length = 31)
0
1
2
3
4
5
31
32
33
34
35
CLK
RSTN
DI0 - 11
D1
D2
D3
D4
D5
D31
D32
D33
D34
D1
D2
D3
D35
OE
DO0 - 11
UNKNOWN
Hi-Z
D5
PARA=H, DL0-10=L
Serial Set Data (Delay Length = 32)
DL0/SDI
0
1
2
3
4
5
6
7
8
9
10
DL1/SICK
DL2/LEN
RSTN
1
2
3
32
33
34
CLK
DI0 - 11
DO0 - 11
INVALID
D1
UNKNOWN
D2
D3
D1
D2
D3
PARA=L, DL3-10=Don't Care, OE=H
SEIKO NPC CORPORATION —9
SM5837AF
Please pay your attention to the following points at time of using the products shown in this document.
The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on
human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such
use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and
harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right
to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that
the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties.
Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document.
Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products,
and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or
modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in
compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested
appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku,
Tokyo 103-0026, Japan
Telephone: +81-3-6667-6601
Facsimile: +81-3-6667-6611
http://www.npc.co.jp/
Email: [email protected]
NC9408BE
2006.04
SEIKO NPC CORPORATION —10