NSC ADC12D040CIVS

ADC12D040
Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with
Internal/External Reference and Sample-and-Hold
General Description
Features
The ADC12D040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipelined architecture with digital error correction and an
on-chip sample-and-hold circuit to minimize die size and
power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the
ADC12D040 achieves 10.9 effective bits at 10 MHz input
and consumes just 600 mW at 40 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale input swing equal
to VREF with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. The
digital outputs for the two ADCs are available on separate
12-bit buses with an output data format choice of offset
binary or 2’s complement.
For ease of interface, the digital output driver power pins of
the ADC12D040 can be connected to a separate supply
voltage in the range of 2.5V to the digital supply voltage,
making the outputs compatible with low voltage systems.
When not converting, power consumption can be reduced by
pulling the PD pin high, placing the converter into the powerdown state where it typically consumes just 75 mW. The
ADC12D040’s speed, resolution and single supply operation
make it well suited for a variety of applications.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
n
n
n
n
n
n
n
n
n
© 2002 National Semiconductor Corporation
DS200460
Binary/2’s comp output format
Single supply operation
Internal sample-and-hold
Outputs 2.5V to 5V compatible
TTL/CMOS compatible input/outputs
Low power consumption
Power down mode
On-chip reference buffer
Internal/External 2V reference
Key Specifications
n
n
n
n
n
n
n
n
n
n
n
n
n
Resolution
Conversion Rate
DNL
INL
SNR (fIN = 10MHz)
ENOB (fIN = 10MHz)
THD (fIN = 10 MHz)
SFDR (fIN = 10 MHz)
Data Latency
Supply Voltage
Power Consumption, Operating
Power Down
Crosstalk
12 Bits
40 MSPS(min)
± 0.4 LSB(typ)
± 0.7 LSB(typ)
68 dB(typ)
10.9 bits(typ)
−78 dB (typ)
80 dB (typ)
6 Clock Cycles
+5V ± 5%
600 mW(typ)
75 mW(typ)
80 dB(typ)
Applications
n
n
n
n
n
n
n
Ultrasound and Imaging
Instrumentation
Communications Receivers
Sonar/Radar
xDSL
Cable Modems
DSP Front Ends
www.national.com
ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and
Sample-and-Hold
December 2002
ADC12D040
Connection Diagram
20046001
Ordering Information
www.national.com
Industrial (−40˚C ≤ TA ≤ +85˚C)
Package
ADC12D040CIVS
64 Pin TQFP
ADC12D040CIVSX
64 Pin TQFP Tape and Reel
ADC12D040EVAL
Evaluation Board
2
ADC12D040
Block Diagram
20046002
3
www.national.com
ADC12D040
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
15
2
VINA+
VINB+
Non-Inverting analog signal Inputs. With a 2.0V reference
voltage each input signal level is 2.0 VP-P centered on VCM.
16
1
VINA−
VINB−
Inverting analog signal Input. With a 2.0V reference voltage
the input signal level is from 2.0 VP-P centered on VCM. This
pin may be connected to VCM for single-ended operation, but
a differential input signal is required for best performance.
7
VREF
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. VREF is 2.0V nominal and
should be between 1.0V to 2.4V.
11
INT/EXT REF
13
5
VRPA
VRPB
12
6
VRNA
VRNB
14
4
VRMA
VRMB
VREF select pin. With a logic low at this pin the internal 2.0V
reference is selected. With a logic high on this pin an external
reference voltage should be applied to VREF input pin 7.
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
DIGITAL I/O
60
CLK
Digital clock input. The range of frequencies for this input is
100 kHz to 50 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
22
41
OEA
OEB
OEA and OEB are the output enable pins that, when low,
enables their respective TRI-STATE data output pins. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
59
PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
21
OF
Output Format pin. A logic low on this pin causes output data
to be in straight binary. A logic high on this pin causes the
output data to be in 2’s complement format.
www.national.com
4
Pin No.
Symbol
24–29
34–39
DA0–DA11
Equivalent Circuit
ADC12D040
Pin Descriptions and Equivalent Circuits
(Continued)
Description
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output
word. Output levels are TTL/CMOS compatible.
42–47
52–57
DB0–DB11
ANALOG POWER
9, 18, 19,
62, 63
VA
3, 8, 10,
17, 20, 61,
64
AGND
Positive analog supply pins. These pins should be connected
to a quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
The ground return for the analog supply.
DIGITAL POWER
33, 48
VD
32, 49
DGND
30, 51
23, 31, 40,
50, 58
Positive digital supply pin. This pin should be connected to
the same quiet +5V source as is VA and be bypassed to
DGND with a 0.1 µF monolithic capacitor located within 1 cm
of the power pin and with a 10 µF capacitor.
The ground return for the digital supply.
VDR
Positive digital supply pins for the ADC12D040’s output
drivers. These pins should be connected to a voltage source
of +2.5V to +5V and bypassed to DR GND with a 0.1 µF
monolithic capacitor. If the supply for these pins are different
from the supply used for VA and VD, they should also be
bypassed with a 10 µF tantalum capacitor. VDR should never
exceed the voltage on VD. All bypass capacitors should be
located within 1 cm of the supply pin.
DR GND
The ground return for the digital supply for the ADC12D040’s
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12D040’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
5
www.national.com
ADC12D040
Absolute Maximum Ratings
Machine Model (Note 5)
(Notes 1,
Soldering Temperature,
Infrared, 10 sec. (Note 6)
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VA, VD, VDR
VD + 0.3V
|VA–VD|
≤ 100 mV
Voltage on Any Input or Output Pin
Package Input Current (Note 3)
Package Dissipation at TA = 25˚C
−40˚C ≤ TA ≤ +85˚C
Operating Temperature
Supply Voltage (VA, VD)
+4.75V to +5.25V
Output Driver Supply (VDR)
+2.35V to VD
VREF Input
± 25 mA
± 50 mA
1.0V to 2.2V
CLK, PD, OE
−0.05V to VD + 0.05V
Analog Input Pins
See (Note 4)
−0V to (VA − 0.5V)
≤100mV
|AGND–DGND|
ESD Susceptibility
Human Body Model (Note 5)
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
−0.3V to VA or VD
+0.3V
Input Current at Any Pin (Note 3)
235˚C
Storage Temperature
6.5V
VDR
250V
2500V
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V, OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9)
Typical
(Note 10)
Limits
(Note 10)
12
Bits(min)
± 0.7
± 0.4
± 2.0
± 1.0
LSB(max)
Positive Error
0.51
+2.8/−1.9
%FS
Negative Error
0.68
+4/−2.7
%FS
Offset Error (VIN+ = VIN−)
−0.1
± 1.2
%FS(max)
Under Range Output Code
0
0
Over Range Output Code
4095
4095
Symbol
Parameter
Conditions
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non Linearity (Note 11)
DNL
Differential Non Linearity
GE
Gain Error
LSB(max)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
SNR
Signal-to-Noise Ratio
SINAD
Signal-to-Noise and Distortion
ENOB
Effective Number of Bits
THD
Total Hamonic Distortion
H2
Second Harmonic
H3
Third Harmonic
SFDR
Spurious Free Dynamic Range
IMD
Intermodulation Distortion
0 dBFS Input, Output at −3 dB
100
fIN = 1 MHz, VIN = −0.5 dBFS
69
fIN = 10 MHz, VIN = −0.5 dBFS
68
fIN = 1 MHz, VIN = −0.5 dBFS
69
fIN = 10 MHz, VIN = −0.5 dBFS
68
fIN = 1 MHz, VIN = −0.5 dBFS
11.1
fIN = 10 MHz, VIN = −0.5 dBFS
10.9
fIN = 1 MHz, VIN = −0.5 dBFS
−80
fIN = 10 MHz, VIN = −0.5 dBFS
−78
fIN = 1 MHz, VIN = −0.5 dBFS
−84
fIN = 10 MHz, VIN = −0.5 dBFS
−80
fIN = 1 MHz, VIN = −0.5 dBFS
−84
fIN = 10 MHz, VIN = −0.5 dBFS
−82
MHz
dB
66.5
dB(min)
dB
65.6
dB(min)
10.6
Bits(min)
Bits
dB
−69
dB(max)
−73
dB(max)
−69.5
dB(max)
69.5
dB(min)
dB
dB
fIN = 1 MHz, VIN = −0.5 dBFS
84
fIN = 10 MHz, VIN = −0.5 dBFS
80
fIN = 9.6 MHz and 10.2 MHz,
each = −6.0 dBFS
−80
dBFS
± 0.02
%FS
dB
INTER-CHANNEL CHARACTERISTICS
Channel — Channel Offset Match
www.national.com
6
(Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V, OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Typical
(Note 10)
Conditions
Channel — Channel Gain Error
Match
10 MHz Tested Channel. 15 MHz
Other Channel
Crosstalk
Limits
(Note 10)
Units
(Limits)
± 0.05
%FS
−80
dB
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
(CLK LOW)
VIN = 2.5 Vdc
+ 0.7 Vrms
VA/2
V
8
pF
7
pF
CIN
VIN Input Capacitance (each pin to
GND)
VREF
Input Reference Voltage (Note 13)
2.00
V
RREF
Reference Input Resistance
100
MΩ(min)
(CLK HIGH)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V, OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
2.0
V(min)
1.0
V(max)
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 5.25V
VIN(0)
Logical “0” Input Voltage
VD = 4.75V
IIN(1)
Logical “1” Input Current
VIN = 5.0V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 3V
VDR = 2.5V
2.3
V(min)
VDR = 3V
2.7
V(min)
0.4
V(max)
VOUT = 2.5V or 5V
100
nA
VOUT = 0V
−100
nA
IOZ
TRI-STATE Output Current
+ISC
Output Short Circuit Source
Current
VOUT = 0V
−20
mA(min)
−ISC
Output Short Circuit Sink Current
VOUT = VDR
20
mA(min)
COUT
Digital Output Capacitance
5
pF
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND, VREF = 2.0V
PD Pin = VDR
93
15
110
mA(max)
mA
ID
Digital Supply Current
PD Pin = DGND
PD Pin = VDR
16
0
18
mA(max)
mA
IDR
Digital Output Supply Current
PD Pin = DGND, CL = 0 pF (Note 14)
PD Pin = VDR
10.5
0
12
mA(max)
mA
Total Power Consumption
PD Pin = DGND, CL = 0 pF (Note 15)
PD Pin = VDR
600
75
700
mW
mW
Power Supply Rejection
Rejection of Full-Scale Error with
VA = 4.75V vs 5.25V
56
PSRR1
7
dB
www.national.com
ADC12D040
Converter Electrical Characteristics
ADC12D040
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V, OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C (Notes 7, 8, 9, 12)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
40
MHz(min)
fCLK1
Maximum Clock Frequency
55
fCLK2
Minimum Clock Frequency
100
kHz
tCH
Clock High Time
10.0
ns(min)
tCL
Clock Low Time
10.0
ns(min)
tCONV
Conversion Latency
tOD
Data Output Delay after Rising
CLK Edge
tAD
Aperture Delay
1.2
ns
tAJ
Aperture Jitter
2
ps rms
tHOLD
Clock Edge to Data Transistion
8
ns
tDIS
Data outputs into TRI-STATE
Mode
4
ns
tEN
Data Outputs Active after
TRI-STATE
4
ns
tPD
Power Down Mode Exit Cycle
500
ns
6
VDR = 3.0V
10
17.5
Clock
Cycles
ns(max)
ns(min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 64-pin
TQFP, θJA is 50˚C/W, so PDMAX = 2.5 Watts at 25˚C and 1.3 Watts at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
this device under normal operation will typically be about 620 mW (600 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per
(Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale
input voltage must be ≤4.85V to ensure accurate conversions.
20046007
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.
Note 10: Typical figures are at TA = TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
www.national.com
8
(Continued)
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for this application.
Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
VDR, and the rate at which the outputs are switching (which is signal dependent). IDR =VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply
voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
Note 15: Excludes IDR. See note 14.
9
www.national.com
ADC12D040
AC Electrical Characteristics
ADC12D040
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of 1⁄2 LSB
above negative full scale.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
OFFSET ERROR is the difference between the two input
voltages (VIN+–VIN−) required to cause a transition from code
2047 to 2048.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
CLOCK DUTY CYCLE is the ratio of the time during one
cycle that a repetitive digital waveform is high to the total
time of one period. The specification here refers to the ADC
clock input signal.
COMMON MODE VOLTAGE (VCM) is the d.c. potential
present at both signal inputs to the ADC.
OVERRANGE RECOVERY TIME is the time required after
VIN goes from a specified voltage out of the normal input
range to a specified voltage within the normal input range
and the converter makes a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
CONVERSION LATENCY See PIPELINE DELAY.
CROSSTALK is coupling of energy from one channel into
the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 11⁄2 LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC12D040, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the dc power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a. c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
A gain of unity occurs when the negative and positive full
scale errors are equal to each other, including having the
same sign.
GAIN ERROR MATCHING is the difference in gain errors
between the two converters divided by the average gain of
the converters.
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (1⁄2 LSB below the first code transition)
through positive full scale (1⁄2 LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is VREF/2n,
where “n” is the ADC resolution in bits, which is 12 in the
case of the ADC12D040.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12D040 is guaranteed
not to have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
www.national.com
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first seven harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where f1 is the RMS power of the fundamental (output)
frequency and f2 through f10 are the RMS power of the first
9 harmonic frequencies in the output spectrum.
10
ADC12D040
Timing Diagram
20046009
Output Timing
Transfer Characteristic
20046010
FIGURE 1. Transfer Characteristic
11
www.national.com
ADC12D040
Typical Performance Characteristics
VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz un-
less otherwise stated
Spectral Response @ Fin = 9.95 MHz, FCLK = 40 MHz
IMD Response Fin = 9.6 MHz, 10.2 MHz, FCLK = 40 MHz
20046056
20046055
Crosstalk Response Fin = 9.95 MHz, FCROSSTALK = 15
MHz, FCLK = 40 MHz
DNL
20046036
20046057
INL
INL & DNL vs Supply Voltage
20046037
www.national.com
20046038
12
INL & DNL vs Temperature
DNL & INL vs Clock Frequency
20046039
20046044
DNL & INL vs Clock Duty Cycle
DNL & INL vs Reference Voltage
20046047
20046050
SNR, SINAD, SFDR vs Supply Voltage
SINAD, SNR, SFDR vs Input Frequency
20046042
20046040
13
www.national.com
ADC12D040
Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless
otherwise stated (Continued)
ADC12D040
Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless
otherwise stated (Continued)
SNR, SINAD, SFDR vs Clock Frequency
SNR, SINAD, SFDR vs Clock Duty Cycle
20046048
20046045
SNR, SINAD, SFDR vs Reference Voltage
SNR, SINAD, SFDR vs Temperature
20046058
20046051
Distortion vs Supply Voltage
Distortion vs Input Frequency
20046043
20046041
www.national.com
14
Distortion vs Clock Frequency
Distortion vs Clock Duty Cycle
20046049
20046046
Distortion vs Reference Voltage
Distortion vs Temperature
20046059
20046052
Power Consumption vs Reference Voltage
Power Consumption vs Temperature
20046054
20046053
15
www.national.com
ADC12D040
Typical Performance Characteristics VA = VD = 5V, VDR = 3V, fCLK = 40 MHz, fIN = 10 MHz unless
otherwise stated (Continued)
ADC12D040
Functional Description
Operating on a single +5V supply, the ADC12D040 uses a
pipelined architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
input signal is digitized to 12 bits. The reference input is
buffered to ease the task of driving that pin.
The output word rate is the same as the clock frequency,
which can be between 100 kSPS and 55 MSPS (typical).
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by
the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 75 mW.
20046011
Applications Information
FIGURE 2. Expected Input Signal Range
1.0 OPERATING CONDITIONS
The ADC12D040 performs best with a differential input with
each input centered around VCM. The peak-to-peak voltage
swing at both VIN+ and VIN− should not exceed the value of
the reference voltage or the output data will be clipped. The
two input signals should be exactly 180˚ out of phase from
each other and of the same amplitude. For single frequency
inputs, angular errors result in a reduction of the effective full
scale input. For a complex waveform, however, angular
errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
EFS = dev1.79
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
We recommend that the following conditions be observed for
operation of the ADC12D040:
4.75V ≤ VA ≤ 5.25V
VD = V A
2.35V ≤ VDR ≤ VD
100 kHz ≤ fCLK ≤ 55 MHz
1.0V ≤ VREF ≤ 2.2V
1.1 Analog Inputs
The ADC12D040 has two analog signal inputs, VIN+ and
VIN−. These two pins form a differential input pair. There is
one reference input pin, VREF.
1.2 Reference Pins
The ADC12D040 is designed to operate with a 2.0V reference, but performs well with reference voltages in the range
of 1.0V to 2.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12D040. Increasing
the reference voltage (and the input signal swing) beyond
2.2V will degrade THD for a full-scale input. It is very important that all grounds associated with the reference voltage
and the input signal make connection to the analog ground
plane at a single point to minimize the effects of noise
currents in the ground path.
The three Reference Bypass Pins (VRP, VRM and VRN) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. DO
NOT LOAD these pins.
20046012
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, VREF, and be centered around VCM. For single
ended operation, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input.
The peak-to-peak differential input signal should be twice the
reference voltage to maximize SNR and SINAD performance
(Figure 2b). For example, set VREF to 1.0V, bias VIN− to 1.0V
and drive VIN+ with a signal range of 0V to 2.0V. Because
very large input signal swings can degrade distortion performance, better performance with a single-ended input can be
obtained by reducing the reference voltage when maintaining a full-range output. Tables 1, 2 indicate the input to
output relationship of the ADC12D040.
1.3 Signal Inputs
The signal inputs are VIN+ and VIN−. The input signal, VIN, is
defined as
VIN = (VIN+) – (VIN−)
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of VA/2. The input signals should remain between ground and 4V.
The Peaks of the individual input signals (VIN+ and VIN−)
should each never exceed the voltage described as
VIN+, VIN− = VREF/2 + VCM ≤ 4V (differential)
to maintain THD and SINAD performance.
www.national.com
16
ADC12D040
Applications Information
(Continued)
TABLE 1. Input to Output Relationship —
Differential Input
VIN+
VIN−
Binary Output
2’s Complement
Output
VCM −0.5* VREF
VCM +0.5* VREF
0000 0000 0000
1000 0000 0000
VCM −0.25* VREF
VCM +0.25* VREF
0100 0000 0000
1100 0000 0000
VCM
VCM
1000 0000 0000
0000 0000 0000
VCM +0.25* VREF
VCM −0.25* VREF
1100 0000 0000
0100 0000 0000
VCM +0.5* VREF
VCM −0.5* VREF
1111 1111 1111
0111 1111 1111
TABLE 2. Input to Output Relationship —
Single-Ended Input
VIN+
VIN−
Binary Output
2’s Complement
Output
1000 0000 0000
VCM −VREF
VCM
0000 0000 0000
VCM −0.5* VREF
VCM
0100 0000 0000
1100 0000 0000
VCM
VCM
1000 0000 0000
0000 0000 0000
VCM +0.5* VREF
VCM
1100 0000 0000
0100 0000 0000
VCM +VREF
VCM
1111 1111 1111
0111 1111 1111
nated, near the CLK pin, with a resistor in series with a
capacitor such that the resistor value is equal to the characteristic impedance of the clock transmission line and
The VIN+ and the VIN− inputs of the ADC12D040 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702 and the LMH6628 are good amplifiers for
driving the ADC12D040.
where tPD is the signal propagation rate down the line, L is
the length of the line in inches and ZO is the characteristic
impedance of the line.
Typical tPD is about 150 ps/inch for FR-4 board material.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33Ω series resistors at each of the signal
inputs with a 68 pF capacitor across the inputs, as can be
seen in Figure 5 . These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The 68 pF capacitor is for Nyquist applications and should be replaced with a 10 pF capacitor for
undersampling applications.
2.2 OEA, OEB
The OEA or OEB pin, when high, puts the output pins into a
high impedance state. When this pin is low the outputs are in
the active state. The ADC12D040 will continue to convert
whether this pin is high or low, but the output can not be read
while the pin is high.
2.3 PD
The PD pin, when high, holds the ADC12D040 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 40MHz clock and 40mW if the clock is stopped. The
output data pins are undefined in this mode. Power consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down
mode.
2.0 DIGITAL INPUTS
Digital inputs consist of CLK, OEA, OEB and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 55 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 ksps.
The clock source should be series terminated to match the
source impedance with the characteristic impedance, ZO, of
the clock line and the ADC CLK pin should be a.c. termi-
2.4 OF
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high.
3.0 OUTPUTS
The ADC12D040 has 24 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while the OE
and PD pins are low. While the tOD time provides information
17
www.national.com
ADC12D040
Applications Information
the specified 20 pF/pin will cause tOD to increase, making it
difficult to properly latch the ADC output data. The result
could be an apparent reduction in dynamic performance.
(Continued)
about output timing, a simple way to capture a valid output is
to latch the data on the falling edge of the conversion clock
(pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through VDR and DR GND. These large charging current
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing and careful attention to the ground plane will
reduce this problem. Additionally, bus capacitance beyond
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one input should be connected to each output pin. Additionally, inserting series resistors of 47Ω to 56Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
20046013
FIGURE 4. Application Circuit using Transformer or Differential OpAmp Drive Circuit
www.national.com
18
ADC12D040
Applications Information
(Continued)
20046014
FIGURE 5. Differential Drive Circuit of Figure 4
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 56Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12D040 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
mVP-P.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power.
The VDR pin provides power for the output drivers and may
be operated from a supply in the range of 2.35V to VD
(nominal 5V). This can simplify interfacing to low voltage
devices and systems. DO NOT operate the VDR pin at a
voltage higher than VD.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12D040
between these areas, is required to achieve specified performance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC12D040’s other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
19
www.national.com
ADC12D040
Applications Information
(Continued)
20046016
FIGURE 6. Example of a Suitable Layout
www.national.com
20
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12D040 with
a device that is powered from supplies outside the range of
the ADC12D040 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause tOD to increase, making it difficult to properly latch
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12D040, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 47Ω to 56Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figure 5) will
improve performance. The LMH6702 and the LMH6628
have been successfully used to drive the analog inputs of the
ADC12D040.
(Continued)
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the analog ground plane.
Figure 6 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. Furthermore, all components in the reference
circuitry and the input signal chain that are connected to
ground should be connected together with short traces and
enter the analog ground plane at a single point. All ground
connections should have a low inductance path to ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 7.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180o out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, VREF should be in
the range of
1.0V ≤ VREF ≤ 2.2V
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
20046017
FIGURE 7. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
21
www.national.com
ADC12D040
Applications Information
ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and
Sample-and-Hold
Physical Dimensions
inches (millimeters) unless otherwise noted
64-Lead TQFP Package
Ordering Number ADC12D040CIVS
NS Package Number VECO64A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.