APA2057A 2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver Features • General Description Operating Voltage The APA2057A is a monolithic integrated circuit, which combines a stereo power amplifier and a stereo output capacitor-less headphone amplifier. The stereo power amplifier provides 19-steps gain setting for flexible application. The headphone amplifier is ground-reference output, and doesn’t need the output capacitors for DC blocking. The advantages of eliminating the output capacitor are saving cost, PCB’s space, and component height. – HVDD= 3.0~3.6V • • • – VDD= 4.5~5.5V No Output Capacitor at Headphone Amplifier Required Meeting VISTA Requirement Low Distortion AMP Mode – THD+N=56dB, at VDD = 5V, RL = 4Ω, PO=1.5W – THD+N=64dB, at VDD = 5V, RL = 8Ω, PO=0.9W • • • • • • • • Both the de-pop circuitry and the thermal shutdown protection circuitry are integrated in the APA2057A, which reduces pops and clicks noise during power on/ off and in shutdown mode. Thermal shutdown protects the chip from being destroyed by over-temperature failure. To simplify the audio system design in notebook computer applications, the APA2057A provides the internal gain setting, and these features can minimize components and PCB area. HP Mode – THD+N=73dB, at HVDD=3.3V, RL=16Ω PO=125mW – THD+N=77dB, at HVDD=3.3V, RL=32Ω, PO=88mW – THD+N=85dB, at HVDD=3.3V, RL=10kΩ, VO=1.7Vrms The APA2057A is available in both TSSOP-28P and TQFN5x5-28 packages. Both packages are characterized by space saving and thermal efficiency. Output Power at 1% THD+N – 1.9W, at VDD = 5V, AMP Mode, RL = 4Ω – 1.2W, at VDD = 5V, AMP Mode, RL = 8Ω at 10% THD+N –2.4W at VDD = 5V, AMP Mode, RL = 4Ω –1.5W at VDD = 5V, AMP Mode, RL = 8Ω Applications • • Depop Circuitry Integrated Internal 19-Steps Gain Setting for Flexible Application Note Book PCs LCD Monitor Thermal Shutdown Protection and Over-Current Protection Circuitry High Supply Voltage Ripple Rejection Surface-Mount Packaging – TSSOP-28P (with Enhanced Thermal Pad) – TQFN5x5-28 (with Enhanced Thermal Pad) Lead Free and Green Devices Available (RoHS Compliant) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 1 www.anpec.com.tw APA2057A Ordering and Marking Information Package Code R : TSSOP-28P QB : TQFN5x5-28 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2057A Assembly Material Handling Code Temperature Range Package Code APA2057A R : APA2057A QB : APA2057A XXXXX XXXXX - Date Code APA2057A XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 25 BIAS INL_A 5 24 HP_EN INL_H 6 23 PGND LOUT+ 8 22 SET 24 BEEP 23 AMP_EN 26 SET INR_H 4 PGND 7 25 VDD 27 AMP_EN INR_A 3 26 GND 28 BEEP 27 INR_A VDD 1 GND 2 28 INR_H Pin Configuration APA2057A INL_A 1 21 BIAS INL_H 2 20 HP_EN PGND 3 22 ROUT+ 19 PGND LOUT+ 4 21 ROUT- 18 ROUT+ APA2057A 18 HP_L CVDD 7 15 HVDD CP+ 12 17 HP_R CGND 13 16 HVSS CP- 14 15 CVSS (TSSOP-28P) HP_L 14 16 PVDD CVDD 11 HP_R 13 PVDD 6 HVSS 12 19 HVDD CVSS 11 17 ROUT- PVDD 10 CP- 10 LOUT- 5 CP+ 8 20 PVDD CGND 9 LOUT- 9 (TQFN5x5-28) (Top view) (Top view) = Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD HVDD, VSS VSET, VAMP_EN, VHP_EN Parameter Rating Supply Voltage (PVDD, CVDD, VDD) Supply Voltage (HVDD) Supply Voltage (VSS) +0.3 to -6 Input Voltage V V 0 to VDD+0.3V TA Operating Ambient Temperature Range TJ Maximum Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 -0.3 to 6 Unit 2 -40 to 85 °C 150 °C www.anpec.com.tw APA2057A Absolute Maximum Ratings (Cont.) (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD Power Dissipation Unit -65 to +150 °C 260 °C Internally Limited W Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Thermal Resistance - Junction to Ambient Typical Value Unit (Note 2) θJA TSSOP-28P 45 TQFN5x5-28 43 o C/W Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TSSOP28P & TQFN-28 packages with solder on the printed circuit board. Recommended Operating Conditions Symbol Parameter Range Unit VDD Supply Voltage 4.5 ~ 5.5 V HVDD Supply Voltage 3.0 ~ 3.6 V VIH High Level Threshold Voltage AMP_EN, HP_EN 2~ V VIL Low Level Threshold Voltage AMP_EN, HP_EN ~ 0.8 V Vicm Common Mode Input Voltage for Amplifier ~ VDD-1 Shutdown VSET Input Voltage V ~ HVDD-1 for Headphone Amplifier ~ 0.8 Gain Setting V 2 ~ 4.2 Fix Gain 4.5 ~ Electrical Characteristics VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol VDD HVDD Parameter Test Conditions APA2057A Unit Min. Typ. Max. Supply Voltage 4.5 - 5.5 V Headphone Amplifier Supply Voltage 3.0 - 3.6 V IVDD VDD Supply Current Only Speaker mode, - 17.5 29 IHVDD HVDD Supply Current AMP_EN = HP_EN = 0V - 0.15 1 IVDD VDD Supply Current IHVDD HVDD Supply Current IVDD VDD Supply Current IHVDD HVDD Supply Current Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Only Headphone mode, - 12 20 HP_EN = AMP_EN = 5V - 3 5 All Enable, HP_EN=5V and AMP_EN = 0V - 20 35 - 3 5 3 mA www.anpec.com.tw APA2057A Electrical Characteristics (Cont.) VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol Parameter Test Conditions APA2057A Min. Typ. Max. - 50 90 - 1 10 Unit ISD(HVDD) HVDD Shutdown Current ISD(VDD) VDD Shutdown Current IAMP_EN Input Current AMP_EN - 1 - µA IHP_EN Input Current HP_EN - 10 15 µA 1.9 1.2 - 1.0 2.4 1.5 - 1.3 SET = 0V µA SPEAKER MODE PO VOS THD+N Crosstalk PSRR Output Power W Output Offset Voltage RL =8Ω, Gain =10.5dB - - 10 mV Total Harmonic Distortion Plus Noise fin =1kHz PO = 1.5W, RL =4Ω PO = 0.9W, RL =8Ω - 0.15 0.06 - % fin =1kHz, CB=2.2µF, RL=8Ω, PO=0.92W - 80 - fin =1kHz, CB=2.2µF, RL =4Ω, PO=1.5W - 83 - CB =2.2µF, RL =8Ω, fin =120Hz - 70 - dB PO =0.8W, RL =8Ω, A-weighting Filter - 90 - dB Gain =10.5dB, RL =8Ω, CB =2.2µF - 80 - µV (rms) 160 120 - 100 200 165 - 150 THD+N=10% - 2.9 - THD+N=1% - 2.4 - Channel Separation Power Supply Rejection Ratio S/N Vn THD+N =1%, fin =1kHz RL =4Ω RL =8Ω THD+N =10%, fin =1kHz RL =4Ω RL =8Ω Noise Output Voltage dB HEADPHONE MODE Po Output Power THD+N = 1%, fin =1kHz RL = 16Ω RL = 32Ω THD+N = 10%, fin =1kHz RL =16Ω RL =32Ω Vo Output Voltage Swing RL =10kΩ Vos Output Offset Voltage RL =32Ω mW -10 +10 Vrms mV fin = 1kHz THD+N Total Harmonic Distortion Plus Noise PO = 125mW, RL =16Ω PO = 88mW, RL =32Ω - PSRR Channel Separation Power Supply Rejection Ratio Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 - fin =1kHz, RL =16Ω, PO =125mW - 80 - fin =1kHz, RL =32Ω, PO =88mW - 85 - fin =1kHz, RL=10kΩ, VO =1.7Vrms - 105 - CB = 2.2µF, RL=32Ω, fin =120Hz - 80 - 4 % 0.005 VO=1.7Vrms, RL=10kΩ Crosstalk 0.02 0.02 dB dB www.anpec.com.tw APA2057A Electrical Characteristics (Cont.) VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol Parameter Test Conditions APA2057A Unit Min. Typ. Max. - 95 - dB HEADPHONE MODE (CONT.) With A-weighting Filter S/N PO = 70mW, RL =32Ω 92 VO =1.2Vrms, RL=10kΩ - 30 - µV (rms) Input Feedback Resistance 38 40 42 kΩ Fosc Switching Frequency 460 540 620 kHz CVSS Charge Dump Output Voltage (CVSS) - -0.98 VDD - V Req Charge Pump Requirement Resistance - 9 12 Ω Beep Trigger Level - 3 - VPP Beep Response Time - 4 - ms Vn Noise Output Voltage Rf CB =2.2µF CHARGE PUMP No load BEEP Vbeep TRES ATTENUATION Att (HP_EN) Att (AMP_EN) HP Disable Attenuation RL = 32Ω, VO = 1.1Vrms, fin = 1kHz - 115 - dB RL = 10kΩ, VO = 1.1Vrms, fin = 1kHz - 85 - dB AMP Disable Attenuation RL = 8Ω, VO = 2Vrms, fin = 1kHz - 112 - dB RL = 4Ω, VO = 2Vrms, fin = 1kHz - 112 - dB - 90 - dB - 100 - dB - 85 - dB - 80 - dB - 120 - msec Att_SD (HP_EN) Shutdown Active Att_SD(AMP_EN) Shutdown Active RL = 10kΩ on the Headphone Mode, VO = 1.1Vrms, fin = 1kHz RL = 8Ω on the AMP Mode, VO = 1Vrms, fin = 1kHz HEADPHONE TO SPEAKER CROSSTALK AMP_EN = 0V, RL = 8Ω Crosstalk Channel Separation HP_EN = 5V, RL = 16Ω, fin = 1kHz, PO = 125mW SPEAKER TO HEADPHONE CROSSTALK HP_EN = 5V, RL = 10kΩ Crosstalk Channel Separation AMP_EN = 0V, RL = 4Ω, fin = 1kHz, PO = 1.5W AMPLIFIER START-UP TIME Tstart-up Start-Up Time Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 5 www.anpec.com.tw APA2057A Gain Setting Table _AMP Mode (VDD=5V) Input Voltage (VSET) Hysteresis (mV) Recommended Voltage (V) 2.00 SD 0.00 2.04 2.12 47 2.08 2.15 2.24 36 2.20 -3 2.28 2.35 41 2.31 -1 2.39 2.47 41 2.43 1 2.51 2.58 35 2.54 3 2.62 2.70 41 2.66 4 2.74 2.81 48 2.78 5 2.86 2.92 43 2.89 6 2.97 3.04 47 3.01 7 3.09 3.15 45 3.12 8 3.21 3.27 54 3.24 Gain (dB) Low (V) High (V) -70 0 -7 -5 9 3.33 3.39 59 3.36 10 3.45 3.51 64 3.48 11 3.56 3.62 53 3.59 12 3.68 3.73 59 3.70 13 3.80 3.85 66 3.82 14 3.92 3.96 69 3.94 15 4.02 4.07 64 4.05 16 4.15 4.17 76 4.16 10.5 4.26 5.00 94 5.00 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 6 www.anpec.com.tw APA2057A Recommend Resistance’s Value for Gain Setting Gain (dB) R1 (1%) R# (1%) -70 10k 0 -7 18k 13k -5 20k 16k -3 18k 16k -1 16k 15k 1 15k 16k 3 13k 15k 4 24k 30k 5 13k 18k 6 13k 20k 7 13k 22k 8 16k 30k 9 13k 27k 10 13k 30k 11 15k 39k 12 13k 39k 13 13k 43k 14 13k 50k 15 15k 68k 16 13k 68k 10.5 10k >90k Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 7 www.anpec.com.tw APA2057A Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 VDD =5V fin=1kHz Cin=2.2µF BW<80kHz AMP mode VDD =5V RL=4Ω Cin=2.2µF BW<80kHz AMP mode RL=8Ω 1 THD+N (%) THD+N (%) 10 RL=4Ω 1 fin=20kHz fin=20Hz 0.1 fin=1kHz 0.05 0 0.5 1 1.5 2 2.5 0.1 0.01 3 0.1 Output Power (W) 5 Crosstalk vs. Frequency +0 VDD =5V RL=4Ω Cin=2.2µF PO=1.5W BW<80kHz AMP mode -10 -20 Crosstalk (dB) THD+N (%) 2 Output Power (W) THD+N vs. Frequency 10 1 1 -30 VDD =5V RL=4Ω Cin=2.2µ µ uF PO=1.5W AMP mode -40 -50 -60 Right to Left -70 Left to Right -80 Right Channel -90 Left Channel 0.1 20 100 1k -100 20 10k 20k 100 Frequency (Hz) 10k 20k 1k Frequency (Hz) Output Noise Voltage vs. Frequency Frequency Response 100µ +11 +30 +25 10µ VDD =5V Cin =2.2µF RL=4Ω PO=0.2W AMP mode +9 +8 Phase +20 +15 +10 Phase (deg) +10 Gain (dB) Output Noise Voltage (Vrms) Gain +5 VDD =5V RL=4Ω Cin=2.2µF A-weighting AMP mode 1µ 20 +7 +0 100 1k +6 10 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 100 1k 10k -5 100k 200k Frequency (Hz) 8 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Frequency 10 VDD =5V RL=8Ω Cin=2.2µF BW<80kHz AMP mode THD+N (%) THD+N (%) 10 1 fin=20kHz 0.1 fin=20Hz VDD =5V RL=8Ω Cin=2.2µF PO=0.92W BW<80kHz AMP mode 1 Left Channel 0.1 fin=1kHz Right Channel 0.05 0.01 0.1 0.05 20 5 1 100 Output Power (W) Crosstalk vs. Frequency Output Noise Voltage vs. Frequency VDD =5V RL=8 Ω Cin=2.2µF PO=0.92W AMP mode Output Noise Voltage (Vrms) -20 Crosstalk (dB) -30 -40 -50 -60 -70 Left to Right -80 Right to Left 10µ VDD =5V RL=8Ω Cin=2.2µF A-weighting AMP mode -90 -100 20 1µ 100 10k 20k 1k 20 Frequency (Hz) Frequency Response Crosstalk vs. Frequency +11 +0 +30 Gain -10 +25 -20 +10 +15 +10 +8 -30 Crosstalk (dB) +9 +20 Phase (deg) VDD =5V Cin =2.2µF RL=8Ω PO=0.13W AMP mode +5 -40 -50 -60 -70 VDD =5V RL=4Ohm (AMP) RL=10kΩ(HP) Cin=2.2µF (AMP) PO=1.5W(AMP) AMP (active) mode HP Mode Right(AMP) to Right(HP) Left(AMP) to Left(HP) Left(AMP) to Right(HP) -80 -90 Phase +7 -100 +0 -110 +6 10 100 1k 10k 20k 1k 100 Frequency (Hz) Gain (dB) 10k 20k 100µ +0 -10 1k Frequency (Hz) 10k -5 100k 200k -120 20 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Right(AMP) to Left(HP) 9 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) AMP Attenuation vs. Frequency AMP Attenuation vs. Frequency +0 AMP Attenuation (dB) -20 -30 VDD =5V RL=4Ω Cin=2.2µF VO=2Vrms(f in=1kHz, AMP enable) AMP mode (disable) VDD =5V RL=8Ω Cin=2.2µF VO=2Vrms(fin=1kHz,AMP enable) AMP mode (disable) -10 -20 AMP Attenuation (dB) -10 +0 -40 -50 -60 -70 -80 -90 -100 -30 -40 -50 -60 -70 -80 -90 -100 -110 -110 -120 20 1k 100 -120 10k 20k 20 Frequency (Hz) Shutdown Attenuation vs. Frequency -20 -30 -40 Shutdown Attenuation vs. Frequency +0 VDD =5V VDD =5V RL=4Ω Cin=2.2µF VO=1Vrms(fin=1kHz) Shutdown active AMP mode Shutdown Attenuation (dB) Shutdown Attenuation (dB) +0 -10 -50 -60 -70 -80 -90 -100 -10 RL=8Ω -20 Cin=2.2µF VO=1Vrms(fin=1kHz) -30 Shutdown active -40 AMP mode -50 -60 -70 -80 -90 -100 -110 -110 -120 20 100 1k -120 20 10k 20k 100 Input Voltage vs. Output Voltage 3.5 Output Voltage (Vrms) Output Voltage (Vrms) VDD =5V RL=4Ω Cin=2.2µF fin=1kHz AMP mode 2 1.5 1 0.5 0 10k 20k Input Voltage vs. Output Voltage 4 3.5 2.5 1k Frequency (Hz) Frequency (Hz) 3 10k 20k 1k 100 Frequency (Hz) 3 VDD =5V RL=8Ω Cin=2.2µF fin=1kHz AMP mode 2.5 2 1.5 1 0.5 0.3 0.6 0.9 1.2 0 1.5 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 0.3 0.6 0.9 1.2 1.5 Input Voltage (Vrms) Input Voltage (Vrms) 10 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) THD+N vs. Output Voltage THD+N vs. Output Power 10 T 10 VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode RL=300Ω THD+N (%) THD+N (%) VDD =5V HVDD=3.3V fin=1kHz Cin=3.3µF 1 BW<80kHz HP mode RL=32Ω 0.1 RL=16Ω 1 fin=20kHz 0.1 0.01 fin=20Hz RL=10kΩ 0.001 0 0.5 1 1.5 2 2.5 fin=1kHz 0.01 1m 3 10m Output Voltage (Volt) THD+N vs. Output Power 10 1 THD+N (%) THD+N (%) THD+N vs. Frequency 10 VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode 1 Stereo, in phase 0.1 300m 100m Output Power (W) VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=125mW HP mode BW<80kHz 0.1 Stereo, 180O out of phase BW<22kHz 0.01 Mono 0.01 0 50m 100m 150m 200m 0.005 20 250m 100 Output Power (W) 100µ VDD=5V Output Noise Voltage (Vrms) -10 HVDD=3.3V RL=16Ω -20 Rin=39kΩ Cin=3.3µF Crosstalk (dB) 10k 20k Output Noise Voltage vs. Frequency Crosstalk vs. Frequency +0 1k Frequency (Hz) -30 PO=125mW HP mode -40 -50 -60 -70 Right to Left -80 Right channel Left channel 10µ Left to Right -90 -100 20 100 1k 1µ 20 10k 20k 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 VDD =5V HVDD =3.3V RL=16Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode 11 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) Frequency Response THD+N vs. Output Power +0.2 +190 +180 VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=28mW HP mode -0.1 -0.2 10 THD+N (%) Phase -0 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode +185 Gain Phase (deg) Gain (dB) +0.1 10 1 fin=20kHz 0.1 +175 fin=20Hz 1k 100 fin=1kHz +170 100k 200k 10k 0.01 1m THD+N (%) 1 THD+N vs. Frequency THD+N vs. Output Power 10 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode 1 THD+N (%) 10 Stereo, 180O out of phase 0.1 100m 200m 10m Output Power (W) Frequency (Hz) Stereo, in phase 0.1 BW<80kHz BW<22kHz 0.01 Mono 0.01 0 50m 100m 0.001 20 200m 150m 100 Output Power (W) Crosstalk vs. Frequency Output Noise Voltage vs. Frequency -30 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode Output Noise Voltage (V) Crosstalk (dB) -20 -40 -50 -60 -70 Right to Left Right channel Left channel 10µ -80 Left to Right -90 -100 20 10k 20k 100µ +0 -10 1k Frequency (Hz) 100 1k 1µ 20 10k 20k 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode 12 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) Frequency Response THD+N vs. Output Voltage +190 +0.2 +0.1 +185 +180 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=13mW HP mode -0.1 +175 0.1 fin=20kHz fin=20Hz 0.01 fin=1kHz -0.2 10 THD+N (%) Phase -0 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode 1 Phase (deg) Gain (dB) 10 Gain 100 1k 10k +170 100k 200k 0.001 0 0.5 THD+N vs. Frequency 2.5 3 Crosstalk vs. Frequency +0 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -10 -20 -30 Crosstalk (dB) THD+N (%) 2 Output Voltage (Vrms) 10 1 1.5 1 Frequency (Hz) 0.1 -50 -60 -70 -80 Right to Left -90 Right Channel 0.01 -40 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -100 -110 Left Channel -120 0.001 20 100 1k 10k 20k Left to Right 20 100 Frequency (Hz) Frequency Response Output Noise Voltage vs. Frequency 100µ +195 +0.4 +0.2 Left channel 10µ 1µ 20 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode +190 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode +0 +185 Phase (deg) Gain Right channel Gain (dB) Output Noise Voltage (Vrms) 10k 20k 1k Frequency (Hz) Phase -0.2 100 1k 10k -0.4 20k 10 100 1k 10k +175 100k 200k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 +180 13 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) THD+N vs. Output Voltage THD+N (%) 1 THD+N vs. Frequency 10 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF BW<80kHz HP mode VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode 1 THD+N (%) 10 0.1 fin=20Hz fin=20kHz 0.01 0.1 Right channel 0.01 Left channel fin=1kHz 0.001 0 0.5 1 1.5 2 2.5 0.001 20 3 Output Voltage (Volt) -40 -50 Output Noise Voltage (Vrms) -30 Crosstalk (dB) Output Noise Voltage vs. Frequency 100µ VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -20 -60 -70 -80 Left to Right -90 -100 Right to Left -110 -120 -130 20 100 1k Right channel Left channel 10µ 1µ 10k 20k VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF A-weighting HP mode 20 100 Frequency (Hz) +0.4 +0 -10 Gain +185 Phase -0.2 Crosstalk (dB) -20 +190 Phase (deg) VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode +0 10k 20k Crosstalk vs. Frequency +195 +0.2 1k Frequency (Hz) Frequency Response Gain (dB) 10k 20k 1k Frequency (Hz) Crosstalk vs. Frequency +0 -10 100 -30 -40 -50 -60 -70 +180 VDD =5V HVDD=3.3V RL=16Ω (HP) RL=8Ω(AMP) Rin=39kΩ(HP) Cin=3.3µF (HP) PO=125mW(HP) AMP (active) mode HP Mode Left (HP) to Left (AMP) Right (HP) to Left (AMP) -80 -90 -0.4 10 100 1k 10k +175 100k 200k -100 20 100 Right (HP) to Right (AMP) 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Left (HP) to Right (AMP) 14 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) HP Attenuation vs. Frequency +0 -20 -30 -20 -40 -50 -60 -70 -80 -90 -40 -50 -60 -70 Right channel Right channel -100 20 1k 100 10k 20k Frequency (Hz) 20 -30 -40 -50 -20 -60 -70 -80 -90 -100 Left channel -110 -120 -130 -30 -40 -50 -60 -70 -80 -100 -110 -130 100 Left channel -90 Right channel -120 Right channel -140 20 10k 20k 1k 20 20k Input Voltage vs. Output Voltage 3 VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode Output Voltage (Vrms) Mono Stereo, in phase 1.5 1 0.5 0 10k Frequency (Hz) Input Voltage vs. Output Voltage 2 1k 100 Frequency (Hz) 2.5 20k VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(f in=1kHz) Shutdown active HP mode -10 Shutdown Attenuation (dB) -20 10k Shutdown Attenuation vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz) Shutdown active HP mode -10 1k 100 Frequency (Hz) Shutdown Attenuation vs. Frequency +0 Output Voltage (Vrms) Left channel -90 -120 Shutdown Attenuation (dB) -30 -80 Left channel -100 -110 VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(f in=1kHz HP enable) HP mode (disable) -10 HP Attenuation (dB) -10 HP Attenuation (dB) HP Attenuation vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz HP enable) HP mode (disable) VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode 2.5 2 Mono Stereo, in phase 1.5 1 0.5 0 0.5 1 1.5 2 0 2.5 0.5 1 1.5 2 2.5 3 Input Voltage (Vrms) Input Voltage (Vrms) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 0 15 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) Input Voltage vs. Output Voltage Output Voltage (Vrms) 2.5 2 Input Voltage vs. Output Voltage 3 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode 2.5 Stereo, in phase 1.5 1 0.5 0 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3µF fin=1kHz HP mode Mono Output Voltage (Vrms) 3 2 Mono & Stereo, in phase 1.5 1 0.5 0 0.5 1 1.5 2 2.5 0 3 0 0.5 1 Input Voltage (Vrms) PSRR vs. Frequency +0 VDD=5V -10 RL=4Ω -10 Cin=2.2µF -20 Vrr=200mVrms -20 -30 -30 -40 -40 PSRR (dB) PSRR (dB) AMP mode -50 -60 Right channel -50 -60 Right channel 100 1k Left channel -90 Vrr: Ripple Voltage on VDD -100 20 -100 10k 20k Vrr: Ripple Voltage on VDD 20 100 Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode -10 -20 -30 PSRR (dB) PSRR (dB) -30 -40 -50 -60 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode -40 -50 -60 -70 -70 Left channel -80 -90 -100 10k 20k 1k Frequency (Hz) -20 3 VDD =5V RL=8Ω Cin=2.2µF Vrr=200mVrms AMP mode -80 Left channel -90 -10 2.5 -70 -80 +0 2 PSRR vs. Frequency +0 -70 1.5 Input Voltage (Vrms) Right channel 20 100 Left channel -80 -90 Right channel Vrr: Ripple Voltage on HVDD 1k -100 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 20 100 Vrr: Ripple Voltage on HVDD 1k 10k 20k Frequency (Hz) 16 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage 50 20 16 *HP Mode disable HVDD=3.3V IHVDD=0.15mA 14 12 10 8 **AMP Mode disable VDD=5V IVDD=12mA 6 Amp mode HP mode No Load AMP Mode No Load Shutdown Current (µA) Supply Current (mA) 18 4 40 ISD(VDD) 30 20 10 ISD(HVDD) HP Mode 2 3.0 4.5 3.5 4.0 Supply Voltage (Volt) 5.0 0 5.5 3.0 Power Dissipation vs. Output Power 4.0 4.5 5.0 Supply Voltage (Volt) 5.5 Power Dissipation vs. Output Power 400 1.4 350 1.2 RL=16Ω RL=4Ω Power Dissipation (mW) Power Dissipation (W) 3.5 1.0 0.8 0.6 RL=8Ω 0.4 VDD =5V THD+N <1% AMP mode 0.2 0.0 0.0 0.5 1.0 300 250 RL=32Ω 200 150 100 0 0 2.0 1.5 VDD =5V HVDD=3.3V THD+N <1% HP mode 50 50 Output Power (W) 150 100 200 Output Power (mW) Output Power vs. Load Resistance & Output Power vs. Load Resistance 250 Mono, THD+N=10% 200 VDD =5V HVDD=3.3V fin=1kHz BW<80kHZ HP mode 150 100 Mono, THD+N=1% 250 150 100 50 0 0 100 CF=CCO=1µF THD+N=1%; Stereo, in phase CF :Charge pump flying capacitor CCO:Charge pump output capacitor 10 1000 Load Resistance (Ω) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 CF=CCO=1µF THD+N=1%; Mono 200 50 10 VDD =5V fin=1kHz BW<80kHZ HP mode CF=CCO=2.2µF THD+D=1%; Mono & Stereo, in phase 300 Output Power (mW) Output Power (mW) Charge Pump Capacitance 350 300 20 30 40 50 60 70 80 90 100 Load Resistance (Ω) 17 www.anpec.com.tw APA2057A Typical Operating Characteristics (Cont.) Input Resistance vs. Amplifier's Gain Input Resistance (kΩ)_AMP Mode 37.5 VDD =5V fin=1kHz BW<80kHZ No Load AMP mode 35.0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 Gain (dB)_AMP Mode Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 18 www.anpec.com.tw APA2057A Operating Waveforms Output Transient at Turn On VDD Output Transient at Shutdown Release 5V/div HP_Out 5V/div SD 10mV/div HP_Out 10mV/div AMP_Out AMP_Out 20mV/div ((Out+)-(Out-)) 20mV/div ((Out+)-(Out-)) 20ms/div 20ms/div Output Transient at Turn Off Output Transient at Shutdown Active VDD 5V/div HP_Out 5V/div SD HP_Out 10mV/div 10mV/div AMP_Out AMP_Out 20mV/div ((Out+)-(Out-)) 200ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 20mV/div ((Out+)-(Out-)) 20ms/div 19 www.anpec.com.tw APA2057A Pin Description PIN NAME NO. FUNCTION TSSOP-28 TQFN5x5-28 1 25 VDD Power supply for control section 2 26 GND Ground 3 27 INR_A 4 28 INR_H Right channel input terminal for headphone driver 5 1 INL_A Left channel input terminal for speaker amplifier Right channel input terminal for speaker amplifier 6 2 INL_H Left channel input terminal for headphone driver 7,23 3,19 PGND Power ground 8 4 LOUT+ Left channel positive output for speaker 9 5 LOUT- Left channel negative output for speaker 10,20 6,16 PVDD Power amplifier power supply 11 7 CVDD Charge pump power supply 12 8 CP+ 13 9 CGND 14 10 CP- 15 11 CVSS Charge pump output, connect to the “HVSS” 16 12 HVSS Headphone amplifier negative power supply 17 13 HP_R Right channel output for headphone 18 14 HP_L Left channel output for headphone 19 15 HV DD Headphone amplifier positive power supply 21 17 ROUT- Right channel negative output for speaker 22 18 ROUT+ Right channel positive output for speaker 24 20 HP_EN Headphone driver enable pin, pull high to enable headphone mode 25 21 BIAS Bias voltage generator It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix gain and pull low to 0V, the APA2057A enter shutdown mode. ISD = 80µA 26 22 SET 27 23 AMP_EN 28 24 BEEP Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Charge pump flying capacitor positive connection Charge pump ground Charge pump flying capacitor negative connection Speaker driver enable pin, pull low to enable speaker mode PC BEEP Trigger signal input 20 www.anpec.com.tw APA2057A Block Diagram ROUT+ INR_A ROUTInternal gain setting LOUT+ INL_A LOUTSET SET BIAS AMP_EN SPK EN BEEP HP_EN BEEP detect Rf(HP_R) HP EN *40kΩ INR_H HP_R Rf(HP_L) *40kΩ INL_H HP_L CVDD HVDD CP+ CP- Charge Pump Power Mamagement PVDD VDD CGND CVSS HVSS PGND GND * The internal Rf's value has 10% variation by process Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 21 www.anpec.com.tw APA2057A Typical Application Circuit ROUT+ R_CH Ci(AMP_R) R_ch INR_A 4Ω for AMP 2.2µF Ci(AMP_L) L_ch ROUT- Internal gain setting LOUT+ L_CH INL_A for AMP 4Ω 2.2µF VDD(5V) LOUT- 10kΩ R1 SET 10nF SET 2.2µF BIAS Shutdown AMP_EN R# 0.47µF BEEP HP_EN SET 3.3µF BEEP Detect CB Rf(HP_R) INR_H Ci(HP_R) Rf(HP_L) Sleeve Ri(HP_R) Ri(HP_L) L_ch Ring HP_R 39kΩ Ci(HP_L) Pull-high HP_EN to enable headohone driver HP EN *40kΩ 510kΩ 0.47nF Recommended for de-pop R_ch for HP SPK EN Tip *40kΩ INL_H Headphone Jack HP_L for HP 3.3µF 39kΩ VDD(5V) VDD(5V) CVDD CCPB CCPF CP+ 1µF 1µF CP- Power Mamagement Charge Pump PVDD VDD CGND CS(VDD) VSS R#: For the gain setting of speaker driver that , you need, refer to the Gain Setting Table s recommended voltage, and setting this voltage , at SET pin s voltage =5R#/(R#+10k). R1<=25kΩ. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 HVDD(3.3V) HVDD CCPO PGND GND CS(PVDD) 0.1µF 10µF CS(HVDD) 0.1µF 0.1µF VSS 1µF 22 www.anpec.com.tw APA2057A Application Information Headphone Mode Operation Amplifier Mode Operation The APA2057A has two pairs of operational amplifiers internally, which allows different amplifier configurations. HVDD VOUT - OUT+ + Pre-amplifier Output signal HVDD/2 GND OP1 Conventional Headphone amplifier Vbias HVDD - VOUT DIFF_AMP_CONFIG + OUT- GND OP2 Figure 1: APA2057A Internal Configuration (each channel) The OP1 and OP2 are all differential drive configurations. The differential drive configurations doubling the voltage VSS Cap-free Headphone amplifier Figure 2: Cap-free Operation swing on the load. Compare with the single-ending configuration, the differential gain for each channel is 2X The APA2057A’s headphone amplifiers uses a charge pump to invert the positive power supply (CVDD) to negative power supply (CV SS), see Figure2. The headphone amplifiers operate at this bipolar power supply (HVDD & VSS), and the outputs reference refers to the ground. This feature eliminates the output capacitor which is using in conventional single-ended headphone amplifier. The internal supply voltage of the headphone amplifier comes from HVDD and VSS. For good AC performance, the HVDD connected to 3.3V is recommended. It can avoid the output over voltage for line out application. (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to all differential mode is established. All differential mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to the ground. A differential amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus, it is doubling the output swing for a specified supply voltage. The output power can be Charge Pump Flying Capacitor 4 times greater than the SE amplifier working under the same condition. A differential configuration, similar as the The flying capacitor (CCPF) affects the load transient of the charge pump. If the capacitor’s value is too small, and then that will degrade the charge pump’s current driver capability and the performance of headphone amplifier. one used in APA2057A, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, it’s not necessary for DC voltage to be across the load. This Increasing the flying capacitor’s value will improve the load transient of charge pump. It is recommended to use the low ESR ceramic capacitors (X7R type is recommended) above 1µF. eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 23 www.anpec.com.tw APA2057A Application Information (Cont.) Charge Pump Output Capacitor drive. Both amplifier and headphone “ON” mode: Pull low • The output capacitor (C CPO)’s value affects the power ripple directly at CVSS(VSS). Increasing the value of output capacitor reduces the power ripple. The ESR of output capacitor affects the load transient of CVSS(V SS ). Lower ESR and greater than 1µf ceramic capacitor (X7R type is recommended) is a recommendation. the AMP_EN and pull high the HP_EN control pins, then turn on both speaker drivers and headphone drivers Both amplifier and headphone “OFF” mode: Pull • high the AMP_EN and pull low the HP_EN control pins, then turn off both speaker drivers and head- Charge Pump Bypass Capacitor phone drivers The bypass capacitor (CCPB) relates with the charge pump switching transient. The capacitor’s value is the same as flying capacitor (1µF). Place it close to the CVDD and PGND. If the AMP_EN and HP_EN are connected together, this pin will be connected to headphone jack’s control pin (Figure 3), the APA2057A is switchable between “Amplifier mode (Headphone mute), or Headphone mode Headphone Detection Input HP_R (Amplifier mute). Control pin Ring Gain Setting 1kΩ The gain for speaker drivers can be adjusted by applying DC voltage to SET pin. The APA2057A control consists of HPD_Switch HP_EN HP_L 19 step gain settings from 2.0V to 4.2V, and the gain is from -7dB to 16dB. Each gain step corresponds to a spe- 1kΩ cific input voltage range, as shown in “Gain Setting Table”. To minimize the effect of noise on the gain setting control, Sleeve Tip Headphone Detection which can affect the selected gain level, hysteresis and clock delay are implemented. For the highest accuracy, Headphone Jack with swich Figure 3 HPD Configurations The HP_EN will detect the voltage. If the voltage is the voltage shown in the “recommended voltage” column of the table is used to select a desired gain. This less than 0.8V, the headphone amplifiers will be disabled; if the voltage is greater than 2V, the headphone amplifier recommended voltage is exactly halfway between the two nearest transitions. The amount of hysteresis corre- will be enabled. sponds to half of the step width, as shown in Figure 4. Apply 0V to SET pin will place the APA2057A into shut- In Figure 3, phone-jack with the control pin is used and connected to the HP_EN input from control pin. When a headphone plug is inserted, the HP_EN will pull high down mode, and when SD =5V, it allows the speaker driver at a fixed gain (AV=10.5dB). internally which enables headphone amplifiers; without headphone plug, the HP_EN is pulled to the GND. 20 10 Operation Mode Forward Backward 0 Gain (dB) The APA2057A amplifier has two pairs of independent amplifier. One for stereo speaker is BTL structure, and the other for headphone is cap-less structure. Each pair has independent input pin; INR_A and INA_L are for stereo speaker drivers, and INR_H and INL_H are for -10 -20 -30 -40 stereo headphone drivers. -50 • Amplifier mode operation: Pull low the AMP_EN control pin can enable the stereo speaker driver. -60 • Headphone mode operation: Pull high the HP_EN control pin can enable the cap-less headphone Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 -70 0.0 1.0 2.0 3.0 4.0 5.0 DC Volume (V) Figure 4: APA2057A Gain setting vs. SET pin Voltage 24 www.anpec.com.tw APA2057A Application Information (Cont.) is important to confirm the capacitor polarity in the application. Gain Setting (Cont.) For headphone driver, the internal feedback resistor is 40kΩ (Rf(HP) external, 10% variation by process), therefore, the headphone driver’s gain is set by the input resistor (Ri(HP) external), the Table 1 lists the reference gain settings with external resistor for headphone driver (HP Mode). Note: The headphone dirver’s input is ground reference, so please check the Ci(HP)’s polarized at design. Effective Bias Capacitor, CB As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply HP Mode Gain Setting Table for Reference Ri(HP),external *Rf(HP),internal HP OUT (V/V) HP Gain(dB) (kΩ) (kΩ) 62 40 0.65 -3.8 50 40 0.80 -1.9 39 40 1.03 0.2 30 40 1.33 2.5 24 40 1.67 4.4 20 40 2.00 6.0 *The internal Rf's value has 10% variation by process. Table 1: Gain Setting Table for Reference rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor is improved PSRR due to increased 1.8V bias voltage stability. Typical applications employ a 5V regulator with 2.2µF and a 0.1µF bypass capacitor, which aids in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2057A. The selection of bypass capacitors, espe- Input Capacitor, Ci cially CB, is dependent upon desired PSRR requirements and click-and-pop performance. In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the Power Supply Decoupling, Cs The APA2057A is a high-performance CMOS audio amplifier minimum input impedance Ri from a high-pass filter with the corner frequency are determined by the following that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) equation: F C (highpass) = 1 is as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length (1) (2 πR i(MIN) ×C i ) The value of Ci must be considered carefully because it directly affects the low frequency performance of the between the amplifier and the speaker. The optimum decoupling is achieved by using two different types circuit. Consider the example where R i is 10kΩ and the specification calls for a flat bass response down to of capacitor that target on different types of noise on the power supply leads. For higher frequency transients, 10Hz. Equation is reconfigured as below: 1 Ci = (2 πR iFc) spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically (2) 0.1µF, is placed as close as possible to the device VDD lead works best (the pin1 (VDD) and pin2 (GND)’s capaci- When the input resistance variation is considered, the Ci is 1.6µF, so a value in the range of 2.2µF to 3.3µF would tor must short less than 1cm). For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of be chosen. A further consideration for this capacitor is the leakage path from the input source through the input 10µF or greater is placed near the audio power amplifier is recommended. network (R i+R f , Ci ) to the load. This leakage current creates a DC offset voltage at the input to the amplifier Shutdown Function that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or In order to reduce power consumption while not in use, the APA2057A contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor turns the amplifier off when a logic low is placed on the SET pin. The trigger point between a logic high and logic should face the amplifiers’ input becaue the DC level of the amplifiers’input is held at VDD/2. Please note that it Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 25 www.anpec.com.tw APA2057A Application Information (Cont.) power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as Shutdown Function (Cont.) low level is typically 2.0V. It is the best to switch between the ground and the supply VDD to provide maximum power to the load is increased resulting in nearly flat internal power dissipation over the normal operating device performance. range. Note that the internal dissipation at full output power is less than in the half power range. Calculating By switching the SET pin to low, the amplifier enters a low-current consumption state, I DD<80µA. Even the the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with APA2057A is in the shutdown mode, PC_BEEP will keep detecting circuit. In normal operating, SET pin is pulled to 8W loads and a 5V supply, the maximum draw on the power supply is almost 3W. high level to keep the IC out of the shutdown mode. The SET pin should be tied to a definite voltage to avoid un- Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 by the operational amplifier’s offset. 0.50 47.62 0.21 2.83 0.55 PC-BEEP Detection 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 wanted state changes. The wake-up time of shutdown is about 150ms, and the shutdown release’s pop is caused The APA2057A integrates a PCBEEP circuit detection for notebook PC using. When PC-BEEP signal drives to **High peak voltages cause the THD D+N to increase. to increase Table 2. Efficiency vs. Output Power in 5-V/8W Differential Amplifier Systems. PCBEEP input pin, PCBEEP mode is active. The APA2057A will turn on speaker drivers and the internal gain is fixed A final point to remember about linear amplifiers is how as 0dB. The PCBEEP signal becomes the amplifiers input signal. If the amplifiers in the shutdown mode, it will to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in equation, be out of the shutdown mode whenever PCBEEP mode is enabled. The APA2057A will return to previous setting VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, using the effi- when it is out of the PC BEEP mode. The input impedance is 100kΩ on PCBEEP input pin. ciency analysis to choose the correct supply voltage and speaker impedance for the application. Speaker Driver Amplifier Efficiency Power Dissipation An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation 8 states the maximum power dissipation point for a SE supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = PO Psup mode operating at a given supply voltage and driving a specified load. SE mode: (3) Where: V rms * VOrms (V * VP ) PO = O = P RL 2RL VP VOrms = 2 2VP Psup = VDD * IDD (AVG) = VDD * πRL VDD 2 2π2RL (8) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- (4) sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. (5) BTL mode: PD,MAX = (6) 4VDD 2 (9) 2π2RL Since the APA2057A is a dual channel power amplifier, Efficiency of a Differential configuration: the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. (V * V ) PO 2VP πRL (7) = P P / VDD * = Psup 2RL πRL 4VDD Table 1 calculates efficiencies for four different output Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 PD,MAX = Even with this substantial increasing in power dissipation, the APA2057A does not require extra heatsink.The power 26 www.anpec.com.tw APA2057A Application Information (Cont.) Power Dissipation (Cont.) Via diameter =15mil X10 70 mil dissipation from equation 9, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation 9: T -T PD,MAX = J,MAX A θJA Via diameter =25mil X4 120 mil 180 mil 70 mil 15 mil (10) For TSSOP-28 package with thermal pad, the thermal resistance (θJA) is equal to 45oC/W. 240 mil Since the maximum junction temperature (TJ,MAX) of APA2057A is 150°C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation that the IC package is able to handle can be obtained from equation10. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (R L) must be increased or the ambient temperature 12mil Exposed for thermal PAD connected Ground plane for ThermalPAD should be reduced. Figure 5: TSSOP-28P Layout Recommendation Thermal Pad Consideration The thermal pad must be connected to the ground. Thermal Consideration The package with thermal pad of the APA2057A re- Linear power amplifiers dissipate a significant amount quires special attention on thermal design. If the thermal design issues are not properly addressed, the of heat in the package under normal operating conditions. In the Power Dissipation vs. Output Power graph, the APA2057A 4Ω will go into thermal shutdown when driving a 4Ω load. The thermal pad on the bottom of the APA2057A APA2057A is operating at a 5V supply and a 4Ω speaker that 2W output power peaks are available. The vertical should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad axis gives the information of power dissipation (PD) in the IC with respect to each output driving power (PO) on the through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of horizontal axis. This is valuable information when attempting to estimate the heat dissipation of the IC requirements for the ampli- 15 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For fier system. good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat Using the power dissipation curves for a 5V/4Ω system, the internal dissipation in the APA2057A and maximum ambient temperatures is shown in Table 3. away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25°C, a larger Peak output power (W) Average output power (W) shutdown temperature (150°C). 2 1.95 1.25 37 In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of 2 1.17 1.25 37 2 0.74 1.19 43 thermal shutdown. See Demo Board Circuit Layout as an example for PCB layout. 2 0.43 1.05 55 2 0.19 0.8 78 copper plane or forced-air cooling will be required to keep the APA2057A junction temperature below the thermal Power Max. TA (°C) dissipation (W/channel) With thermal pad Table 3: APA2057A Power information, 5V/4Ω, Stereo, Differential mode Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 27 www.anpec.com.tw APA2057A Application Information (Cont.) Thermal Consideration (Cont.) Package θJA TSSOP-28 45°C/W TQFN -28 43°C/W Table 4: Thermal resistance Table This parameter is measured with the recommended copper heat sink pattern on a 2-layer PCB, 23cm 2 in 5. 7mmx4mm in PCB, 2oz. Copper, 100mm2 coverage. Airflow 0 CFM the maximum ambient temperature depends on the heat sink ability of the PCB system. To calculate maximum ambient temperatures, first consideration is that the numbers from the dissipation graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJ,Max), and the total intemal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2057A is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graph. TA,Max = TJ,Max - θJAPD (11) 150 - 45(0.8x2) = 78°C (with thermal pad) NOTE: Internal dissipation of 0.8W is estimated for a 2W system with 15-dB headroom per channel. Table 3 shows that for some applications, no airflow is required to keep junction temperatures in the specified range. The APA2057A is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent IC from damage. The information in table 3 was calculated for maximum listen volume with limited distortion. When the output level is reduced, the numbers in the table change significantly. Also, using 8Ω speakers will dramatically increase the thermal performance by increasing amplifier efficiency. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 28 www.anpec.com.tw APA2057A Package Information TSSOP-28P D SEE VIEW A E2 EXPOS ED PAD E1 E D1 c 0.25 b S Y M B O L VIEW A L GAUGE PLANE SEATING PLANE 0 A1 A2 A e TSSOP-28P INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 9.60 9.80 0.378 0.386 D1 4.50 6.00 0.177 0.236 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 e 0.65 BSC L 0.45 0 0o 0.026 BSC 0.75 0.018 8o 0o 0.030 8o Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 29 www.anpec.com.tw APA2057A Package Information TQFN5x5-28 D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TQFN5x5-28 S Y M B O L A MIN. MAX. MIN. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.18 0.30 0.007 0.012 D 4.90 5.10 0.193 0.201 D2 3.50 3.80 0.138 0.150 E 4.90 5.10 0.193 0.201 E2 3.50 3.80 0.138 0.150 0.45 0.014 A3 b INCHES MILLIMETERS 0.20 REF e 0.008 REF 0.020 BSC 0.50 BSC L 0.35 K 0.20 MAX. 0.018 0.008 Note : 1. Followed from JEDEC MO-220 WHHD-3. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 30 www.anpec.com.tw APA2057A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSSOP-28P Application TQFN5x5-28 A H 330.0±2.00 50 MIN. P0 P1 4.00±0.10 8.00±0.10 A H 330.0±2.00 50 MIN. P0 P1 4.0±0.10 T1 C 16.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. W 16.0±0.30 1.75±0.10 P2 D0 D1 T A0 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 T1 C d D W 1.5 MIN. 20.2 MIN. 12.4+2.00 13.0+0.50 -0.00 -0.20 8.0±0.10 P2 D0 2.0±0.10 1.5+0.10 -0.00 E1 B0 F 7.50±0.10 K0 10.20.±0.20 1.50±0.20 E1 12.0±0.30 1.75±0.10 F 5.5±0.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 5.35±0.20 5.35±0.20 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity TSSOP- 28P Tape & Reel 2000 TQFN5x5-28 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 31 www.anpec.com.tw APA2057A Taping Direction Information TSSOP-28P USER DIRECTION OF FEED TQFN5x5-28 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 32 www.anpec.com.tw APA2057A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 33 www.anpec.com.tw APA2057A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 34 www.anpec.com.tw