ANPEC APW7300KAI-TRG

APW7301
3A 24V 340kHz synchronous Buck Converter
Features
General Description
•
Wide Input Voltage from 4.5V to 24V
•
3A Continuous Output Current
APW7301 is a 3A synchronous buck converter with integrated 85mΩ power MOSFETs. The APW7301 design
•
Adjustable Output Voltage from 0.925V to 20V
•
Intergrated High/Low Side MOSFET
•
PFM/PWM mode Operation
•
Fixed 340kHz Switching Frequency
•
Stable with Low ESR Ceramic Output Capacitors
•
Power-On-Reset Detection
•
Programmable Soft-Start
•
Over-Temperature Protection
•
Current-Limit Protection with Frequency Foldback
•
Enable/Shutdown Function
•
Small SOP-8P Package
•
Lead Free and Green Devices Available
with a current-mode control scheme, can convert wide
input voltage of 4.5V to 24V to the output voltage adjustable from 0.925V to 20V to provide excellent output voltage regulation.
The APW7301 is equipped with an automatic PFM/PWM
mode operation. At light load, the IC operates in the PFM
mode to reduce the switching losses. At heavy load, the
IC works in PWM.
The APW7301 is also equipped with Power-on-reset, softstart, and whole protections (over-temperature, and current-limit) into a single package.
This device, available SOP-8P, provides a very compact
system solution external components and PCB area.
(RoHS Compliant)
Applications
Pin Configuration
APW7301
•
LCD Monitor/TV
•
Set-Top Box
•
DSL, Switch HUB
•
Notebook Computer
BS
VIN
LX
GND
1
2
3
4
9
GND
8
7
6
5
SS
EN
COMP
FB
SOP-8P
(Top View)
Simplified Application Circuit
9
Exposed Pad
The pin 4 must be connected to the pin 9 (Exposed Pad)
VIN
APW7301
VOUT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
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APW7301
Ordering and Marking Information
Package Code
KA : SOP-8P
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7301
Assembly Material
Handling Code
Temperature Range
Package Code
APW7301 KA :
APW7301
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VIN
VIN Supply Voltage (VIN to GND)
VLX
LX to GND Voltage
EN, FB, COMP, SS to GND Voltage
Rating
Unit
-0.3 ~ 30
V
-1 ~VIN+0.3
V
-0.3 ~ 6
V
VBS
BS to GND Voltage
VLX-0.3 ~ VLX+6
V
PD
Power Dissipation
Internally Limited
W
TJ
Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
o
SOP-8P
75
SOP-8P
15
Junction-to-Case Resistance in Free Air (Note 3)
C/W
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2013
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APW7301
Recommended Operating Conditions (Note 4)
Symbol
Range
Unit
VIN Supply Voltage
4.5 ~ 24
V
VOUT
Converter Output Voltage
0.925~20
V
IOUT
Converter Output Current
TA
Ambient Temperature
VIN
TJ
Parameter
0~3
Junction Temperature
A
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 4 : Refer to the typical application circuit.
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA=25°C.
Symbol
Parameter
APW7301
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IVIN
IVIN_SD
VIN Supply Current
VFB=1V, VEN=3V, LX=NC
-
1.9
-
mA
VIN Shutdown Supply Current
VEN=0V
-
0.3
-
µA
3.8
4.05
4.4
V
-
0.3
-
V
0.9
0.925
0.943
V
300
340
380
kHz
POWER-ON-RESET (POR)
VIN POR Voltage Threshold
VIN Rising
VIN POR Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
Regulated on FB pin
OSCILLATOR AND DUTY CYCLE
FOSC
Oscillator Frequency
Foldback Frequency
VFB=0V
-
110
-
kHz
Maximum Converter’s Duty
VFB=0.925V
-
90
-
%
Minimum On Time
(Note 5)
-
220
-
ns
PFM MODE OPERATION
IPK_PFM
PFM Mode Current Limit
-
0.8
-
A
IPK_TH
PWM to PFM Inductor Peak Threshold
-
0.6
-
A
-
110
-
mΩ
-
-
10
µA
Error Amplifier Transconductance
-
820
-
µA/V
Error Amplifier Voltage Gain
-
80
-
V/V
Switch Current to COMP Voltage
Transresistance
-
5.2
-
A/V
POWER MOSFET
High/low Side MOSFET On Resistance
High/Low Side MOSFET Leakage
Current
VEN=0V, VLX=0V
CURRENT-MODE PWM CONVERTER
GEA
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APW7301
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA= 25°C.
Symbol
Parameter
APW7301
Test Conditions
Min.
Unit
Typ.
Max.
PROTECTIONS
ILIM
High Side MOSFET Current-Limit
-
5.6
-
A
TOTP
Over-Temperature Trip Point
Peak Current
-
160
-
°C
Over-Temperature Hysteresis
-
50
-
°C
Over-Voltage Protection
-
120
-
%
-
6
-
µA
2.2
2.5
2.7
V
-
100
-
mV
SOFT-START, ENABLE AND INPUT CURRENTS
ISS
Soft-Start Current
EN Under-Voltage Lockout (UVLO)
Threshold
VEN rising
EN UVLO Hysteresis
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APW7301
Typical Operating Characteristics
Efficiency vs. Output Current
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Efficiency vs. Output Current
60
50
VIN = 19V
40
30
VIN = 12V
20
VOUT = 1.2V
60
50
VOUT = 1.8V
40
30
VOUT = 2.5V
20
10
10
VOUT = 5V
0
0
0.001
0.01
0.1
1
10
0.001
0.01
Output Current (A)
1
10
Soft Start Time vs. SS pin to GND
Capacitance
80
1.90
TA=25oC
VIN =12V, VOUT =3.3V, TA=25oC,
The time of 10%~90%VOUT
70
1.85
Soft Start Time, tSS (ms)
VIN Supply Current, IVIN (mA)
0.1
Output Current (A)
VIN Supply Current vs. VIN Supply
Voltage
1.80
1.75
1.70
60
50
40
30
20
10
1.65
5
10
15
20
0
25
0
100
200
300
400
500
VIN Supply Voltage (V)
SS pin to GND Capacitance (nF)
EN UVLO Threshold Voltage vs.
VIN Supply Voltage
Reference Voltage vs. VIN Supply
Voltage
0.928
2.6
TA=25oC
2.5
Reference Voltage, VREF (V)
EN UVLO Threshold Voltage, VEN (V)
VIN = 12V
VOUT = 3.3V
2.4
VEN Rising
2.3
2.2
VEN Falling
2.1
2.0
0.927
0.926
0.925
0.924
0.923
5
10
15
20
25
5
VIN Supply Voltage (V)
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Rev. A.2 - Apr., 2013
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15
20
25
VIN Supply Voltage (V)
5
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APW7301
Typical Operating Characteristics
360
360
VIN = 12V
355
Switching Frequency, FOSC(kHz)
Switching Frequency, FOSC(kHz)
Switching Frequency vs. VIN
Supply Voltage
Switching Frequency vs.
Junction Temperature
350
345
340
335
330
325
320
358
356
354
352
350
-50
0
50
5
150
100
o
10
15
20
25
VIN Supply Voltage (V)
Junction Temperature ( C)
Reference Voltage vs. Junction
Temperature
0.941
Reference Voltage, VREF(V)
TA = 25oC
VIN = 12V
0.937
0.933
0.929
0.925
0.921
0.917
-50
0
50
100
150
o
Junction Temperature ( C)
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APW7301
Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power On
Power Off
V IN
VIN
VOUT
V OUT
1
1
2
2
IL
IL
3
3
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no
load
CH1: VIN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC
CH3: IL, 0.5A/Div, DC
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no
load
CH1: VIN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC
CH3: IL, 0.5A/Div, DC
TIME: 10ms/Div
TIME: 50ms/Div
Enable
Shutdown
VEN
VEN
1
1
VOUT
V OUT
2
2
IL
IL
3
3
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
RLOAD =2Ω
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
RLOAD =2Ω
CH1: VEN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC
CH3: IL, 2A/Div, DC
CH1: VEN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC
CH3: IL, 2A/Div, DC
TIME:50µs/Div
TIME: 5ms/Div
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APW7301
Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Normal Operation in Heavy
Load
Current Limit & Frequency
Foldback
VOUT
VOUT
1
VLX
VLX
1
3
2
IL
IL
2
3
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
IOUT =3A
CH1: VOUT , 2V/Div, DC
CH2: IL, 2A/Div, DC
CH3: VLX, 10V/Div, DC
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
Ramp up IOUT into current limit
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 2A/Div, DC
TIME: 2µs/Div
TIME: 50µs/Div
Normal Operation in Light
Load
Load Transient
VOUT
VLX
VOUT
1
1
3
IOUT
IL
2
2
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
IOUT =100mA
CH1: VOUT , 2V/Div, DC
CH2: IL, 1A/Div, DC
CH3: VLX, 10V/Div, DC
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
COMP=6.8kΩ+3.9nF, IOUT =300mA-3A-300mA
CH1: VOUT , 0.5V/Div, offset=3.3V
CH2: IOUT , 2A/Div, DC
TIME: 50µs/Div
TIME: 5µs/Div
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APW7301
Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Short Circuit
Load Transient
VOUT
VLX
VOUT
1
1
VLX
2
IOUT
IL
2
3
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
VOUT short to ground.
VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
COMP=6.8kΩ+3.9nF, IOUT =1A-3A-1A
CH1: VOUT , 2V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 5A/Div, DC
TIME: 10µs/Div
CH1: VOUT , 0.5V/Div, offset=3.3V
CH2: IOUT , 2A/Div, DC
TIME: 50µs/Div
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APW7301
Pin Description
PIN
FUNCTION
SOP-8P
Name
1
BS
High-Side Gate Drive Boost Input. BS supplies the voltage to drive the high-side N-channel
MOSFET. At least 10nF capacitor should be connected from LX to BS to supply the high side switch.
2
VIN
Power Input. VIN supplies the power (4.5V to 24V) to the control circuitry, gate drivers and step-down
converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between
VIN and GND eliminates switching noise and voltage ripple on the input to the IC.
3
LX
Power Switching Output. LX is the Drain of the N-Channel power MOSFET to supply power to the
output LC filter.
4
GND
5
FB
Output feedback Input. The APW7301 senses the feedback voltage via FB and regulates the voltage
at 0.925V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage
from 0.925V to 20V.
6
COMP
Output of the error amplifier. Connect a series RC network from COMP to GND to compensate the
regulation control loop. In some cases, an additional capacitor from COMP to GND is required.
7
EN
Enable Input. EN is a digital input that turns the regulator on or off. EN threshold is 2.5V with 0.2V
hysteresis. Pull up with 100kΩ resistor for automatic startup.
8
SS
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set
the soft-start period. A 0.1µF capacitor sets the soft-start period to 15ms. To disable the soft-start
feature, leave SS unconnected.
9
Exposed Pad
Connect the exposed pad to the system ground plan with large copper area for dissipating heat into
the ambient air.
Ground. Connect the exposed pad on backside to Pin 4.
Block Diagram
VIN
2
Current Sense
Amplifier
LOC
Over
Temperature
Protection
Power-OnReset
Current
Limit
5V
1 BS
POR
5V
OTP
6µA
120%VREF
SS 8
Gate
Driver
Fault
Logics
OVP
Inhibit
Gate
Control
3 LX
5V
FB 5
Gm
VREF
Current
Compartor
Error
Amplifier
Gate
Driver
COMP 6
2.5/2.3V
EN 7
UVLO
Enable
1.5V
Slope
Compensation
Internal
Regulator
5V
VIN
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Oscillator
340kHz/
110kHz
4 GND
LOC
FB
0.6V
Current Sense
Amplifier
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APW7301
Typical Application Circuit
VIN
4.5V~24V
C2
(option*)
C1
10µF
2
1
VIN
C3
10nF
BS
R4
100k
7
LX
EN
VOUT
3.3V/3A
3
L1
10µH
C4
22µFx2
APW7301
8
SS
6
C5
0.1µF
5
COMP
FB
R1
24K
GND
R3
6.8k
4
R2
9.1K
C6
3.9nF
* For cirtical condition, like plug in, the large capacitace and high voltage rating are needed to avoid the high spike
voltage.
Recommended Feedback Compensation Value
Vin(V)
VOUT(V)
L1(µH)
C4(µF)
R1(KΩ)
R2(KΩ)
R3(KΩ)
C6(nF)
24
5
10
22(Ceremic)
39
9.1
6.8
3.9
12
5
10
44 (Ceremic)
39
9.1
5
1.5
12
3.3
10
22 (Ceremic)
24
9.1
6.8
3.9
12
2.5
10
22 (Ceremic)
15
9.1
6.8
3.9
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APW7301
Function Description
Main Control Loop
Enable/Shutdown
The APW7301 is a constant frequency current mode
switching regulator. During normal operation, the inter-
Driving EN to ground places the APW7301 in shutdown.
When in shutdown, the internal N-Channel power MOSFET
nal N-channel power MOSFET is turned on each cycle
when the oscillator sets an internal RS latch and would
turns off, all internal circuitry shuts down and the quiescent supply current reduces to 0.3µA.
be turned off when an internal current comparator (ICMP)
resets the latch. The peak inductor current at which ICMP
Current-Limit Protection
resets the RS latch is controlled by the voltage on the
COMP pin, which is the output of the error amplifier
The APW7301 monitors the output current, flowing
through the N-Channel power MOSFET, and limits the
(EAMP). An external resistive divider connected between
VOUT and ground allows the EAMP to receive an output
IC from damages during overload, short-circuit and overvoltage conditions.
feedback voltage VFB at FB pin. When the load current
increases, it causes a slight decrease in VFB relative to
Frequency Foldback
the 0.925V reference, which in turn causes the COMP
voltage to increase until the average inductor current
The foldback frequency is controlled by the FB voltage.
When the FB pin voltage is under 0.6V, the frequency of
matches the new load current.
the oscillator will be reduced to 110kHz. This lower frequency allows the inductor current to safely discharge,
VIN Power-On-Reset (POR) and EN Under-voltage
Lockout
thereby preventing current runaway. The oscillator’s frequency will switch to its designed rate when the feedback
The APW7301 keep monitoring the voltage on VIN pin to
prevent wrong logic operations which may occur when
voltage on FB rises above the rising frequency foldback
VIN voltage is not high enough for the internal control
threshold (0.6V, typical) again.
circuitry to operate. The VIN POR has a rising threshold
of 4.05V (typical) with 0.3V of hysteresis.
Over-Voltage Protection
An external under-voltage lockout (UVLO) is sensed at
the EN pin. The EN UVLO has a rising threshold of 2.5V
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increase over 120% of the
reference voltage, the over-voltage protection compara-
with 0.2V of hysteresis. The EN pin should be connected
a resistor divider from VIN to EN .
tor will force the high-and low-side MOSFET gate driver
off. As soon as the output voltage is within regulation, the
After the VIN and EN voltages exceed their respective
voltage thresholds, the IC starts a start-up process and
OVP comparator is disengaged. The chip will restore its
normal operation.
then ramps up the output voltage to the setting of output
voltage.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction temperature of the APW7301 When the junction temperature exceeds TJ =+160oC, a thermal sensor turns off the power
MOSFET, allowing the device to cool down. The thermal
sensor allows the converter to start a start-up process
and regulate the output voltage again after the junction
temperature cools by 50oC.
The OTP designed with a 50 oC hysteresis lowers the
average T J during c ontinuous thermal overload
conditions, increasing life time of the IC.
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APW7301
Application Information
T=1/FOSC
Setting Output Voltage
The regulated output voltage is determined by:
R1
VOUT= 0.925 × (1 +
VLX
DT
I
IOUT
) ⋅ ( V)
R2
IL
To prevent stray pickup, please locate resistors R1 and
R2 close to APW7301.
IOUT
IQ1
I
ICOUT
Input Capacitor Selection
VOUT
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge current needed each time the N-channel power MOSFET
(Q1) turns on. Place the small ceramic capacitors physi-
VOUT
Figure 1. Converter Waveforms
cally close to the VIN and between the VIN and GND.
The important parameters for the bulk input capacitor are
In critical condition, like input voltage plug in, it will cause
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
the high spike voltage. It is recommended to place large
capacitance and higher voltage rating to reduce the spike
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage. In general, to parallel a electrolytic capacitor with
large capacitance can reduce the spike voltage in critical
voltage rating should be at least 1.25 times greater than
the maximum input voltage and a voltage rating of 1.5
condition. This electrolytic capacitor must also be short
pin wire to make it as close as to the power plane or trace.
times is a conservative guideline. The RMS current (IRMS)
of the bulk input capacitor is calculated as the following
equation:
VIN
VIN
CIN1
IRMS = IOUT D × (1 − D) ⋅ ( A )
CIN2
10uF/
MLCC
APW7301
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exer-
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements
cised with regard to the capacitor surge current rating.
are the function of the switching frequency and the ripple
current (DI). The output ripple is the sum of the voltages,
VIN
VIN
IQ1
having phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
CIN
Q1
ated as the following equations:
IL
LX
Q2
IOUT
VOUT
L
ICOUT
D =
V OUT
V IN
........... (1)
∆I =
V OUT × (1 − D )
F OSC × L
........... (2)
ESR
COUT
V ESR = ∆ I × ESR
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........... (3)
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APW7301
Application Information(Cont.)
Output Capacitor Selection (Cont.)
Inductor Value Calculation
The peak- to-peak voltage of the ideal output capacitor is
The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the
calculated as the following equations:
........... (4)
use of a smaller inductor for the same amount of inductor
ripple current. However, this is at the expense of efficiency
For the applications using bulk capacitors, the ∆VCOUT is
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
much smaller than the VESR and can be ignored. Therefore,
the AC peak-to-peak output voltage(∆VOUT) is shown below:
effect on ripple current.
Accepting larger values of ripple current allows the use of
∆VCOUT =
∆I
8 × FOSC × COUT
∆VOUT = ∆I × ESR ⋅ ( V )
low inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
........... (5)
For the applications using bulk capacitors, the VESR is
setting ripple current is ∆I< 0.4 x IOUT(max). Please be noticed that the maximum ripple current occurs at the maxi-
much smaller than the ∆V COUT and can be ignored.
Therefore, the AC peak-to-peak output voltage(∆VOUT) is to
mum input voltage. The minimum inductance of the inuctor is calculated by using the following equation:
∆VCOUT.
VOUT ·(VIN - VOUT)
≤ 1.2
340000 ·L ·VIN
The load transient requirements are the function of the
slew rate (di/dt) and the magnitude of the transient load
VOUT ·(VIN - VOUT)
408000 ·VIN
urrent. These requirements are generally met with a
mix of capacitors and careful layout. High frequency ca-
L≥
pacitors initially supply the transient and slow the current
where VIN = VIN(MAX)
load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR
Table2 Inductor Selection Guide
Vender
(Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements.
(H)
Part number
CYNTEC PCMB063T-100MS
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
........... (6)
Inductance DCR Current
(µH)
(mΩ) Rating(A)
10
62
4
Chilisin
MHCC10040-100M
10
30
6.5
Gausstek
PL94P051M-10U
10
38
3.8
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading.
Table1 Capacitor Selection Guide
Capacitance
Voltage
Vender
Model
TC
Si2e
Rating(V)
(µF)
muRata
GRM31CR61E106K
10
X5R
25
1206
muRata
GRM31CR61C226K
22
X5R
16
1206
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APW7301
Application Information (Cont.)
Thermal Consideration
1. Begin the layout by placing the power components first.
The APW7301 maximum power dissipation depends on
Orient the power circuitry to achieve a clean power flow
path. If possible, make all the connections on one side of
the thermal resistance and temperature difference between the die junction and ambient air. The power dissi-
the PCB with wide, copper filled areas.
2. In Figure 3, the loops with same color bold lines con-
pation PD across the device is:
duct high slew rate current. These interconnecting impedances should be minimized by using wide and short
PD = (TJ - TA) / θJA
where (TJ-TA) is the temperature difference between the
printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
junction and ambient air. θJA is the thermal resistance
between Junction and ambient air.
away from switching nodes (LX or others) on the PCB
and it should be placed near the IC as close as possible.
For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated
Therefore, place the feedback divider and the feedback
compensation network close to the IC to avoid switching
power dissipation should less than:
PD = (125-25)/75=1.33(W) --- (SOP-8P)
noise. Connect the ground of feedback divider directly to
the GND pin of the IC using a dedicated ground trace.
Maximum Power Dissipation, PD(W)
4. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground plane
2.5
to connect the C1, C2, and Schottky diode to provide a low
impedance path between the components for large and
2
high slew rate current.
1.5
+
VIN
1
-
SOP-8P
VIN BS
EN
0.5
Compensation
Network
C1
L1
C3
LX
+
U1
C2 Load VOUT
APW7301
COMP
0
0
25
50
75
100
-
R3
125
C5
Ambient Temperature, TA( oC)
FB
R1
GND
R2
Feedback
Divider
Figure 2. Current Path Diagram
Sensitive node (FB, COMP) should be away from
switching node(LX) and it should be placed near
the IC with short trace
Layout Consideration
In high power switching regulator, a correct layout is
5
6
4
3
Input Capacitor C1 should be
near the IC as close as possible
2
VOUT
L1
VIN
VLX
C1
lines indicating high current paths. Components along
the bold lines should be placed close together. Below is
SOP-8
1
combined using the ground plane construction or single
point grounding. Figure 3 illustrates the layout, with bold
Ground
APW7301
7
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separating and finally
Numerous vias connected from
the thermal pad to the
solderside ground plane(s)
should be used to enhance heat
dissipation
8
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
a checklist for your layout:
C2
Power path should be short and wide
Figure 3. Recommended Layout Diagram
Copyright  ANPEC Electronics Corp.
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APW7301
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
THERMAL
PAD
E1
E2
D1
c
A1
0.25
A2
A
b
e
GAUGE PLANE
SEATING PLANE
θ
L
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.60
0.063
0.000
0.15
0.006
A1
0.00
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
0.049
D1
2.50
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0o C
8oC
0
0oC
8o C
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
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APW7301
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
SOP-8P
W
E1
12.0±0.30 1.75±0.10
A0
B0
6.40±0.20 5.20±0.20
F
5.5±0.05
K0
2.10±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8P
Tape & Reel
2500
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APW7301
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
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APW7301
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW7301
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
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