27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified General Description Features The 27C16 is a high speed 16K UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. The 27C16 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device by following the programming procedure. This EPROM is fabricated with the reliable, high volume, time proven, P2CMOSTM silicon gate technology. The 27C16 specified on this data sheet is fully compliant with MIL-STD-883, Revision C. Y Y Y Y Y Y Y Y Y Y Access time down to 450 ns Low CMOS power consumption Ð Active Power: 26.25 mW max Ð Standby Power: 0.53 mW max (98% savings) Performance compatible to NSC800TM CMOS microprocessor Single 5V power supply Pin compatible to MM2716 and higher density EPROMs StaticÐno clocks required TTL compatible inputs/outputs TRI-STATEÉ output Windowed DIP Package Specifications guaranteed over full military temperature range (b55§ C to a 125§ C) Block Diagram Pin Names A0 – A10 Addresses CE Chip Enable OE Output Enable O0 –O7 Outputs PGM Program NC No Connect TL/D/10329 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NS800TM are P2CMOSTM trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/D/10329 RRD-B30M105/Printed in U. S. A. 27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified January 1989 Connection Diagram 27C256 27C128 27C64 27C32 27C32 27C64 27C128 27256 27256 27128 2764 2732 2732 2764 27128 27256 VPP VPP VPP A12 A12 A12 VCC VCC VCC PGM PGM A7 A7 A7 A7 A14 VCC NC A13 A6 A6 A6 A13 A6 A8 A8 A8 A5 A5 A8 A5 A5 A9 A9 A9 A4 A9 A4 A4 A4 A11 A11 A11 A11 A3 A3 A3 A3 OE/VPP OE OE OE A2 A2 A2 A2 A10 A10 A10 A10 A1 A1 A1 A1 CE CE CE CE A0 A0 A0 A0 O7 O7 O7 O7 O0 O0 O0 O0 O6 O6 O6 O6 O1 O1 O1 O1 O5 O5 O5 O5 O2 O2 O2 O2 O4 O4 O4 O4 GND GND GND GND O3 O3 O3 O3 Dual-In-Line Package 27C16Q TL/D/10329 – 2 Top View Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the 27C16 pins. Military Temp Range (b55§ C to a 125§ C) VCC e 5V g 10% Parameter/Order Number Access Time (ns) 27C16Q450/883 450 27C16Q550/883 550 2 Absolute Maximum Ratings (Note 1) Operating Conditions (Note 9) b 55§ C to a 125§ C Temperature Under Bias Storage Temperature Temperature Range (Tcase) VCC Power Supply (Notes 2 and 3) b 65§ C to a 125§ C All Input Voltages with Respect to Ground b 55§ C to a 125§ C 5V a 10% VPP Power Supply (Note 3) VCC a 6.5V to b 0.3V All Output Voltages with Respect to Ground (Note 11) VCC a 0.3V to GND b0.3V VPP Supply Voltage with Respect to Ground during Programming a 26.5V to b 0.3V Power Dissipation Lead Temperature (Soldering, 10 Seconds) 1.0W 300§ C READ OPERATION DC Electrical Characteristics Symbol Parameter Conditions Min Typ (Note 4) Max Units ILI Input Load Current VIN e VCC or VIL 10 mA ILO Output Leakage Current VOUT e VCC or VIL, CE e VIH 10 mA ICC1 (Note 3) VCC Current (Active) TTL Inputs OE e CE e VIL, f e 1 MHz Inputs e VIH or VIL, I/O e 0 mA 2 30 mA ICC2 (Note 3) VCC Current (Active) CMOS Inputs OE e CE e VIL, f e 1 MHz Inputs e VCC or GND, I/O e 0 mA 1 25 ICCSB1 VCC Current (Standby) TTL Inputs CE e VIH 0.1 1 mA ICCSB2 VCC Current (Standby) CMOS Inputs CE e VCC 0.01 0.1 mA VIL Input Low Voltage b 0.1 0.8 V VIH Input High Voltage 2.2 VCC a 1 V VOL1 Output Low Voltage IOL e 2.1 mA VOH1 Output High Voltage IOH e b400 mA VOL2 Output Low Voltage IOL e 0 mA VOH2 Output High Voltage IOH e 0 mA 0.45 2.4 mA V V 0.1 4.4 V V AC Electrical Characteristics 27C16 Symbol Parameter Conditions 450 Min tACC 550 Max Min Units Max Address to Output Delay CE e OE e VIL 450 550 ns tCE CE to Output Delay OE e VIL 450 550 ns tOE OE to Output Delay CE e VIL 120 120 ns tDF OE High to Output Float CE e VIL 100 ns tOH (Note 5) Output Hold from Addresses, CE or OE, Whichever Occurred First CE e OE e VIL 0 0 3 100 0 0 ns Capacitance TA e a 25§ C, f e 1 MHz (Note 5) Typ Max Units CIN Symbol Input Capacitance Parameter VIN e 0V Conditions 4 10 pF COUT Output Capacitance VOUT e 0V 8 12 pF AC Test Conditions Output Load Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level Inputs Outputs 1 TTL Gate and CL e 100 pF s 20 ns 0.8V to 2.2V 1V and 2V 0.8V and 2V AC Waveforms (Notes 2, 8, 9, 10) TL/D/10329 – 3 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Note 3: VPP may be connected to VCC except during programming. ICC1 s the sum of the ICC active and IPP read currents. Note 4: Typical values are for TA e a 25§ C and nominal supply voltages. Note 5: This parameter is only sampled and is not 100% tested. Note 6: OE may be delayed up to tACC b tOE after the falling edge of CE without impact on tACC. Note 7: The tDF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) b 0.10V Low to TRI-STATE, the measured VOL1 (DC) a 0.10V Note 8: TRI-STATE may be attained using OE or CE. Note 9: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.1 mF ceramic capacitor be used on every device between VCC and GND. Note 10: The 27C16 requires one address transition after initial power-up to reset the outputs. Note 11: The outputs must be restricted to VCC a 0.3V to avoid latch-up and device damage. 4 PROGRAMMING CHARACTERISTICS (Note 1) DC Programming Characteristics (Notes 2 & 3) (TA e a 25§ C g 5§ C, VCC e 5V g 10%, VPP e 25V g 1V) Symbol Parameter Conditions Max Units Input Current (for Any Input) VIN e VCC or GND 10 mA IPP VPP Supply Current during Programming Pulse CE/PGM e VIH 30 mA ICC VCC Supply Current 10 mA ILI Min Typ VIL Input Low Level b 0.1 VIH Input High Level 2.0 0.8 V VCC a 1 V AC Programming Characteristics (Notes 2 & 3) (TA e a 25§ C g 5§ C, VCC e 5V g 10%, VPP e 25V g 1V) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 2 ms tOES OE Setup Time 2 mS tDS Data Setup Time 2 ms tAH Address Hold Time 2 ms tOEH OE Hold Time 2 ms tDH Data Hold Time tDF Output Enable to Output Float Delay CE/PGM e VIL tOE Output Enable to Output Delay CE/PGM e VIL tPW Program Pulse Width 45 tPRT Program Pulse Rise Time 5 ns tPFT Program Pulse Fall Time 5 ns 2 ms 0 50 120 ns 100 ns 55 ms AC Test Conditions VCC VPP Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level Inputs Outputs 5V g 10% 25V g 1V s 20 ns 0.8V to 2.2V 5 1V and 2V 0.8V and 2V Programming Waveforms VPP e 25V g 11V, VCC e 5V g 5% (Note 3) TL/D/10329 – 4 Note: All times shown in parentheses are minimum and in ms unless otherwise specified. Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The 27C16 must not be inserted into or removed from a board with VPP at 25V g 1V to prevent damage to the device. Note 3: The maximum allowable voltage which may be applied to the VPP pin during programming is 26V. Care must be taken when switching the VPP supply to prevent overshoot exceeding this 26V maximum specification. A 0.1 mF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Functional Description b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. DEVICE OPERATION The six modes of operation of the 27C16 are listed in Table I. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are a 5V VCC and a VPP. The VPP power supply must be at 25V during the three programming modes, and must be at 5V in the other three modes. Read Mode The 27C16 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC – tOE. The 27C16 requires one address transition after initial power-up to reset the outputs. Programming CAUTION: Exceeding 26.5V on pin 21 (VPP) will damage the 27C16. Initially, and after each erasure, all bits of the 27C16 are in the ‘‘1’’ state. Data is introduced by selectively programming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The 27C16 is in the programming mode when the VPP power supply is at 25V and OE is at VIH. It is required that a 0.1 mF capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, a 50 ms, active high, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. You can program any location at any timeÐ either individually, sequentially, or at random. The program pulse has a maximum width of 55 ms. The 27C16 must not be programmed with a DC signal applied to the CE/PGM input. Standby Mode The 27C16 has a standby mode which reduces the active power dissipation by 98%, from 26.25 mW to 0.53 mW. The 27C16 is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR-Tying Because 27C16s are usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and 6 Functional Description (Continued) 12,000 mW/cm2 power rating. The 27C16 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Programming multiple 27C16s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled 27C16s may be connected together when they are programmed with the same data. A high level TTL pulse applied to the CE/PGM input programs the paralleled 27C16s. Note: The 27C16-550 may take up to 60 minutes for complete erasure to occur. An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. Program Inhibit Programming multiple 27C16s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs (including OE) of the parallel 27C16s may be common. A TTL level program pulse applied to an 27C16’s CE/ PGM input with VPP at 25V will program that 27C16. A low level CE/PGM input inhibits the other 27C16 from being programmed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 25V. VPP must be at VCC, except during programming and program verify. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designerÐthe standby current level, the active current level, and the transient current peaks that are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 mF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. ERASURE CHARACTERISTICS The erasure characteristics of the 27C16 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ð–4000Ð range. Opaque labels should be placed over the 27C16 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. The recommended erasure procedure for the 27C16 is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (Ð). The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a TABLE I. Mode Selection Pins Mode CE/PGM (18) OE (20) VP (21) VCC (24) Outputs (9 – 11, 13 – 17) Read VIL VIL VCC 5 DOUT Standby VIH Don’t Care VCC 5 Hi-Z Program Pulsed VIL to VIH VIH 25 5 DIN Program Verify VIL VIL 25 5 DOUT Program Inhibit VIL VIH 25 5 Hi-Z Output Disable X VIH VCC 5 Hi-Z 7 27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified Physical Dimensions inches (millimeters) Lit. Ý 114700 24 Lead Ceramic Dual-In-Line Package (J) Order Number 27C16Q450/883 or 27C16Q550/883 NS Package Number J24AQ LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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