74LVC821A 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 03 — 11 May 2004 Product data sheet 1. General description The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an output enable input (pin OE) are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE inputs does not affect the state of the flip-flops. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 V tolerant inputs and outputs; for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Flow-through pin-out architecture 10-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard JESD8-B ESD protection: ◆ HBM EIA/JESD22-A114-B exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V. ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C. 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay CP to Qn CL = 50 pF; VCC = 3.3 V - 3.7 - ns tPZH, tPZL 3-state output enable time OE to Qn CL = 50 pF; VCC = 3.3 V - 3.5 - ns tPHZ, tPLZ 3-state output disable time OE to Qn CL = 50 pF; VCC = 3.3 V - 3.0 - ns fmax maximum clock frequency CL = 50 pF; VCC = 3.3 V - 200 - MHz CI input capacitance - 5.0 - pF outputs enabled - 17 - pF outputs disabled - 11 - pF power dissipation capacitance per gate CPD VCC = 3.3 V [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ (CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC. [1] [2] 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description 74LVC821AD −40 °C to +125 °C SO24 plastic small outline package; 24 leads; body width SOT137-1 7.5 mm 74LVC821ADB −40 °C to +125 °C SSOP24 plastic shrink small outline package; 24 leads; body SOT340-1 width 5.3 mm 74LVC821APW −40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm 74LVC821ABQ −40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm 9397 750 13276 Product data sheet Version SOT355-1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 2 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 5. Functional diagram 2 D0 Q0 23 3 D1 Q1 22 4 D2 Q2 21 5 D3 Q3 20 6 D4 7 D5 8 D6 9 D7 Q7 16 10 D8 Q8 15 11 D9 Q9 14 FF0 to FF9 3-STATE OUTPUTS Q4 19 Q5 18 Q6 17 13 CP 1 OE 001aaa679 Fig 1. Functional diagram. 13 13 2 3 4 5 6 7 8 9 10 11 1 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 C1 EN 23 22 21 2 23 1D 3 22 4 21 5 20 17 6 19 16 7 18 8 17 9 16 10 15 11 14 20 19 18 15 14 OE 1 001aaa677 001aaa678 Fig 2. Logic symbol. Fig 3. IEC logic symbol. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 3 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 Q CP FF4 FF5 CP OE Q0 D5 Q1 D6 D Q Q Q Q6 Q D CP FF8 Q CP FF9 Q7 Q4 D9 D CP FF7 Q5 D8 D CP FF6 Q3 D7 D CP Q2 FF10 Q8 Q9 001aaa681 Fig 4. Logic diagram. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 4 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 6. Pinning information 6.1 Pinning OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 821A 7 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 CP VCC 1 24 D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 GND(1) 18 Q5 D5 OE 001aaa676 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 Top view 12 13 GND CP 001aaa680 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO24 and (T)SSOP24. Fig 6. Pin configuration DHVQFN24. 6.2 Pin description Table 3: Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 2 data input D1 3 data input D2 4 data input D3 5 data input D4 6 data input D5 7 data input D6 8 data input D7 9 data input D8 10 data input D9 11 data input 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 5 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 3: Pin description …continued Symbol Pin Description GND 12 ground (0 V) CP 13 clock input (LOW-to-HIGH, edge-triggered) Q9 14 3-state flip-flop output Q8 15 3-state flip-flop output Q7 16 3-state flip-flop output Q6 17 3-state flip-flop output Q5 18 3-state flip-flop output Q4 19 3-state flip-flop output Q3 20 3-state flip-flop output Q2 21 3-state flip-flop output Q1 22 3-state flip-flop output Q0 23 3-state flip-flop output VCC 24 supply voltage 7. Functional description Table 4: Function table [1] Operating mode Input Load and read register Load register and disable outputs Hold [1] OE CP Dn Internal flip-flops Output Qn L ↑ I L L L ↑ h H H H ↑ I L Z H ↑ h H Z L H or L X NC NC H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; NC = no change; X = don’t care. 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions IIK input diode current VI input voltage IOK output diode current VI < 0 V [1] VO > VCC or VO < 0 V 9397 750 13276 Product data sheet Min Max Unit −0.5 +6.5 V - −50 mA −0.5 +6.5 V - ±50 mA © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 6 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 5: Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VO Parameter Conditions output voltage IO output source or sink current ICC, IGND VCC or GND current Tstg storage temperature Ptot power dissipation Min Max HIGH or LOW state [1] −0.5 VCC + 0.5 V 3-state [1] −0.5 +6.5 V - ±50 mA - ±100 mA VO = 0 V to VCC Tamb = −40 °C to +125 °C [2] Unit −65 +150 °C - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO24 package: above 70 °C derate linearly with 8 mW/K. For SSOP24 and TSSOP24 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN24 package: above 60 °C derate linearly with 4.5 mW/K. 9. Recommended operating conditions Table 6: Operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage for maximum speed performance 2.7 - 3.6 V for low-voltage applications 1.2 - 3.6 V VI input voltage VO output voltage 0 - 5.5 V HIGH or LOW state 0 - VCC V 3-state 0 - 5.5 V in free air −40 - +125 °C Tamb operating ambient temperature tr, tf input rise and fall times VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 1.2 V VCC - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.2 V - - GND V VCC = 2.7 V to 3.6 V - - 0.8 V Tamb = −40 °C to +85 °C [1] VIH VIL HIGH-level input voltage LOW-level input voltage 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 7 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 2.7 V to 3.6 V VOL LOW-level output voltage [2] Min Typ Max Unit VCC − 0.2 VCC - V IO = −12 mA; VCC = 2.7 V VCC − 0.5 - - V IO = −18 mA; VCC = 3.0 V VCC − 0.6 - - V IO = −24 mA; VCC = 3.0 V VCC − 0.8 - - V VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V [2] - GND 0.2 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V ILI input leakage current VI = 5.5 V or GND; VCC = 3.6 V - ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - 0.1 ±5 µA Ioff power-off leakage supply current VI or VO = 5.5 V; VCC = 0 V - 0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.1 10 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - 5 500 µA CI input capacitance - 5.0 - pF VCC = 1.2 V VCC - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.2 V - - 0 V VCC = 2.7 V to 3.6 V - - 0.8 V IO = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.3 - - V IO = −12 mA; VCC = 2.7 V VCC − 0.65 - - V IO = −18 mA; VCC = 3.0 V VCC − 0.75 - - V IO = −24 mA; VCC = 3.0 V VCC − 1 - - V [2] Tamb = −40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V ILI input leakage current VI = 5.5 V or GND; VCC = 3.6 V - - ±20 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - - ±20 µA Ioff power-off leakage supply current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - - 40 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - - 5000 µA 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 8 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs [1] All typical values are measured Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V. 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10 Symbol Parameter Tamb = −40 °C to +85 Conditions tPHL, tPLH propagation delay CP to Qn VCC = 2.7 V VCC = 3.0 V to 3.6 V 3-state output enable time OE to Qn [2] VCC = 2.7 V VCC = 3.0 V to 3.6 V 3-state output disable time OE to Qn [2] VCC = 2.7 V VCC = 3.0 V to 3.6 V clock pulse width HIGH or LOW [2] VCC = 2.7 V VCC = 3.0 V to 3.6 V set-up time Dn to CP [2] VCC = 2.7 V VCC = 3.0 V to 3.6 V hold time Dn to CP [2] VCC = 2.7 V VCC = 3.0 to 3.6 V maximum clock frequency [2] VCC = 2.7 V skew power dissipation capacitance per gate - 8.5 ns 1.5 3.7 7.3 ns - 20 - ns 1.5 - 8.8 ns 1.3 3.5 7.6 ns - 9.0 - ns 1.5 - 6.8 ns 1.5 3.0 6.2 ns - - - ns 3.3 - - ns 3.3 1.7 - ns - - - ns 0.9 - - ns 1.9 0.6 - ns - - - ns 1.5 - - ns 1.5 0.0 - ns - - - MHz 150 - - MHz 150 200 - MHz [3] - - 1.0 ns outputs enabled - 17 - pF outputs disabled - 11 - pF VCC = 3.0 V to 3.6 V VCC = 3.3 V 9397 750 13276 Product data sheet 1.5 [2] VCC = 3.0 V to 3.6 V CPD ns see Figure 7 VCC = 1.2 V tsk(0) - see Figure 8 VCC = 1.2 V fmax 18 see Figure 8 VCC = 1.2 V th - see Figure 7 VCC = 1.2 V tsu Unit see Figure 9 VCC = 1.2 V tW Max see Figure 9 VCC = 1.2 V tPHZ, tPLZ Typ see Figure 7 VCC = 1.2 V tPZH, tPZL Min °C [1] [4] [5] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 9 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10 Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Qn tPZH, tPZL tPHZ, tPLZ 3-state output enable time OE to Qn 3-state output disable time OE to Qn clock pulse width HIGH or LOW tW set-up time Dn to CP tsu hold time Dn to CP th maximum clock frequency fmax see Figure 7 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 11.0 ns VCC = 3.0 V to 3.6 V 1.5 - 9.5 ns see Figure 9 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 11.0 ns VCC = 3.0 V to 3.6 V 1.3 - 9.5 ns see Figure 9 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - 8.5 ns VCC = 3.0 V to 3.6 V 1.5 - 8.0 ns see Figure 7 VCC = 1.2 V - - - ns VCC = 2.7 V 3.3 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns see Figure 8 VCC = 1.2 V - - - ns VCC = 2.7 V 0.9 - - ns VCC = 3.0 V to 3.6 V 1.9 - - ns see Figure 8 VCC = 1.2 V - - - ns VCC = 2.7 V 1.5 - - ns VCC = 3.0 V to 3.6 V 1.5 - - ns VCC = 1.2 V - - - MHz VCC = 2.7 V 150 - - MHz 150 - - MHz - - 1.0 ns see Figure 7 VCC = 3.0 V to 3.6 V tsk(0) skew VCC = 3.0 V to 3.6 V [3] [1] All typical values are measured Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ (CL × VCC2 × fo) = sum of the outputs. [5] The condition is VI = GND to VCC. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 10 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 12. Waveforms 1/f max VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna894 Measurement points are given in Table 9. VOL and VOH are the typical output voltage drop that occur with the output load. Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. Table 9: Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5 × VCC 0.5 × VCC ≥ 2.7 V 1.5 V 1.5 V VI VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL mna202 Measurement points are given in Table 10. VOL and VOH are the typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. Data set-up and hold times for the Dn input to the CP input. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 11 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 10: Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5 × VCC 0.5 × VCC ≥ 2.7 V 1.5 V 1.5 V VI OE input VM VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mgu775 Measurement points are given in Table 11. VOL and VOH are the typical output voltage drop that occur with the output load. Fig 9. 3-state enable and disable times. Table 11: Measurement points Supply voltage Input Output VCC VM VM VX VY < 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.1 × VCC VOH − 0.1 × VCC ≥ 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V VEXT VCC PULSE GENERATOR VI RL VO D.U.T. RT CL RL mna616 Data test circuit (see Table 12). RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 10. Load circuitry for switching times. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 12 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs Table 12: Test data Supply voltage Input Load VCC CL VI RL tPLH, tPHL Ω [1] tPZH, tPHZ tPZL, tPLZ 1.2 V VCC 50 pF 500 open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 2 × VCC 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCC [1] The circuit performs better when RL = 1000 Ω. 9397 750 13276 Product data sheet VEXT © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 13 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SO24. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 14 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT340-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 12. Package outline SSOP24. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 15 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT355-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline TSSOP24. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 16 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm B D SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e y1 C v M C A B w M C b 2 y 11 L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.6 5.4 4.25 3.95 3.6 3.4 2.25 1.95 0.5 4.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT815-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 14. Package outline DHVQFN24. 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 17 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 14. Revision history Table 13: Revision history Document ID Release date Data sheet status Change notice Order number Supersedes 74LVC821A_3 20040511 Product data - 9397 750 13276 74LVC821A_2 Modifications: • Figure 4: corrected. 74LVC821A_2 20040415 Product data - 9397 750 13047 74LVC821A_1 74LVC821A_1 19980925 Product specification - 9397 750 04584 - 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 18 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13276 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 11 May 2004 19 of 20 74LVC821A Philips Semiconductors 10-bit D-type flip-flop with 5 V tolerant inputs/outputs 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 11 May 2004 Document order number: 9397 750 13276 Published in The Netherlands