ETC SST29LE010A-200-4C-EH

1 Megabit (128K x8) Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for the SST29EE010A
– 3.0-3.6V for the SST29LE010A
– 2.7-3.6V for the SST29VE010A
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs
(typical)
PRODUCT DESCRIPTION
The SST29EE010A/29LE010A/29VE010A are 128K x8
CMOS Page-Write EEPROMs manufactured with SST’s
proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The
SST29EE010A/29LE010A/29VE010A write with a
single power supply. Internal Erase/Program is transparent to the user. The SST29EE010A/29LE010A/
29VE010A conform to JEDEC standard pinouts for bytewide memories.
Featuring high performance Page-Write, the
SST29EE010A/29LE010A/29VE010A provide a typical
Byte-Write time of 39 µsec. The entire memory, i.e., 128
KBytes, can be written page-by-page in as little as 5
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of a Write
cycle. To protect against inadvertent write, the
SST29EE010A/29LE010A/29VE010A have on-chip
hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, the SST29EE010A/29LE010A/29VE010A
are offered with a guaranteed Page-Write endurance of
104 cycles. Data retention is rated at greater than 100
years.
The SST29EE010A/29LE010A/29VE010A are suited
for applications that require convenient and economical
• Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
1
2
3
4
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm & 8mm x 20mm)
updating of program, configuration, or data memory. For
all system applications, the SST29EE010A/29LE010A/
29VE010A significantly improve performance and reliability, while lowering power consumption. The
SST29EE010A/29LE010A/29VE010A improve flexibility while lowering the cost for program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
SST29EE010A/29LE010A/29VE010A are offered in 32pin TSOP and 32-lead PLCC packages. A 600-mil, 32pin PDIP package is also available. See Figures 1 and 2
for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electrical write capability. The SST29EE010A/29LE010A/
29VE010A does not require separate Erase and
Program operations. The internally timed write cycle
executes both erase and program transparently to the
user. The SST29EE010A/29LE010A/29VE010A have
industry standard Software Data Protection. The
SST29EE010A/29LE010A/29VE010A are compatible
with industry standard EEPROM pinouts and
functionality.
Read
The Read operations of the SST29EE010A/29LE010A/
29VE010A are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc.
303-02 2/00
These specifications are subject to change without notice.
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
array. Hence, the Page-Write feature of SST29EE010A/
29LE010A/29VE010A allow the entire memory to be
written in as little as 5 seconds. During the internal write
cycle, the host is free to perform additional tasks, such as
to fetch data from other locations in the system to set up
the write to the next page. In each Page-Write operation,
all the bytes that are loaded into the page buffer must
have the same page address, i.e. A7 through A16. Any
byte not loaded with user data will be written to FF.
CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page-Write to the SST29EE010A/29LE010A/
29VE010A uses the JEDEC Standard Software Data
Protection (SDP) three-byte command sequence.
See Figures 4 and 5 for the Page-Write cycle timing
diagrams. If after the completion of the three-byte SDP
load sequence the host loads a byte into the page buffer
within a byte-load cycle time (TBLC) of 100 µs, the
SST29EE010A/29LE010A/29VE010A will stay in the
page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no
additional byte is loaded into the page buffer within 200
µs (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last
rising edge of WE# or CE#. Data in the page buffer can
be changed by a subsequent byte-load cycle. The page
load period can continue indefinitely, as long as the host
continues to load the device within the byte-load cycle
time of 100 µs. The page to be loaded is determined by
the page address of the last byte loaded.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE010A/29LE010A/29VE010A. Steps 1 and 2
use the same timing for both operations. Step 3 is an
internally controlled write cycle for writing the data loaded
in the page buffer into the memory array for nonvolatile
storage. During both the SDP three-byte load sequence
and the byte-load cycle, the addresses are latched by the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched by the rising edge of either CE# or
WE#, whichever occurs first. The internal write cycle is
initiated by the TBLCO timer after the rising edge of WE#
or CE#, whichever occurs first. The Write cycle, once
initiated, will continue to completion, typically within 5 ms.
See Figures 4 and 5 for WE# and CE# controlled PageWrite cycle timing diagrams and Figures 13 and 15 for
flowcharts.
Software Chip-Erase
The SST29EE010A/29LE010A/29VE010A provide a
Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state.
This is useful when the entire device must be quickly
erased.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three-byte load sequence that allows writing to the selected page and will
leave the SST29EE010A/29LE010A/29VE010A protected at the end of the Page-Write. The page load cycle
consists of loading 1 to 128 Bytes of data into the page
buffer. The internal write cycle consists of the TBLCO
time-out and the write timer operation. During the Write
operation, the only valid reads are Data# Polling and
Toggle Bit.
The Software Chip-Erase operation is initiated by using
a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle
similar to the Write cycle. During the Erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure 8 for timing diagram, and Figure 17 for
the flowchart.
The Page-Write operation allows the loading of up to 128
Bytes of data into the page buffer of the SST29EE010A/
29LE010A/29VE010A before the initiation of the internal
write cycle. During the internal write cycle, all the data in
the page buffer is written simultaneously into the memory
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303-02 2/00
1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Write Operation Status Detection
The SST29EE010A/29LE010A/29VE010A provide two
software means to detect the completion of a Write cycle,
in order to optimize the system write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising WE# or CE# whichever
occurs first, which initiates the internal write cycle.
Data Protection
The SST29EE010A/29LE010A/29VE010A provide both
hardware and software features to protect nonvolatile
data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a Write cycle.
2
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
VCC Power Up/Down Detection: The Write operation is
inhibited when VCC is less than 2.5V.
3
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
4
Software Data Protection (SDP)
The SST29EE010A/29LE010A/29VE010A provide the
JEDEC approved Software Data Protection scheme for
all data alteration operations, i.e., Write and Chip-Erase.
With this scheme, any Write operation requires the
inclusion of a series of three byte-load operations to
precede the data loading operation. The three byte-load
sequence is used to initiate the Write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down.
Data# Polling (DQ7)
When the SST29EE010A/29LE010A/29VE010A are in
the internal write cycle, any attempt to read DQ7 of the
last byte loaded during the byte-load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ7 will show true data. The device is then
ready for the next operation. See Figure 6 for Data#
Polling timing diagram and Figure 14 for a flowchart.
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5
6
7
8
9
Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts
to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the Write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 14 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
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303-02 2/00
1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Product Identification Mode Exit
In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting
is accomplished by issuing the Software ID Exit (reset)
operation, which returns the device to the Read operation. The Reset operation may also be used to reset the
device to the read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 10 for timing waveform and Figure 16 for a flowchart.
Product Identification
The product identification mode identifies the device as
the SST29EE010A/29LE010A/29VE010A and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is
typically used by a programmer to identify the correct
algorithm for the SST29EE010A/29LE010A/29VE010A.
Users may wish to use the software product identification
operation to identify the part (i.e. using the device code)
when using multiple manufacturers in the same socket.
For details, see Table 3 for hardware operation or Table
4 for software operation, Figure 9 for the software ID entry
and read timing diagram and Figure 16 for the ID entry
command sequence flowchart. The manufacturer and
device codes are the same for both operations.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Byte
Manufacturer’s Code
0000 H
SST29EE010A Device Code 0001 H
SST29LE010A Device Code 0001 H
SST29VE010A Device Code 0001 H
Data
BF H
22 H
23 H
23 H
303 PGM T1.1
FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010A/29LE010A/29VE010A
X-Decoder
A16 - A0
1,048,576 Bit
EEPROM
Cell Array
Address Buffer & Latches
Y-Decoder and Page Latches
CE#
OE#
WE#
Control Logic
I/O Buffers and Data Latches
DQ7 - DQ0
303 ILL B1.0
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
A11
A9
A8
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
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2
3
4
303 ILL F01.1
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
WE#
4
3
2
1
32 31 30
29
NC
VCC
A6
NC
5
A16
A7
A15
6
28
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE#
A1
11
23
A10
A0
12
22
CE#
DQ0
13
21
14 15 16 17 18 19 20
DQ7
DQ5
DQ4
DQ3
32-Lead PLCC
Top View
DQ6
A14
6
VSS
VCC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A12
1
2
3
4
5
32-Pin
6
PDIP
7
8 Top View
9
10
11
12
13
14
15
16
DQ1
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
5
7
8
9
10
303 ILL F02.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A16-A7
Row Address Inputs
A6-A0
DQ7-DQ0
Column Address
Inputs
Data Input/output
CE#
OE#
WE#
Vcc
Chip Enable
Output Enable
Write Enable
Power Supply
Vss
NC
Ground
No Connection
11
Functions
To provide memory addresses. Row addresses define a page for a
Write cycle.
Column Addresses are toggled to load page data.
To output data during Read cycles and receive input data during Write
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations
To provide 5-volt supply (± 10%) for the SST29EE010A, 3-volt supply
(3.0-3.6V) for the SST29LE010A and 2.7-volt supply (2.7-3.6V) for the
SST29VE010A
Unconnected pins.
303 PGM T2.0
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
OE#
Read
VIL
VIL
Page-Write
VIL
VIH
Standby
VIH
X
Write Inhibit
X
VIL
Write Inhibit
X
X
Software Chip-Erase
VIL
VIH
Product Identification
Hardware Mode
VIL
VIL
Software Mode
SDP Enable Mode
VIL
VIL
VIH
VIH
WE#
VIH
VIL
X
X
VIH
VIL
DQ
DOUT
DIN
High Z
High Z/ DOUT
High Z/ DOUT
DIN
Address
AIN
AIN, See Table 4
X
X
X
AIN, See Table 4
VIH
Manufacturer Code (BF)
Device Code (see notes)
A16 - A1 = VIL, A9 = VH, A0 = VIL
A16 - A1 = VIL, A9 = VH, A0= VIH
See Table 4
See Table 4
VIL
VIL
303 PGM T3.0
TABLE 4: SOFTWARE COMMAND CODES
Command
Sequence
1st Bus
Write Cycle
Addr(1) Data
5555H AAH
5555H AAH
2nd Bus
Write Cycle
Addr(1) Data
2AAAH 55H
2AAAH 55H
3rd Bus
Write Cycle
Addr(1) Data
5555H A0H
5555H 80H
5555H
AAH
2AAAH
55H
5555H
90H
5555H
AAH
2AAAH
55H
5555H
F0H
Alternate Software 5555H
ID Entry(3)
AAH
2AAAH
55H
5555H
80H
Page-Write
Software ChipErase
Software ID Entry
Software ID Exit
4th Bus
Write Cycle
Addr(1) Data
Addr(2) Data
5555H AAH
5th Bus
Write Cycle
Addr(1) Data
6th Bus
Write Cycle
Addr(1) Data
2AAAH
55H
5555H
10H
5555H
2AAAH
55H
5555H
60H
AAH
303 PGM T4.0
Notes:
(1)
Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
Page-Write consists of loading up to 128 Bytes (A 6 - A0).
(3) Alternate six-byte software Product-ID Command Code
(4) The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
Notes for Software Product ID Command Code:
1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0,
SST29EE010A Device Code = 22H, is read with A0 = 1.
SST29LE010A/29VE010A Device Code = 23H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
3. This device supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code
sequence. For new designs, SST recommends the three-byte command code sequence be used.
(2)
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
Output Short Circuit Current(1) ....................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
SST29EE010A OPERATING RANGE
Range
Ambient Temp
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
VCC
5V±10%
5V±10%
SST29LE010A OPERATING RANGE
Range
Ambient Temp
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
VCC
3.0V to 3.6V
3.0V to 3.6V
SST29VE010A OPERATING RANGE
Range
Ambient Temp
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
VCC
2.7V to 3.6V
2.7V to 3.6V
1
2
3
4
5
6
AC CONDITIONS OF TEST
Input Rise/Fall Time ......... 10 ns
Output Load ..................... 1 TTL Gate and CL = 100 pF
7
See Figures 12 and 13
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9
10
11
12
13
14
15
16
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303-02 2/00
1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TABLE 5: SST29EE010A DC OPERATING CHARACTERISTICS VCC = 5V±10%
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
ICC
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read
30
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
50
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
ISB1
Standby VCC Current
3
mA
CE#=OE#=WE#=VIH, VCC =VCC Max.
(TTL input)
ISB2
Standby VCC Current
50
µA
CE#=OE#=WE#=VCC -0.3V.
(CMOS input)
VCC = VCC Max.
ILI
Input Leakage Current
1
µA
VIN =GND to VCC, VCC = VCC Max.
ILO
Output Leakage Current
10
µA
VOUT =GND to VCC, VCC = VCC Max.
VIL
Input Low Voltage
0.8
V
VCC = VCC Min.
VIH
Input High Voltage
2.0
V
VCC = VCC Max.
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA, VCC = VCC Min.
VOH
Output High Voltage
2.4
V
IOH = -400µA, VCC = VCC Min.
VH
Supervoltage for A9
11.6
12.4
V
CE# = OE# =VIL, WE# = VIH
IH
Supervoltage Current
100
µA
CE# = OE# = VIL, WE# = VIH,
A9 = VH Max.
for A9
303 PGM T5.1
TABLE 6: SST29LE010A/29VE010A DC OPERATING CHARACTERISTICS VCC = 3.0-3.6 FOR SST29LE010A,
VCC = 2.7-3.6 FOR SST29VE010A
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
Power Supply Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
ICC
Read
12
mA
Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write
15
mA
CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
ISB1
Standby VCC Current
1
mA
CE#=OE#=WE#=VIH, VCC =VCC Max.
(TTL input)
ISB2
Standby VCC Current
15
µA
CE#=OE#=WE#=VCC -0.3V.
(CMOS input)
VCC = VCC Max.
ILI
Input Leakage Current
1
µA
VIN =GND to VCC, VCC = VCC Max.
ILO
Output Leakage Current
10
µA
VOUT =GND to VCC, VCC = VCC Max.
VIL
Input Low Voltage
0.8
V
VCC = VCC Min.
Input High Voltage
2.0
V
VCC = VCC Max.
VIH
VOL
Output Low Voltage
0.4
V
IOL = 100 µA, VCC = VCC Min.
VOH
Output High Voltage
2.4
V
IOH = -100 µA, VCC = VCC Min.
VH
Supervoltage for A9
11.6
12.4
V
CE# = OE# =VIL, WE# = VIH
IH
Supervoltage Current
100
µA
CE# = OE# = VIL, WE# = VIH,
for A9
A9 = VH Max.
303 PGM T6.1
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303-02 2/00
1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TABLE 7: POWER-UP TIMINGS
Symbol
Parameter
TPU-READ(1)
Power-up to Read Operation
(1)
TPU-WRITE
Power-up to Write Operation
Maximum
100
5
Units
µs
ms
1
303 PGM T7.0
TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
CI/O(1)
I/O Pin Capacitance
VI/O = 0V
CIN(1)
Input Capacitance
VIN = 0V
Maximum
12 pF
6 pF
2
3
303 PGM T8.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
4
5
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND
TDR(1)
VZAP_HBM(1)
VZAP_MM(1)
ILTH(1)
Endurance
Data Retention
ESD Susceptibility
Human Body Model
ESD Susceptibility
Machine Model
Latch Up
6
Minimum Specification
Units
Test Method
10,000
100
2000
Cycles
Years
Volts
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
200
Volts
JEDEC Standard A115
100
mA
(1)This
8
JEDEC Standard 78
303 PGM T9.2
Note:
7
9
parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
10
11
12
13
14
15
16
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
AC CHARACTERISTICS
TABLE 10: SST29EE010A READ CYCLE TIMING PARAMETERS
SST29EE010A-90
Symbol
Parameter
Min
Max
90
SST29EE010A-120
Min
Max
120
Units
TRC
Read Cycle Time
TCE
Chip Enable Access Time
90
120
ns
TAA
Address Access Time
90
120
ns
TOE
Output Enable Access Time
TCLZ(1)
CE# Low to Active Output
0
0
ns
TOLZ(1)
OE# Low to Active Output
0
0
ns
40
ns
50
ns
(1)
CE# High to High-Z Output
30
30
ns
TOHZ(1)
TOH(1)
OE# High to High-Z Output
30
30
ns
TCHZ
Output Hold from Address
Change
0
0
ns
303 PGM T10.0
TABLE 11: SST29LE010A READ CYCLE TIMING PARAMETERS
SST29LE010A-150
Symbol
TRC
TCE
TAA
TOE
TCLZ(1)
TOLZ(1)
TCHZ(1)
TOHZ(1)
TOH(1)
Parameter
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
Min
150
Max
SST29LE010A-200
Min
200
150
150
60
0
0
Max
200
200
100
0
0
30
30
0
50
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
303 PGM T11.0
TABLE 12: SST29VE010A READ CYCLE TIMING PARAMETERS
SST29VE010A-200
Symbol
TRC
TCE
TAA
TOE
TCLZ(1)
TOLZ(1)
TCHZ(1)
TOHZ(1)
TOH(1)
Parameter
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
Min
200
Max
SST29VE010A-250
Min
250
200
200
100
0
0
250
250
120
0
0
50
50
0
Max
50
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
303 PGM T12.0
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
Symbol
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TDS
TDH
TBLC(1)
TBLCO(1)
TIDA
TSCE
Parameter
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
WE# Pulse Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip-Erase
SST29EE010A
Min
Max
10
0
50
0
0
0
0
70
70
35
0
0.05
100
200
10
20
SST29LE/VE010A
Min
Max
10
0
70
0
0
0
0
120
120
50
0
0.05
100
200
10
20
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ms
1
2
3
4
5
6
7
303 PGM T13.1
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
8
9
10
11
12
13
14
15
16
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TRC
TAA
ADDRESS A16-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
HIGH-Z
TCHZ
TOH
TCLZ
HIGH-Z
DATA VALID
DQ 7-0
DATA VALID
303 ILL F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
TAH
Page-Write
TAS
ADDRESS A16-0
5555
2AAA
5555
TCS
TCH
CE#
TOES
TOEH
OE#
TWP
TBLCO
TBLC
WE#
TDH
DQ 7-0
AA
55
SW0
SW1
A0
DATA VALID
TWC
TDS
SW2
BYTE 0
BYTE 1
BYTE 127
303 ILL F04.1
FIGURE 4: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
TAH
Page-Write
1
TAS
ADDRESS A16-0
5555
2AAA
5555
TCP
2
TBLCO
TBLC
CE#
TOES
3
TOEH
OE#
4
TCS
TCH
WE#
5
TDH
DQ 7-0
AA
55
SW0
SW1
A0
DATA VALID
BYTE 0
6
TWC
TDS
SW2
BYTE 1
BYTE 127
303 ILL F05.1
FIGURE 5: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
7
8
9
10
ADDRESS A16-0
TCE
11
CE#
TOES
TOEH
12
OE#
TOE
13
WE#
DQ 7
D
D#
D#
14
D
TWC + TBLCO
303 ILL F06.0
15
16
FIGURE 6: DATA# POLLING TIMING DIAGRAM
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
ADDRESS A16-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6
TWC + TBLCO
TWO READ CYCLES
WITH SAME OUTPUTS
303 ILL F07.0
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
Six-Byte Code for Software Chip-Erase
ADDRESS A14-0
DQ 7-0
5555
AA
2AAA
5555
55
5555
80
2AAA
AA
TSCE
5555
55
10
CE#
OE#
TBLCO
TWP
WE#
TBLC
SW0
SW1
SW2
SW3
SW4
SW5
303 ILL F09.1
FIGURE 8: SOFTWARE CHIP-ERASE TIMING DIAGRAM
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Three-Byte Sequence
for Software ID Entry
ADDRESS A14-0
5555
1
5555
2AAA
0000
0001
2
TAA
DQ 7-0
AA
90
55
BF
DEVICE CODE
3
TIDA
CE#
4
OE#
5
TWP
WE#
6
TBLC
SW0
SW1
DEVICE ID
SW2
= 22 for SST29EE010A
= 23 for SST29LE010A/29VE010A
303 ILL F10.2
7
FIGURE 9: SOFTWARE ID ENTRY AND READ
8
9
Three-Byte Sequence
for Software ID Exit and Reset
ADDRESS A14-0
DQ 7-0
5555
AA
10
5555
2AAA
55
11
F0
TIDA
12
CE#
13
OE#
14
TWP
WE#
TBLC
SW0
SW1
15
SW2
303 ILL F11.0
16
FIGURE 10: SOFTWARE ID EXIT AND RESET
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
VIHT
VHT
INPUT
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
303 ILL F12.1
«
AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10%
90%) are <10 ns.
Note: VHT–VHIGH Test
VLT–VLOW Test
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test
FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE
VCC
TO TESTER
RL HIGH
TO DUT
CL
RL LOW
303 ILL F13.0
FIGURE 12: A TEST LOAD EXAMPLE
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
See Figure 15
Start
1
Page-Write
Command
2
3
Set Page
Address
4
5
Set Byte
Address = 0
6
Load Byte
Data
7
8
Increment
Byte Address
By 1
No
9
Byte
Address =
128?
10
Yes
11
12
Wait TBLCO
13
Wait for End-ofWrite (TWC,
Data# Polling bit
or Toggle bit
operation)
Write
Completed
14
15
303 ILL F14.2
16
FIGURE 13: WRITE ALGORITHM
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Page-Write
Initiated
Page-Write
Initiated
Page-Write
Initiated
Wait TWC
Read a byte
from page
Read DQ7
(Data for last
byte loaded)
Write
Completed
Read same
byte
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Write
Completed
Yes
Write
Completed
303 ILL F15.1
FIGURE 14: WAIT OPTIONS
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Command Sequence
1
Write data: AA
Address: 5555
2
3
Write data: 55
Address: 2AAA
4
Write data: A0
Address: 5555
Load 0 to
128 Bytes of
page data
5
6
Page Load Operation
7
8
Wait TBLCO
9
Wait TWC
10
11
Device Written
12
303 ILL F16.1
13
FIGURE 15: PAGE-WRITE FLOWCHART
14
15
16
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AA
Address: 5555
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: 55
Address: 2AAA
Write data: 90
Address: 5555
Write data: F0
Address: 5555
Pause 10 µs
Pause 10 µs
Read Software ID
Return to normal
operation
303 ILL F17.0
FIGURE 16: SOFTWARE PRODUCT COMMAND FLOWCHARTS
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Software Chip-Erase
Command Sequence
1
Write data: AA
Address: 5555
2
3
Write data: 55
Address: 2AAA
4
5
Write data: 80
Address: 5555
6
Write data: AA
Address: 5555
7
8
Write data: 55
Address: 2AAA
9
Write data: 10
Address: 5555
10
11
Wait TSCE
12
13
Chip-Erase
to FFH
303 ILL F18.1
14
FIGURE 17: SOFTWARE CHIP-ERASE COMMAND CODES
15
16
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
SST29xE010A - XXX
Suffix1
-
XX
Suffix2
-
XX
Package Modifier
H = 32 leads
Numeric = Die modifier
Package Type
P = PDIP
N = PLCC
E = TSOP (die up) 8mm x 20mm
W = TSOP (die up) 8mm x 14mm
U = Unencapsulated die
Operating Temperature
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 = 150 ns
120 = 120 ns
90 = 90 ns
Version Code
Voltage
E = 5.0V-only
L = 3.0 - 3.6V
V = 2.7 - 3.6V
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
SST29EE010A Valid combinations
SST29EE010A-90-4C-EH
SST29EE010A-90-4C-NH
SST29EE010A-120-4C-EH
SST29EE010A-120-4C-NH
SST29EE010A-90-4C-PH
SST29EE010A-120-4C-PH
1
SST29EE010A-90-4C-WH
SST29EE010A-120-4C-WH
SST29EE010A-90-4I-EH
SST29EE010A-120-4I-EH
2
SST29EE010A-90-4I-NH
SST29EE010A-120-4I-NH
3
SST29EE010A-120-4C-U2
4
SST29LE010A Valid combinations
SST29LE010A-150-4C-EH
SST29LE010A-150-4C-NH
SST29LE010A-200-4C-EH
SST29LE010A-200-4C-NH
SST29LE010A-150-4C-WH
SST29LE010A-200-4C-WH
SST29LE010A-150-4I-EH
SST29LE010A-150-4I-WH
SST29LE010A-150-4I-NH
5
6
SST29LE010A-200-4C-U2
SST29VE010A Valid combinations
SST29VE010A-200-4C-EH
SST29VE010A-200-4C-NH
SST29VE010A-250-4C-EH
SST29VE010A-250-4C-NH
SST29VE010A-200-4C-WH
SST29VE010A-250-4C-WH
SST29VE010A-200-4I-EH
SST29VE010A-200-4I-WH
SST29VE010A-200-4I-NH
7
8
SST29VE010A-250-4C-U2
9
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Note:
10
The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
11
12
13
14
15
16
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
PACKAGING DIAGRAMS
pin 1 index
1
CL
.600
.625
32
.530
.550
1.645
1.655
.065
.075
7˚
4 PLCS.
.170
.200
Base Plane
Seating Plane
.015
.050
.070
.080
Note:
.045
.065
.016
.022
.120
.150
.100 BSC
0˚
15˚
.008
.012
.600 BSC
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.1
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
TOP VIEW
Optional Pin #1
Identifier
SIDE VIEW
.485
.495
.447
.453
.042
.048
2
1
.106
.112
32
.020 R.
MAX.
.023
x 30˚
.029
.030
R.
.040
.042
.048
.585
.595
BOTTOM VIEW
.547
.553
.013
.021
.400
BSC
.026
.032
.490
.530
.050
BSC.
.015 Min.
.075
.095
.050
BSC.
.125
.140
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
.026
.032
32.PLCC.NH-ILL.1
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
1.05
0.95
PIN # 1 IDENTIFIER
1
.50
BSC
2
.270
.170
8.10
7.90
3
4
0.15
0.05
12.50
12.30
5
0.70
0.50
Note:
6
14.20
13.80
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
7
32.TSOP-WH-ILL.3
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
8
9
1.05
0.95
PIN # 1 IDENTIFIER
.50
BSC
8.10
7.90
10
11
.27
.17
12
13
0.15
0.05
18.50
18.30
14
0.70
0.50
Note:
15
20.20
19.80
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
16
32.TSOP-EH-ILL.3
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM
SST PACKAGE CODE: EH
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1 Megabit Page-Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
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