8 Mbit / 16 Mbit (x16) Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet FEATURES: • Organized as 512K x16 / 1M x16 • Latched Address and Data • Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF800/160 - 2.7-3.6V for SST39VF800/160 • Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention • Low Power Consumption: - Active Current: 15 mA (typical) - Standby Current: 4 µA (typical) - Auto Low Power Mode: 4 µA (typical) • Sector-Erase Capability - Uniform 2 KWord sectors • Block-Erase Capability - Uniform 32 KWord blocks • Fast Read Access Time: - 55 ns for SST39LF800/160 - 70 and 90 ns for SST39VF800/160 • Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Word-Program Time: 14 µs (typical) - Chip Rewrite Time: 8 seconds (typical) for SST39LF/VF800 15 seconds (typical) for SST39LF/VF160 • Automatic Write Timing - Internal VPP Generation • End-of-Write Detection - Toggle Bit - Data# Polling • CMOS I/O Compatibility PRODUCT DESCRIPTION The SST39LF800/160 and SST39VF800/160 devices are 512K x16 / 1M x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF800/160 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF800/ 160 write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39LF800/160 and SST39VF800/160 devices provide a typical Word-Program time of 14 µsec.These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF800/160 and SST39VF800/160 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering • JEDEC Standard - Flash EEPROM Pinouts and command sets • Packages Available - 44-Pin SOIC (500mil) - 48-Pin TSOP (12mm x 20mm) - 48-Ball TFBGA (8mm x 10mm) power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39LF800/160 and SST39VF800/160 are offered in 44-pin SOIC, 48-pin TSOP and 48-pin TFBGA packages. See Figures 1, 2 and 3 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while © 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. 399-02 2/00 These specifications are subject to change without notice. 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with SectorErase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. The SST39LF800/160 and SST39VF800/160 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Read The Read operation of the SST39LF800/160 and SST39VF800/160 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Chip-Erase Operation The SST39LF800/160 and SST39VF800/160 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Word-Program Operation The SST39LF800/160 and SST39VF800/160 are programmed on a word-by-word basis. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39LF800/160 and SST39VF800/160 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF800/160 and SST39VF800/ 160 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15-DQ8 are “Don’t Care” during any SDP command sequence. Data# Polling (DQ7) When the SST39LF800/160 and SST39VF800/160 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 18 for a flowchart. Common Flash Memory Interface (CFI) The SST39LF800/160 and SST39VF800/160 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1’s and 0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 18 for a flowchart. Product Identification The Product Identification mode identifies the devices as the SST39LF/VF800, SST39LF/VF160 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39LF800/160 and SST39VF800/160. Users may wish to use the Software Product Identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 19 for the Software ID Entry command sequence flowchart. Data Protection The SST39LF800/160 and SST39VF800/160 provide both hardware and software features to protect nonvolatile data from inadvertent writes. TABLE 1: PRODUCT IDENTIFICATION TABLE Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Manufacturer’s Code 0000H 00BFH Device Code SST39LF/VF800 Device Code SST39LF/VF160 0001H 0001H 2781H 2782H Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform and Figure 19 for a flowchart. Software Data Protection (SDP) The SST39LF800/160 and SST39VF800/160 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command © 2000 Silicon Storage Technology, Inc. Data 2 3 4 5 6 7 8 9 10 11 12 399 PGM T1.0 Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Powered by ICminer.com Electronic-Library Service CopyRight 2003 Address 1 3 399-02 2/00 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet FUNCTIONAL BLOCK DIAGRAM EEPROM Cell Array X-Decoder Memory Address Address Buffer & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ15 - DQ0 399 ILL B1.0 SST39LF/VF160 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 SST39LF/VF800 SST39LF/VF800 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up SST39LF/VF160 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 399 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP TOP VIEW (balls facing down) TOP VIEW (balls facing down) 6 5 4 3 2 1 A13 A9 WE# NC A7 A3 A12 A8 NC NC A17 A4 A14 A10 NC A18 A6 A2 A15 A11 NC NC A5 A1 A16 NC 6 DQ15 VSS 5 DQ7 DQ14 DQ13 DQ6 4 DQ5 DQ12 VDD DQ4 A0 CE# A14 A15 A16 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC A19 DQ5 DQ12 VDD DQ4 NC NC A18 NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 CE# OE# VSS NC DQ15 VSS 2 DQ9 DQ1 1 OE# VSS A B C D E F G H SST39LF/VF800 A12 3 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 A13 A0 A B C D E F G H 399 ILL F02b.0 SST39LF/VF160 399 ILL F02.0 FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Top View Die Up NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Top View Die Up SST39LF/VF160 399 ILL F01a.1 SST39LF/VF800 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WE# A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD 1 2 3 4 5 399 ILL F01b.1 6 FIGURE 3: PIN ASSIGNMENTS FOR 44-PIN SOIC TABLE 2: PIN DESCRIPTION Symbol Pin Name AMS-A0 Address Inputs DQ15-DQ0 Data Input/output CE# OE# WE# VDD Chip Enable Output Enable Write Enable Power Supply Vss NC Ground No Connection Functions To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF800/160 2.7-3.6V for SST39VF800/160 Product Identification Hardware Mode Software Mode WE# VIH VIL VIL A9 AIN AIN X DQ DOUT DIN X X VIL X X X VIH X X X High Z High Z/ DOUT High Z/ DOUT VIL VIL VIH VH Manufacturer Code (00BF) Device Code (1) VIL VIL VIH AIN Note: (1) Device Code 2781 for SST39LF/VF800 and 2782 for SST39LF/VF160 (2) AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 © 2000 Silicon Storage Technology, Inc. 10 12 VIH X X Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 399 PGM T2.1 Note: AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 Standby Write Inhibit 8 11 Unconnected pins. TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Program VIL VIH Erase VIL VIH 7 5 Address AIN AIN Sector or block address, XXh for Chip-Erase X X X AMS(2) - A1 = VIL, A0 = VIL AMS(2) - A1 = VIL, A0 = VIH See Table 4 399 PGM T3.0 399-02 2/00 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr(1) Data 2nd Bus Write Cycle Addr(1) Data 3rd Bus Write Cycle Addr(1) Data 4th Bus Write Cycle Addr(1) Data 5th Bus Write Cycle Addr(1) Data 6th Bus Write Cycle Addr(1) Data Word-Program Sector-Erase Block-Erase Chip-Erase Software ID Entry CFI Query Entry Software ID Exit/ CFI Exit Software ID Exit/ CFI Exit 5555H 5555H 5555H 5555H 5555H 5555H XXH AAH AAH AAH AAH AAH AAH F0H 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H 55H 5555H 5555H 5555H 5555H 5555H 5555H A0H 80H 80H 80H 90H 98H WA(3) 5555H 5555H 5555H 2AAAH 2AAAH 2AAAH SAx(2) BAx(2) 5555H 5555H AAH 2AAAH 55H 5555H F0H Data AAH AAH AAH 55H 55H 55H 30H 50H 10H 399 PGM T4.0 Notes: (1) Address format A14-A0 (Hex). Addresses A15, A16, A17, and A18 are “Don’t Care” for Command sequence for SST39LF/VF800. Addresses A15, A16, A17, A18 and A19 are "Don't Care" for Command sequence for SST39LF/VF160. (2) SAx for Sector-Erase; uses AMS-A11 address lines BAx, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 (3) WA = Program word address (4) Both Software ID Exit operations are equivalent (5) DQ15 - DQ8 are “Don’t Care” for Command sequence (6) With AMS -A1 =0; SST Manufacturer Code = 00BFH, is read with A0 = 0, SST39LF/VF800 Device Code = 2781H, is read with A0 = 1. SST39LF/VF160 Device Code = 2782H, is read with A0 = 1. AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 (7) The device does not remain in Software Product ID Mode if powered down. TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF800 AND SST39LF/VF160 Address Data Data 10H 0051H 11H 0052H Query Unique ASCII string “QRY” 12H 0059H 13H 0001H Primary OEM command set 14H 0007H 15H 0000H Address for Primary Extended Table 16H 0000H 17H 0000H Alternate OEM command set (00H = none exists) 18H 0000H 19H 0000H Address for Alternate OEM extended Table (00H = none exits) 1AH 0000H Note 1: Refer to CFI publication 100 for more details. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 399 PGM T5.0 6 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF800 AND SST39LF/VF160 Address Data Data 1BH 0027H(1) VDD Min. (Program/Erase) 0030H(1) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 0036H VDD Max. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0004H Typical time out for Word-Program 2N µs (24 = 16 µs) 20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) Note: (1) 0030H for SST39LF800/160 and 0027H for SST39VF800/160 1 2 3 4 5 6 399 PGM T6.1 TABLE 7A: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF800 Address Data Data 27H 0014H Device size = 2N Bytes (14H = 20; 220 = 1M Bytes) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0000H y = 255 + 1 = 256 sectors (00FFH = 255) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) 31H 000FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y = 15 + 1 = 16 blocks (000FH = 15) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) 399 PGM T7a.0 TABLE 7B: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF160 Address Data Data 27H 0015H Device size = 2N Byte (15H = 21; 221 = 2M Bytes) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0001H y = 511 + 1 = 512 sectors (01FF = 511) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) 31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y = 31 + 1 = 32 blocks (001F = 31) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) 399 PGM T7.0 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 399-02 2/00 7 8 9 10 11 12 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................ -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ........................................................ -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SST39LF800/160 Range Ambient Temp VDD Commercial 0 °C to +70 °C 3.0 - 3.6V OPERATING RANGE FOR SST39VF800/160 Range Ambient Temp VDD Commercial 0 °C to +70 °C 2.7 - 3.6V Industrial -40 °C to +85 °C 2.7 - 3.6V AC CONDITIONS OF TEST Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 30 pF for SST39LF800/160 CL = 100 pF for SST39VF800/160 See Figures 15 and 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet TABLE 8: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF800/160 AND 2.7-3.6V FOR SST39VF800/160 Limits Symbol Parameter Min Max Units Test Conditions IDD ISB IALP ILI ILO VIL VILC VIH VIHC VOL VOH VH IH Power Supply Current Read Program and Erase Standby VDD Current Auto Low Power Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage 0.7 VDD Input High Voltage (CMOS) VDD-0.3 Output Low Voltage Output High Voltage VDD-0.2 Supervoltage for A9 pin 11.4 Supervoltage Current for A9 pin 20 25 20 20 mA mA µA µA 1 1 0.8 0.3 µA µA V V V V V V V µA 0.2 12.6 200 1 CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min. CE#=WE#=VIL, OE#=VIH, VDD=VDD Max. CE#=VIHC, VDD = VDD Max. CE#=VILC, VDD = VDD Max., all inputs = VIHC or VILC, WE# = VIHC VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. VDD = VDD Max. IOL = 100 µA, VDD = VDD Min. IOH = -100 µA, VDD = VDD Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max. 399 PGM T9.0 TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter (1) TPU-READ TPU-WRITE(1) Power-up to Read Operation Power-up to Program/Erase Operation Minimum Units 100 100 µs µs 2 3 4 5 6 7 8 9 399 PGM T10.0 10 Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition 11 Maximum CI/O(1) I/O Pin Capacitance VI/O = 0V 12 pF CIN(1) Input Capacitance VIN = 0V 6 pF 12 399 PGM T11.0 Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND(1) TDR(1) VZAP_HBM(1) 10,000 100 2000 Cycles Years Volts JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + IDD mA VZAP_MM(1) ILTH(1) Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up 14 15 16 JEDEC Standard 78 399 PGM T12.0 Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 13 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet AC CHARACTERISTICS TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF800/160 AND VDD = 2.7-3.6V FOR SST39VF800/160 SST39LF800/160-55 SST39VF800/160-70 SST39VF800/160-90 Symbol Parameter Min Max Min Max Min Max TRC Read Cycle Time 55 70 90 TCE Chip Enable Access Time 55 70 90 TAA Address Access Time 55 70 90 TOE Output Enable Access Time 30 35 45 (1) TCLZ CE# Low to Active Output 0 0 0 (1) TOLZ OE# Low to Active Output 0 0 0 TCHZ(1) CE# High to High-Z Output 15 20 30 (1) TOHZ OE# High to High-Z Output 15 20 30 (1) TOH Output Hold from Address 0 0 0 Change Units ns ns ns ns ns ns ns ns ns 399 PGM T13.1 Note: (1) This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH (1) WE# Pulse Width High TCPH (1) CE# Pulse Width High TDS Data Setup Time TDH (1) Data Hold Time TIDA (1) Software ID Access and Exit Time TSE Sector-Erase Block-Erase TBE TSCE Chip-Erase Min Max 20 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 100 Units µs ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 399 PGM T14.0 Note: (1) This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 1 TAA TRC ADDRESS AMS-0 2 TCE CE# 3 TOE OE# 4 TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 HIGH-Z DATA VALID Note: 5 TCHZ TOH TCLZ DATA VALID 6 AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 399 ILL F03.0 7 FIGURE 4: READ CYCLE TIMING DIAGRAM 8 INTERNAL PROGRAM OPERATION STARTS 9 TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR 10 TDH TWP WE# TAS 11 TDS TWPH OE# 12 TCH CE# 13 TCS DQ15-0 Note: XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) 14 399 ILL F04.0 AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 15 16 FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 Note: XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 399 ILL F05.0 AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA Note: DATA# DATA# AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 DATA 399 ILL F06.0 FIGURE 7: DATA# POLLING TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 1 ADDRESS AMS-0 2 TCE CE# TOES TOE TOEH 3 OE# 4 WE# 5 DQ6 Note: AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 6 TWO READ CYCLES WITH SAME OUTPUTS 399 ILL F07.0 7 FIGURE 8: TOGGLE BIT TIMING DIAGRAM 8 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA 9 TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 10 CE# 11 OE# 12 TWP WE# 13 DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 14 399 ILL F08.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 15 16 FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA BAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 50 SW0 SW1 SW2 SW3 SW4 SW5 399 ILL F17.0 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 FIGURE 10: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 399 ILL F18.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address AMS = Most significant address AMS = A18 for SST39LF/VF800 and A19 for SST39LF/VF160 FIGURE 11: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 1 THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001 2 3 CE# 4 OE# TIDA TWP WE# 5 TWPH DQ15-0 XXAA SW0 XX55 TAA XX90 SW1 00BF 6 Device ID 399 ILL F09.1 SW2 Device ID = 2781 for SST39LF/VF800 and 2782 for SST39LF/VF160 7 8 FIGURE 12: SOFTWARE ID ENTRY AND READ 9 THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 10 5555 11 CE# 12 OE# TIDA TWP 13 WE# TWPH DQ15-0 TAA XXAA XX55 XX98 SW0 SW1 SW2 14 399 ILL F20.0 15 16 FIGURE 13: CFI QUERY ENTRY AND READ © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 15 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 5555 2AAA AA 5555 55 F0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 SW2 399 ILL F10.0 FIGURE 14: SOFTWARE ID EXIT/CFI EXIT © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 1 VIHT VIT INPUT REFERENCE POINTS VOT OUTPUT 2 VILT 399 ILL F11.1 « AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% 90%) are <5 ns. Note: VIT–VINPUT Test VOT–VOUTPUT Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test 3 4 5 FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS 6 7 TO TESTER 8 TO DUT 9 CL 399 ILL F12.1 10 FIGURE 16: A TEST LOAD EXAMPLE 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 17 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet Start Load data: AA Address: 5555 Load data: 55 Address: 2AAA Load data: A0 Address: 5555 Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 399 ILL F13.0 FIGURE 17: WORD-PROGRAM ALGORITHM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 18 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 1 Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated 2 3 4 Read DQ7 Read word Wait TBP, TSCE, TSE or TBE 5 Read same word Program/Erase Completed No Is DQ7 = true data? 6 Yes No Does DQ6 match? 7 Program/Erase Completed 8 Yes 9 Program/Erase Completed 10 399 ILL F14.0 11 12 13 FIGURE 18: WAIT OPTIONS 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 19 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XXF0 Address: XX Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Wait TIDA Load data: XX98 Address: 5555 Load data: XX90 Address: 5555 Load data: XXF0 Address: 5555 Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 399 ILL F15.0 FIGURE 19: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 20 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence 1 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 2 Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA 3 4 Load data: XX80 Address: 5555 Load data: XX80 Address: 5555 5 Load data: XX80 Address: 5555 6 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA 7 8 9 Load data: XX10 Address: 5555 Load data: XX30 Address: SAX Load data: XX50 Address: BAX 10 11 Wait TSCE Wait TSE Wait TBE 12 Chip erased to FFFFH Sector erased to FFFFH 13 Block erased to FFFFH 14 399 ILL F16.0 15 FIGURE 20: ERASE COMMAND SEQUENCE 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 21 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet Device SST39xFxxx Speed Suffix1 Suffix2 - XXX XX XX Package Modifier J = 44 pins K = 48 pins Numeric = Die modifier Package Type E = TSOP (12mm x 20mm) B = TFBGA (0.8 mm pitch; 8mm x 10mm) S = SOIC (500 mil) Temperature Range C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns, 70 = 70 ns, 90 = 90 ns Device Density 800 = 8 Megabit 160 = 16 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V SST39LF800 Valid combinations SST39LF800-55-4C-EK SST39LF800-55-4C-BK SST39LF800-55-4C-SJ SST39VF800 Valid combinations SST39VF800-70-4C-EK SST39VF800-70-4C-BK SST39VF800-90-4C-EK SST39VF800-90-4C-BK SST39VF800-70-4C-SJ SST39VF800-90-4C-SJ SST39VF800-70-4I-EK SST39VF800-90-4I-EK SST39VF800-70-4I-SJ SST39VF800-90-4I-SJ SST39VF800-70-4I-BK SST39VF800-90-4I-BK SST39LF160 Valid combinations SST39LF160-55-4C-EK SST39LF160-55-4C-BK SST39LF160-55-4C-SJ SST39VF160 Valid combinations SST39VF160-70-4C-EK SST39VF160-70-4C-BK SST39VF160-90-4C-EK SST39VF160-90-4C-BK SST39VF160-70-4C-SJ SST39VF160-90-4C-SJ SST39VF160-70-4I-EK SST39VF160-90-4I-EK SST39VF160-70-4I-SJ SST39VF160-90-4I-SJ SST39VF160-70-4I-BK SST39VF160-90-4I-BK Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 22 399-02 2/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet PACKAGING DIAGRAMS 1.05 0.95 PIN # 1 IDENTIFIER 1 .50 BSC 2 .270 .170 3 12.20 11.80 4 5 0.15 0.05 18.50 18.30 0.70 0.50 Note: 6 7 20.20 19.80 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 8 48.TSOP-EK-ILL.4 48-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK 9 TOP VIEW BOTTOM VIEW 10.00 ± 0.20 10 5.60 0.80 11 6 6 5 5 4.00 4 3 2 2 1 1 0.30 ± 0.05 (48X) 0.80 13 H G F E D C B A A B C D E F G H A1 CORNER 14 A1 CORNER 1.10 ± 0.10 SIDE VIEW 0.15 SEATING PLANE 15 48ba TFBGA.BK8x10-ILL.7 0.21 ± 0.05 Note: 12 4 8.00 ± 0.20 3 1. Complies with the general requirements of JEDEC publication 95 MO-210, although some dimensions may be more stringent. (This specific outline variant has not yet been registered) 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 48-BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM SST PACKAGE CODE: BK © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 23 399-02 2/00 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160 Data Sheet 12.45 12.70 15.74 16.34 Pin #1 Identifier 28.30 28.70 45˚ 2.72 3.00 .33 .51 1.27 .10 .30 .19 .25 0˚ 0.47 1.15 8˚ 44.soic500mil-SJ-ILL.2 Note: 1. All linear dimensions are in millimeters (min/max). 2. Coplanarity: 0.1 (±.05) mm. 44-PIN SMALL OUTLINE IC (SOIC/500MIL) SST PACKAGE CODE: SJ Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 24 399-02 2/00