Alcatel 1964 TRX SDH / SONET integrated modules SERDES Transceiver (Transponder) STM-64 / OC-192 Description These SERDES Transceivers are intended to be used at 10 Gbit/s optical SDH and SONET bit rate and provide electrical accesses at lower 622 Mbit/s bit rate. The modules are housed in a space-saving 300-pin package, providing the same electrical access for overall applications. The transmitter side contains an in-house cooled EA-ILM laser with a laser driver and temperature control loop. The transmit path starts with 16 : 1 serializer Asic. The receiver contains an in-house III-V PIN detector with preamplifier in a front-end module, a main amplifier Asic, a clock and data recovery function with accurate decision circuit. The receive path ends with 1 : 16 deserializer Asic. The Alcatel 1964 TRX family is a range of SERDES transceivers modules, providing convenient and flexible optical interfaces for SDH / SONET systems operating at 9.95 Gbit/s or 10.709 Gbit/s and exceed the applicable ITU-T G.691, Telcordia GR-253-ed.3 and Optical Interworking Forum OIF99.102 standards. Features • New International Standard • Multisource Optical Interfaces • Upward compatibility with the different features • Applications: Short-Reach or Intra-Office (25 km) and Intermediate-Reach or ShortHaul (40 km) • Optical 9.95 Gbit/s rate or 10.709 Gbit/s rate (FEC) • Electrical 622 Mbit/s rate or 669 Mbit/s rate (FEC) • Operating at 1.5 µm wavelength • Full performance in operating case temperature from - 5 to + 65 °C • Space-saving package : 3.5 inch x 4 inch (8.9 cm x 10.16 cm) • Alcatel Reliability and Qualification Program for built in quality Transmitter: • EA-ILM 1.5µ cooled laser • Up to +2 dBm optical output • 16x2 input data 622 Mbit/s LVDS • 1x2 ref. clock 155 or 622 MHz PECL compatible • Shut down command • Analog monitoring • Digital alarms • Power supplies: +5 V, - 5 V & + 3.3 V • Power consumption: 4.2 W typical Receiver: • InGaAs PIN-preamp detector • High typical sensitivity - 15 dBm • 16x2 output data 622 Mbit/s LVDS • 1x2 ref. clock 155 MHz PECL compatible • Analog monitoring • Digital alarms • Power supplies: +5 V, - 5 V & + 3.3 V • Power consumption: 2.8 W typical Applications Used in transmission systems from high-speed for intermediate-reach to long-reach applications, the Alcatel 1900 TRX family operates at SONET OC-192 rates as well as at ITU-T SDH STM-64 rates. Covering all types of SDH / SONET optical interfaces (tributaries and aggregates) the Alcatel 1900 TRX modules are suitable for line systems, Add Drop Multiplexers and digital cross-connects as well as ATM or IP switches and routers. As part of the global Alcatel 1900 TRX family, the Alcatel 1964 TRX ShortHaul module is the first version for all types of STM-64 (Intra-office, ShortHaul and Long-Haul) and OC-192 (Short-Reach, Intermediate-Reach and Long-Reach) optical interfaces. These modules ensure ease of use and offer new flexibility to get 10 Gbit/s optical links to system designers. Optical characteristics Condition Target distance Optical budget Dispersion Path penalty Transmitter Center wavelength Optical output power Spectral width SMSR Extinction ratio Shutdown optical power Generated jitter Return loss Receiver Receiver sensitivity Receiver overload Generated jitter Reflectance Symb Note 1 Note 1 Note 1 Note 3 Note 4 Note 5 λc SNOM ∆λ Er SIDLE Min Typ Max I-64.2 / SR-2 25 0 7 500 2 1530 -5 1550 30 8.2 RNOM RNOM -50 - 14 -1 1530 -1 -40 0.1 24 - 15 - 14 -1 Unit Km dB ps/nm dB 1550 1565 +2 1 -50 -40 0.1 24 nm dBm nm dB dB dBm UIpp dB 0.1 - 27 dBm dBm UIpp dB 30 8.2 Note 2 Note 6 Note 6 Note 2 1565 -1 1 Min Typ Max S-64.2b / IR-2 40 3 11 800 2 - 15 0.1 - 27 Note 1: Optical budgets are defined based on Telcordia GR-253-ed.3 & ITU-T G.691. Note 2: From 50 kHz to 80 MHz bandwidth and no jitter on TxREFCLK. Note 3: Measured at connector interface. Note 4: The maximum full width of the central wavelength peak; measured 20 dB down from the maximum amplitude under modulation condition NRZ at 9.95328 Gbit/s and PRBS 223-1. Note 5: Measured at connector interface under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1. Note 6: Measured at BER 10-12 and under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1 All parameters are specified End-of-Life within the overall relevant operating temperature range. The typical values are referenced to + 25 °C, nominal power supply, beginning of life. Electrical characteristics Parameter Negative supply voltage Negative supply current 1st Positive supply voltage 1st Positive supply current 2nd Positive supply voltage 2nd Positive supply current Power dissipation Common mode LVDS input voltage Differential LVDS input swing LVDS output differential voltage LVDS differential input impedance LVTTL input low voltage LVTTL input high voltage LVTTL input low current LVTTL input high current LVTTL output low voltage LVTTL output high voltage LVPECL differential input voltage swing Condition Symbol VEE IEE VDD IDD VCC ICC Min - 4.94 LVDSVI LVDSVIDTH LVDSVOD LVDSRIN LVTTLVIL LVTTLVIH LVTTLIIL LVTTLIIH LVTTLVOL LVTTLVOH LVPECL VDIF 800 100 250 80 0 2.0 -500 3.13 4.75 Total Note 7 VIN = 0.5 V VIN = 2.4 V IOL = 4 mA IOH = -100 µA Note 8 Typical - 5.2 900 3.3 760 5.0 130 7.0 Max - 5.45 1300 3.47 2000 5.25 200 14 1700 1000 600 120 0.8 3.3 50 0.4 2.4 300 930 Unit V mA V mA V mA W mV mV mVpp Ω V V µA µA V V mV Note 7: Peak to peak single ended voltage. Note 8: Internally AC coupled All parameters are specified End-of-Life within the overall relevant operating temperature range. The typical values are referenced to + 25 °C, nominal power supply, beginning of life. Outline drawing Framer to Transceiver clocking Clocking definition TxREFCLK SONET Framer OC192 SERDES TxREFCLK Transmitter Reference Clock Input: Differential clock PECL compatible input, internally AC coupled with 50 Ω terminated. TxDin Transmitter Parallel Data Input: Differential 622 Mbit/s LVDS input, internally 100 Ω differential terminated. TxPICLK Transmitter Reference Parallel Clock Input: Differential clock LVDS input, internally 100 Ω differential terminated. TxPCLK Transmitter Reference Parallel Clock Output: Differential clock LVDS output. TxMCLK Transmitter Monitor Clock: LVDS clock output signal. This signal represents the synthesized frequency of the serializer. RxDout Receiver Parallel Data Output: Differential 622 Mbit/s LVDS output. RxPOCLK Receiver Reference Parallel Clock Output: Differential clock LVDS output. RxMCLK Receiver Monitor Clock: Differential LVDS output signal. This signal represents the PLL VC0 clock. RxREFCLK Receiver Reference Clock Input: Differential clock PECL compatible input. TxDin TxPICLK TxPCLK RxDout RxPOCLK RxMCLK RxREFCLK TxMCLK Pin out from customer line card K 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 H FGND FGND FFU FGND FGND FFU RxAGND RxAGND FFU RxAGND RxAGND FFU RxAGND RxAGND TBD TxAGND TxAGND FFU TxAGND TxAGND FFU TxAGND TxAGND FFU FGND FGND FFU FGND FGND FFU Receiver power & GND supplies Receiver d.c. signals 622 differential signals Receiver pin description RxDout##P G RxDout12P RxDout12N RxDigGND RxDout13P RxDout13N RxDigGND RxDout14P RxDout14N RxDigGND RxDout15P RxDout15N RxDigGND FFU FFU RxDigGND TxDin12P TxDin12N TxDigGND TxDin13P TxDin13N TxDigGND TxDin14P TxDin14N TxDigGND TxDin15P TxDin15N TxDigGND TxPICLKP TxPICLKN TxDigGND F FFU FFU RxPOWMON Rx3.3VD Rx3.3VD RxPOWALM Rx3.3VD Rx3.3VD FFU Rx-5.2VD Rx-5.2VD FFU Rx-5.2VD Rx-5.2VD FFU FFU FFU LsBIASMON Tx3.3VD Tx3.3VD LsENABLE Tx3.3VD Tx3.3VD LsBIASALM Tx-5.2VD Tx-5.2VD LsTEMPALM Tx-5.2VD Tx-5.2VD TxREFSEL RxPOCLKN RxREFCLKP D RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU TxDigGND TxDigGND LsPOWMON TxDigGND TxDigGND LsTEMPMON TxDigGND TxDigGND FFU TxDigGND TxDigGND FFU TxDigGND A TxDigGND FFU Transmitter power & GND supplies Transmitter d.c. signals 622 differential signals RxREFCLKN Receiver NRZ Data Output Positive: 622 Mbit/s LVDS output signal. Data are RxMCLKP synchronized at the output of the module with the output clock RxPOCLK signal. RxDout15 is the most significant RxMCLKN bit and first bit received. RxDout##N Receiver NRZ Data Output Negative: 622 Mbit/s LVDS output signal. Data are RxLCKREF synchronized at the output of the module with the output clock RxPOCLK signal. RxDout15 is the most significant bit and first bit received. RxPOCLKP E RxDout8P RxDout8N RxDigGND RxDout9P RxDout9N RxDigGND RxDout10P RxDout10N RxDigGND RxDout11P RxDout11N RxDigGND RxPOCLKP RxPOCLKN RxDigGND TxDin8P TxDin8N TxDigGND TxDin9P TxDin9N TxDigGND TxDin10P TxDin10N TxDigGND TxDin11P TxDin11N TxDigGND TxPCLKP TxPCLKN TxDigGND Receiver Parallel Output Clock Positive: 622 MHz LVDS output. Regenerated clock synchronized to the data. The falling edge of RxRESET RxPOCLKP is in the middle of the data pattern. C B A RxDout4P RxDout4N RxDigGND RxDout5P RxDout5N RxDigGND RxDout6P RxDout6N RxDigGND RxDout7P RxDout7N RxDigGND RxMCLKP RxMCLKN RxDigGND TxDin4P TxDin4N TxDigGND TxDin5P TxDin5N TxDigGND TxDin6P TxDin6N TxDigGND TxDin7P TxDin7N TxDigGND Tx155MCKP Tx155MCKN TxDigGND RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDigGND RxDigGND RxLCKREF RxDigGND RxDigGND FFU RxDigGND RxDigGND RxLOCKERR TxDigGND TxDigGND TxSKEWSEL0 TxDigGND TxDigGND TxSKEWSEL1 TxDigGND TxDigGND FFU TxDigGND TxDigGND TxPICLKSEL TxDigGND TxDigGND TxLOCKERR RxDout0P RxDout0N RxDigGND RxDout1P RxDout1N RxDigGND RxDout2P RxDout2N RxDigGND RxDout3P RxDout3N RxDigGND RxREFCLKP RxREFCLKN RxDigGND TxDin0P TxDin0N TxDigGND TxDin1P TxDin1N TxDigGND TxDin2P TxDin2N TxDigGND TxDin3P TxDin3N TxDigGND TxREFCLKP TxREFCLKN TxDigGND NUC FFU No User Connection Reserve For Future Use Receiver Reference Clock Negative: 155 MHz PECL , compatible, internally AC coupled 50 Ω terminated. Transmitter 19 J FFU FFU FFU NUC NUC NUC FFU FFU NUC FFU FFU NUC FFU FFU NUC FFU FFU NUC FFU FFU FFU FFU FFU NUC NUC NUC NUC FFU FFU NUC Receiver 5 Rx+5VA Rx+5VA RxRATESEL Rx3.3VA Rx3.3VA RxRESET FFU FFU FFU Rx-5.2VA Rx-5.2VA FFU Rx-5.2VA Rx-5.2VA FFU Tx+5VA Tx+5VA FFU Tx3.3VA Tx3.3VA TxRATESEL Tx3.3VA Tx3.3VA TxRESET Tx-5.2VA Tx-5.2VA FFU Tx-5.2VA Tx-5.2VA FFU RxLOCKERR Receiver Loss of Clock Error: LVTTL output alarm. Set to logic low when the clock recovery is not locked onto the optical data stream. Set to logic high in Receiver Monitor Clock Positive: normal operation. 622 MHz LVDS output signal. RxRATESEL Receiver rate Selection : LVTTL This signal represents the input command. Selects the bit PLL VC0 clock. rate. When is at logic high, the Receiver Monitor Output Clock standard 9.95328Gbits/s bit Negative: 622 MHz LVDS rate is selected, if it’s logic low output signal. This signal the FEC bit rate 10.709Gbit/s represents the PLL VC0 clock. is selected. Note that in this Receiver Lock Clock Reference: case the RxREFCLK frequency LVTTL input command. Selects has to be 167.328MHz. the reference frequency mode Reserve For Future Use. of RxPOCLK. When is at logic FFU low, the RxPOCLK is forced to NUC lock to the RxREFCLK. When at logic high, the RxPOCLK is locked to the CDR reference clock. Receiver deserializer RESET: LVTTL input command. When at logic low, the deserializer function is reinitialized. Receiver Parallel Output Clock Negative: 622 MHz output RxPOWMON Receiver Power Monitoring: signal. Regenerated clock analog output monitor. This synchronized to the data. The voltage is proportional to the rising edge of RxPOCLKN is in mean optical input power. the middle of the data pattern. Typical slope is 1 V / mW from Receiver Reference Clock –1 to–17dBm. Positive: 155 MHz PECL, RxPOWALM Receiver Power Alarm: LVTTL compatible, internally AC output alarm. Set to logic low coupled 50 Ω terminated. when the incoming optical power is less than –17dBm+/2dB. No User Connection. Transmitter pin description TxDin##P TxDin##N TxPICLKP TxPICLKN TxPCLKP TxREFCLKN Transmitter NRZ Data Input Positive: 622 Mbit/s LVDS input signal. Data are retimed at the input of the module by the input clock TxPICLK signal. TxDin15 is the most significant and the first bit transmitted TxMCLKP Transmitter NRZ Data Input Negative: 622 Mbit/s LVDS input signal. Data are retimed at the input of the module by the input clock TxPICLK signal. TxMCLKN TxDin15 is the most significant and the first bit transmitted. Transmitter Parallel Input Clock Positive: 622 MHz or 311 MHz LVDS input signal. When TxPICLKSEL TxPICLKSEL is at logic low, the frequency has to be 622 MHz and the rising edge of TxPICLKN is in the middle of the data pattern. When TxPICLKSEL is at logic high, the frequency has to be 311 MHz and the rising/falling edges of TxREFSEL TxPICLKN are in the middle of the data crossing point. Transmitter Parallel Input Clock Negative: 622 MHz or 311 MHz LVDS input signal. When TxPICLKSEL is at logic low, the frequency has to be 622 MHz TxSKEWSEL0 and the falling edge of TxPICLKN is in the middle of the data pattern. When TxPICLKSEL is at logic high, the frequency has to be 311 MHz and the falling edge of TxPICLKN is in the middle of the data crossing TxSKEWSEL1 point. Transmitter Parallel Clock output Positive: 622 MHz LVDS output signal. Reference clock generated from the TxREFCLK TxRATESEL signal. Usable to synchronize the output data stage of the framer ASIC. TxPCLKN Transmitter Parallel Clock output Negative: 622 MHz LVDS output signal. Reference clock generated from the TxREFCLK signal. Usable to synchronize the output data stage of the framer ASIC. TxREFCLKP Transmitter Reference Clock TxRESET Positive: 622 MHz or 155 MHz PECL compatible input signal. When TxREFSEL0 is at logic low, the frequency is 155 MHz. LsENABLE When RxREFSEL0 is at logic high, the frequency is 622 MHz. Transmitter Reference Clock Negative: 622 MHz or 155 MHz PECL compatible input signal. When TxREFSEL0 is at logic low, the frequency is 155 MHz. When RxREFSEL0 is at logic high, the frequency is 622 MHz. Transmitter Monitor Clock Positive: 155 MHz LVDS clock output signal. This signal represents the synthesized frequency of the serializer. Transmitter Monitor Clock Negative: 155 MHz LVDS clock output signal. This signal represents the synthesized frequency of the serializer. Transmitter Parallel Clock Select: LVTTL input command. Selects the reference frequency mode of TxPICLK. When at logic low, the frequency has to be 622 MHz. When at logic high, the frequency has to be 311 MHz. Transmitter Reference clock Select : LVTTL input command. Selects the reference frequency mode of TxREFCLK. When at logic low, the frequency is 155 MHz. When at logic high, the frequency is 622 MHz. Transmitter Adjusts Skew of TxPICLK Select: LVTTL input command. This LSB digital logic input allows delaying internally the TxPICLK in the 311 MHz mode. Transmitter Adjusts Skew of TxPICLK Select: LVTTL input command. This MSB digital logic input allows delaying internally the TxPICLK in the 311 MHz mode. Transmitter Rate Selection: LVTTL input command. Selects the bit rate. When is at logic high, the standard 9.95328Gbits/s bit rate is selected, if it’s logic low the FEC bit rate 10.709Gbit/s is selected. Note that in this case the TxREFCLK frequency has to be 167.328MHz or 669.312MHz. Transmitter serializer RESET: LVTTL input command. When at logic low, the serializer function is reinitialized. Laser Enable: LVTTL input command. When at logic high, the laser is disabled. When at logic low, the laser is enabled. TxLOCKERRTransmitter Lock Error: LVTTL output alarm. When at logic low, it indicates that the serializer is not locked on the TxREFCLK. When at logic high, the serializer is in normal operating. LsBIASALM Laser Bias Alarm: LVTTL output alarm. When at logic low, the laser has reached its end of life condition. When at logic high, the laser is in normal operating. LsTEMPALM Laser Temperature Alarm: LVTTL output alarm. When at logic low, the laser temperature is approximately 3°C above or below the normal operating. When at logic high, the laser is in normal operating. LsBIASMon Laser Bias Monitoring: analog output monitor. This voltage is proportional to the laser current. The typical slope is 20 mV / mA. LsPOWMon Laser Power Monitoring: analog output monitor. This voltage is proportional to the laser output power. Normalized at 0.5V over lifetime, the 50 % drift in output power correlates with a 50 % variation in output voltage. LsTEMPMonLaser temperature Monitoring: analog output monitor. This voltage represents the laser temperature deviation. Normalized at 2.5V over lifetime. FFU Reserved for further additional features. NUC No User Connection. This pin has to be left open. July 2001 Copyright © 2001 Alcatel Optronics Absolute maximum ratings Parameter Maximum optical input power Negative supply voltage 1st Positive supply voltage 2nd Positive supply voltage Control input voltage Digital output voltage Analog output voltage Alarm output voltage Storage temperature Storage 72h max Operating case temperature Symbol Min VEE VDD VCC -6 0 0 0 0 0 0 - 20 - 40 -5 TSTG TOP Max +2 0 + 3.6 +6 VDD VDD VDD VDD + 70 + 85 + 65 Unit dBm V V V V V V V °C °C °C Customized versions are available for large quantities. Performance figures contained in this document must be specifically confirmed in writing by Alcatel Optronics before they become applicable to any particular order or contract. Alcatel Optronics reserves the right to make changes to the products or information contained herein without notice. Ordering information Alcatel 1964 TRX Dispersion (ps/nm) I-64.2 / SR-2 400 I-64.2 / SR-2 FEC 400 S-64.2b / IR-2 800 S-64.2b / IR-2 FEC 800 Options 3CN xxxxx xA → FC/PC xB → SC/PC Span (km) 25 25 40 40 Part Number 3CN 00576 xx 3CN 00578 xx 3CN 00532 xx 3CN 00577 xx Ax → With heat sink Bx → Without heat sink Standards Compliant with ITU-T G.691 Telcordia GR-253-ed.3 Optical Interworking Forum OIF99.102 Optical fiber according to ITU-T G.652 Environment according to IEC 68-2 and MIL STD 883 Telcordia TR-EOP-000063 LASER RADIATION AVOID EXPOSURE TO BEAM Class 3A laser product ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC DISCHARGE SENSITIVE DEVICES EUROPE Route de Villejust F-91625 NOZAY CEDEX Tel : (+33) 1 64 49 49 10 Fax : (+33) 1 64 49 49 61 USA 15036, Conference Centre Drive CHANTILLY - VA 20151 Tel : (+1) 703 679 3600 Fax : (+1) 703 679 6667 CANADA 45, De Villebois, suite 200 Gatineau (PQ) Canada, J8T 8J7 Tel : (+1) 703 715 3922 Fax : (+1) 703 860 1183 JAPAN Dai-Tokyo Kasai Shinjuku Building 13F 3-25-3, Yoyogi, Shibuya-Ku TOKYO 151 - 0053 Tel : (+81) 3 5302 4341 Fax : (+81) 3 5302 4331