REVISIONS LTR DESCRIPTION A DATE (YR-MO-DA) Update boilerplate to MIL-PRF-38535 requirements. - LTG 01-03-28 APPROVED Thomas M. Hess REV SHEET 35 REV SHEET 15 16 17 REV STATUS OF SHEETS 18 19 20 21 REV A SHEET 1 22 23 24 25 A 2 3 A A A A 26 27 28 29 30 31 32 33 34 6 7 8 9 10 11 12 13 14 A 4 5 PREPARED BY PMIC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil Larry T. Gauder STANDARD MICROCIRCUIT DRAWING CHECKED BY Thanh V. Nguyen APPROVED BY Thomas M. Hess THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 00-10-31 REVISION LEVEL AMSC N/A MICROCIRCUIT, DIGITAL, CMOS, RADIATION HARDENED MICROPROCESSOR, MONOLITHIC SILICON SIZE A CAGE CODE A SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-01502 67268 1 OF 35 5962-E306-01 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H Federal stock class designator \ 01502 RHA designator (see 1.2.1) 01 Q X X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 02 UT1750AR-12 MHz UT1750AR-16 MHz Radiation hardened microprocessor, 12-MHz operating frequency Radiation hardened microprocessor, 16-MHz operating frequency 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class M Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Descriptive designator CMGA7-P145 CQCC1-F132 Terminals 145 1/ 132 Package style Pin grid array Flat pack, unformed leads 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. ________ 1/ Pin D4 is an index pin. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 2 1.3 Absolute maximum ratings. 1/ DC supply voltage (VDD) ................................................................................... Voltage on any pin (VI/O) .................................................................................. DC input current (II) .......................................................................................... Storage temperature (TSTG) .............................................................................. Latchup immunity (ILU) ..................................................................................... Maximum power dissipation (PD) ...................................................................... Maximum junction temperature (TJ) ................................................................. Thermal resistance, junction-to-case (θJC) ........................................................ -0.3 V to +7.0 V -0.3 V to VDD +0.3 V ±10 mA -65°C to +150°C ±150 mA 2/ 600 mW +175°C 10°C/W 2/ 1.4 Recommended operating conditions. DC supply voltage (VDD).................................................................................... Temperature range (TC) .................................................................................... DC input voltage (VIN) ....................................................................................... Radiation features: Total dose (Dose rate = 50 – 300 rad/s) ........................................................ Single event phenomenon (SEP) effective linear energy threshold, no upsets or latchup (see 4.4.4.4) ....................... Dose rate upset (20 ns pulse)........................................................................ Dose rate latchup.......................................................................................... Dose rate survivability ................................................................................... Neutron irradiation ........................................................................................ 4.5 V to 5.5 V -55°C to +125°C 0 V to VDD ≥ 1 x 106 Rads (Si) 55 MeV/(mg/cm2) 3/ 3/ 3/ > 1 X 1014 neutron/cm2 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) ................................................ 83.7 percent 2/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Methods and Procedures for Microelectronics. Interface Standard Electronic Component Case Outlines. _________ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Test per MIL-STD-883, method 1012. 3/ When characterized as a result of the procuring activities request, the condition will be specified. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 3 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings (SMD's). Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as pecified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as specified on figure 4. 3.2.5 Radiation exposure connections. The radiation exposure connections shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 4 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. b. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125°C, minimum. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 5 TABLE IA. Electrical performance characteristics. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device Type Min Low level input voltage, TTL inputs 3/ VIL1 Low level input voltage, OSC inputs 3/ VIL2 High level input voltage, TTL inputs 3/ 4/ VIH1 High level input voltage, OSC inputs 3/ VIH2 High level output voltage, TTL outputs VOH1 High level output voltage, OSC outputs VOH2 IOH = -100 µA 1, 2, 3 All Low level output voltage, TTL outputs VOL1 IOL = 3.2 Ma 1, 2, 3 All Low level output voltage, OSC outputs VOL2 IOL = 100 µA 1, 2, 3 All Input leakage current, inputs without resistors IIN1 VIN = VDD or VSS 1, 2, 3 All Input leakage current, inputs with pull-up resistors IIN2 Input leakage current, inputs with pull-down resistors 1, 2, 3 Unit Limits Max 0.8 All 1.2 1, 2, 3 All 2.0 V 3.6 IOH = -400 µA 1, 2, 3 All IOH = -800 µA 5/ 2.4 V 2.4 3.5 0.4 1.0 -10 10 VIN = VSS -900 -80 IIN3 VIN = VDD 80 900 Three-state output leakage current IOZ VO = VDD or VSS -10 +10 -20 5/ +20 5/ Short circuit output current 6/ 7/ IOS -100 100 -200 5/ 200 5/ 1, 2, 3 VDD = 5.5 V, VO = 0 V to VDD 1, 2, 3 All All VDD = 5.5 V, VO = 0 V IDD Quiescent current QIDD 9/ CIN Output capacitance COUT Bidirect I/O capacitance CI/O Functional tests 3/ f = 12 MHz, CL = 50 pF 1, 2, 3 All f = 16 MHz, CL = 50 pF Input capacitance V 0.4 IOL = 6.4 mA 5/ Average operating current 6/ 8/ V µA µA mA 50 mA 75 1, 2, 3 All 1 mA 4 All 10 pF 4 All 15 pF 4 All 20 pF 7, 8 All f = 1 MHz at 0 V See 4.4.1c See 4.4.1b See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 6 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Group A subgroups Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Device type Unit Limits Min Max 01 0 42 02 0 33 01 0 39 02 0 33 01 0 51 02 0 42 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 54 02 0 45 01 0 37 02 0 35 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 54 02 0 41 01 --- 50 02 --- 38 01 0 51 02 0 42 01 0 73 02 0 55 01 --- 50 02 --- 38 01 0 54 02 0 41 I/O READ CYCLE OSCIN low to STATE1 high t34a* OSCIN low to STATE1 low t34b* See figure 4 9, 10, 11 9, 10, 11 t34c* 9, 10, 11 OSCIN low to AS active t34d* 9, 10, 11 OSCIN low to AS inactive t34e 9, 10, 11 SCIN low to AS high Z OSCIN low to DS inactive OSCIN low to DS active OSCIN high to DS inactive OSCIN low to DS high Z OSCIN low to R/ WR active t34f* t34g* 9, 10, 11 t34i 9, 10, 11 t34j t34k OSCIN low to M/ IO low t34l* OSCIN low to M/ IO high Z 9, 10, 11 t34h* OSCIN low to R/ WR high Z OSCIN high to M/ IO high 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 t34m* 9, 10, 11 t34n 9, 10, 11 9, 10, 11 t34o* OSCIN low to OP/IN high ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 7 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ t34p* Group A Test conditions 2/ subgroups -55°C ≤ TC ≤ +125°C unless otherwise specified I/O READ CYCLE -Continued See figure 4 9, 10, 11 OSCIN high to OP/ IN low t34q 9, 10, 11 OSCIN low to OP/ IN high Z OSCIN low to address valid OSCIN high to address t34r* 9, 10, 11 t34s 9, 10, 11 invalid Data setup time Data hold time t34t 9, 10, 11 t34u 9, 10, 11 Device type Unit Limits Min Max 01 0 71 02 0 53 01 --- 53 02 --- 40 01 0 57 02 0 45 01 --- 55 02 --- 41 01 0 --- 02 0 --- 01 34 ---- 02 26 --- 01 0 42 02 0 33 01 0 39 02 0 33 01 0 51 02 0 42 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 54 02 0 45 01 0 37 02 0 35 ns I/O WRITE CYCLE OSCIN low to STATE1 high t35* OSCIN low to STATE1 low t35b* OSCIN low to AS active OSCIN high to AS inactive OSCIN low to AS high Z OSCIN low to DS inactive OSCIN low to DS active 9, 10, 11 See figure 4 9, 10, 11 t35c* 9, 10, 11 t35d* 9, 10, 11 t35e 9, 10, 11 t35f* 9, 10, 11 t35g* 9, 10, 11 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 8 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Unit Limits Min Max 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 51 02 0 42 01 --- 50 02 --- 38 01 0 51 02 0 42 01 0 73 02 0 55 01 --- 50 02 --- 38 01 0 54 02 0 41 01 0 71 02 0 53 01 --- 53 02 --- 40 01 0 57 02 0 45 01 --- 55 02 --- 41 01 0 64 02 0 48 01 --- 80 02 --- 60 01 0 72 02 0 54 I/O WRITE CYCLE – Continued OSCIN high to DS inactive OSCIN low to DS high Z t35h* t35j* OSCIN low to R/ WR high Z t35k OSCIN low to M/ IO low t35l* OSCIN low to M/ IO high Z OSCIN low to OP/ IN high OSCIN high to OP/ IN low OSCIN low to OP/ IN high Z OSCIN low to address valid 9, 10, 11 t35i OSCIN low to R/ WR inactive OSCIN high to M/ IO high See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 t35m* 9, 10, 11 t35n 9, 10, 11 t35o* 9, 10, 11 t35p* 9, 10, 11 t35q 9, 10, 11 t35r* OSCIN high to address invalid t35s OSCIN low to data valid t35t* OSCIN high to data invalid (high Z) t35u OSCIN high to R/ WR high t35v* 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 9 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type 9, 10, 11 Unit Limits Min Max 01 0 42 02 0 33 01 0 39 02 0 33 01 0 51 02 0 42 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 54 02 0 45 01 0 37 02 0 35 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 54 02 0 42 01 --- 50 02 --- 38 01 0 53 02 0 42 01 --- 50 02 --- 38 01 0 54 02 0 41 MEM READ CYCLE OSCIN low to STATE1 high t36a* OSCIN low to STATE1 low t36b* OSCIN low to AS active OSCIN high to AS inactive OSCIN low to AS high Z OSCIN low to DS inactive OSCIN low to DS active OSCIN high to DS inactive OSCIN low to DS high Z 9, 10, 11 t36e 9, 10, 11 t36f* 9, 10, 11 t36g* 9, 10, 11 t36h* 9, 10, 11 t36i OSCIN low to R/ WR high Z t36k OSCIN low to OP/ IN high 9, 10, 11 t36d* t36j* OSCIN low to M/ IO high Z 9, 10, 11 t36c* OSCIN low to R/ WR inactive OSCIN low to M/ IO high See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 t36l* 9, 10, 11 t36n 9, 10, 11 t36o* 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 10 TABLE IA. Electrical performance characteristics – Continued. Test OSCIN high to OP/ IN low OSCIN low to OP/ IN high Z OSCIN low to address valid Symbol 1/ Group A Test conditions 2/ subgroups -55°C ≤ TC ≤ +125°C unless otherwise specified MEM READ CYCLE - Continued t36p* See figure 4 t36q 9, 10, 11 t36r* OSCIN high to address invalid t36s Data setup time t36t Data hold time 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 t36u 9, 10, 11 Device type Unit Limits Min Max 01 0 71 02 0 53 01 --- 53 02 --- 40 01 0 57 02 0 45 01 --- 55 02 --- 41 01 0 --- 02 0 --- 01 34 --- 02 26 --- 01 0 42 02 0 33 01 0 39 02 0 33 01 0 51 02 0 42 01 0 50 02 0 38 01 --- 50 02 --- 38 ns MEM WRITE CYCLE OSCIN low to STATE1 high t37a* OSCIN low to STATE1 low t37b* OSCIN low to AS active OSCIN high to AS inactive OSCIN low to AS high Z See figure 4 9, 10, 11 9, 10, 11 t37c* 9, 10, 11 t37d* 9, 10, 11 t37e 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 11 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Unit Limits Min Max 01 0 54 02 0 45 01 0 37 02 0 35 01 0 50 02 0 38 01 --- 50 02 --- 38 01 0 51 02 0 42 01 --- 50 02 --- 38 01 0 53 02 0 42 01 --- 50 02 --- 38 01 0 54 02 0 41 01 0 71 02 0 53 01 --- 53 02 --- 40 01 0 57 02 0 45 01 --- 55 02 --- 41 01 0 64 02 0 48 01 --- 80 02 --- 60 01 0 72 02 0 54 MEM WRITE CYCLE – Continued OSCIN low to DS inactive OSCIN low to DS active OSCIN high to DS inactive OSCIN low to DS high Z OSCIN low to R/ WR active t37f* OSCIN low to address valid 9, 10, 11 t37j* t37l* OSCIN low to OP/ IN high Z 9, 10, 11 t37i OSCIN low to M/ IO high OSCIN high to OP/ IN low 9, 10, 11 t37h* t37k OSCIN low to OP/ IN high 9, 10, 11 t37g* OSCIN low to R/ WR high Z OSCIN low to M/ IO high Z See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 t37n 9, 10, 11 t37o* 9, 10, 11 t37p* 9, 10, 11 t37q 9, 10, 11 t37r* OSCIN high to address invalid t37s OSCIN low to data valid t37t* OSCIN high to data invalid (high Z) t37u OSCIN high to R/ WR high t37v* 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 12 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Unit Limits Min Max 01 0 42 02 0 33 01 0 39 02 0 33 01 0 54 02 0 41 01 0 58 02 0 44 01 15 --- 02 15 --- 01 0 --- 02 0 --- 01 0 53 02 0 42 01 --- 55 02 --- 41 01 10 --- 02 10 --- 01 0 --- 02 0 --- 01 15 --- 02 10 --- 01 10 --- 02 10 --- 01 0 39 02 0 33 01 0 42 02 0 33 01 0 52 02 0 39 DMA NO WAIT STATE OSCIN low to STATE1 high t38a* OSCIN low to STATE1 low t38b* OSCIN high to BRQ low OSCIN low to BRQ high BGNT setup time BGNT hold time 9, 10, 11 9, 10, 11 t38e 9, 10, 11 t38f OSCIN low to BGACK high Z t38h DTACK setup time t38i BUSY hold time 9, 10, 11 t38d* t38g* BUSY setup time 9, 10, 11 t38c* OSCIN low to BGACK active DTACK hold time See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 t38j 9, 10, 11 t38k 9, 10, 11 t38l 9, 10, 11 ns STRI COMMAND, RISC WRITE TIMING OSCIN low to STATE1 low t39a* OSCIN low to STATE1 high t39b* OSCIN high to OE high t39c* See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 13 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Unit Limits Min Max 01 0 46 02 0 37 01 0 50 02 0 40 01 0 49 02 0 37 01 0 65 02 0 49 01 --- 50 02 --- 38 01 --- 55 02 --- 41 01 --- 52 02 --- 39 01 0 39 02 0 33 01 0 42 02 0 33 01 0 46 02 0 35 01 0 52 02 0 39 01 0 49 02 0 37 01 0 47 02 0 35 01 0 65 02 0 49 STRI COMMAND, RISC WRITE TIMING – Continued OSCIN low to OE low OSCIN high to WE low OSCIN high to WE high t39d* 9, 10, 11 t39e* 9, 10, 11 t39f* OSCIN low to address valid t39g* OSCIN low to address high Z t39h OSCIN high to data valid t39i OSCIN low to data high Z See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 t39j ns LRI COMMAND, RISC READ TIMING OSCIN low to STATE1 low t40a* OSCIN low to STATE1 high t40b* OSCIN high to OE low t40c OSCIN low to OE high OSCIN high to WE high OSCIN low to WE low OSCIN low to address valid See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 t40d 9, 10, 11 t40e 9, 10, 11 t40f 9, 10, 11 t40g* 9, 10, 11 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 14 TABLE IA. Electrical performance characteristics – Continued. Test Symbol 1/ Test conditions 2/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A subgroups Device type Unit Limits Min Max 01 --- 50 02 --- 38 01 0 --- 02 0 --- 01 27 --- 02 20 --- 01 32 --- 02 24 --- 01 --- 50 02 --- 38 01 83 --- 02 62 --- 01 83 --- 02 62 --- LRI COMMAND, RISC READ TIMING – Continued OSCIN low to address high Z t40h Data setup time t40i Data hold time See figure 4 9, 10, 11 9, 10, 11 t40j 9, 10, 11 ns UART AND TIMER A/B TIMCLK TIMING TIMCLK low time TIMCLK high time t41a 9, 10, 11 See figure 4 t41b 9, 10, 11 ns MASTER RESET TIMING MRST pulse width t42a See figure 4 9, 10, 11 ns MASTER RESET TIMING WHEN TEST IS ACTIVE MRST timing with TEST active t42b See figure 4 9, 10, 11 ns 1/ Those test symbols marked with asterisks (*) will be guaranteed by test. 2/ Devices supplied to this drawing are characterized at all levels M, D, L, R, F, G. and H of irradiation. However, this device only tested at the 'H' level. Pre and Post irradiation values are identical unless otherwise specified in table IA. When post irradiation electrical measurements for any RHA level, TA = +25°C. 3/ Functional test shall be conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH (min) +20%, -0%; VIL = VIL (max) +0%, -50% as specified herein, for TTL or CMOS compatiable inputs. Devices may be tested using any input voltage within the above specified range, but shall be guaranteed to VIH (min) and VIL (max). 4/ Radiation hardened technology shall have a VIH pre-irradiation of 2.2 V. 5/ Double buffer output pins (i.e. DS , R/ WR , M/ IO , OP/ IN , AS ). 6/ Guaranteed to the limit specified in table IA, if not tested. 7/ Not more than one output may be shorted at a time for a maximum duration of one second. 8/ Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching. Voltage supply should be adequately sized and decoupled to handle a large current surge. 9/ All inputs with internal pull-ups or pull-downs should be left open circuit, all other inputs tied low or high. TEST input pin asserted. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 15 TABLE IB. SEP test limits. 1/ 2/ 3/ Device type All TA = Temperature ±10°C 4/ VDD = 4.5 V Effective LET no upsets [MeV/(mg/cm2)] Maximum device cross section (LET = 80) (cm2) = 55 6.7 x 10-5 +25°C > 80 1/ Devices that contain cross coupled resistance must be tested at the maximum rated TA. For SEP test conditions, see 4.4.4 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line. Test plan must be approved by TRB and qualifying activity. 3/ Values will be added when they become available. Rad hard devices have not yet been tested for SEP. 4/ Worst case temperature TA = +125°C. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 Bias for latch-up test VDD = 5.5 V no latch-up LET 4/ SIZE 5962-01502 A REVISION LEVEL SHEET 16 Device type Case outline Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol A1 NC B15 D12 F1 UARTIN K15 INT5 P2 RD15 A2 OP/IN C1 BUSY F2 MPAR L1 RD6 P3 NC A3 PS1 C2 NC F3 MPROT L2 NC P4 RA1 A4 PS0 C3 AS F13 D5 L3 RD10 P5 RA4 A5 AS3 C4 R/ WR F14 D4 L13 TIMCLK P6 RA7 A6 A15 C5 PS3 F15 D2 L14 PFAIL P7 RA8 A7 A14 C6 AS2 G1 UARTOUT L15 NC P8 RA12 A8 A13 C7 VDD G2 SYSFLT M1 RD7 P9 RA16/OD3 A9 A11 C8 VSS G3 NUO3 M2 RD9 P10 RA17/OD2 A10 A10 C9 A9 G13 VDD M3 RD13 P11 NC A11 NC C10 A6 G14 D3 M13 NC P12 NUI2 A12 A5 C11 A2 G15 D1 M14 SYSCLK P13 TEST A13 A3 C12 NC H1 RD0 M15 INT0 P14 OSCIN A14 A0 C13 D14 H2 NUI1 N1 RD8 P15 OSCOUT A15 NC C14 D11 H3 VDD N2 RD11 R1 NC B1 BGACK C15 D8 H13 VSS N3 RD14 R2 RA0 B2 DS D1 BTERR H14 IOLINT1 N4 NC R3 RA3 B3 M/ IO D2 BRQ H15 D0 N5 RA2 R4 RA5 B4 PS2 D3 NC J1 RD1 N6 RA6 R5 NC B5 NC D4 INDEX PIN J2 RD3 N7 RA9 R6 RA10 B6 AS1 D13 D13 J3 VSS N8 VSS R7 RA11 B7 AS0 D14 D9 J13 INT4 N9 VDD R8 RA13 B8 A12 D15 D7 J14 INT3 N10 RA18/OD1 R9 RA14 B9 A8 E1 NC J15 IOLINT0 N11 M1750 R10 RA15 B10 A7 E2 DTACK K1 RD2 N12 CONSOLE R11 RA19/CS B11 A4 E3 BGNT K2 RD4 N13 MME R12 OE B12 A1 E13 D10 K3 RD5 N14 NC R13 WE B13 NC E14 NC K13 INT1 N15 STATE1 R14 MRST B14 D15 E15 D6 K14 INT2 P1 RD12 R15 NC All X FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 17 Device type Case outline Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 VSS 28 RA10 55 PFAIL 82 D14 109 PS1 2 NC 29 RA11 56 INT0 83 D15 110 PS2 3 RD1 30 RA12 57 INT1 84 A0 111 PS3 4 RD2 31 RA13 58 INT2 85 A1 112 M/ IO 5 RD3 32 NC 59 INT3 86 A2 113 OP/IN 6 RD4 33 VSS 60 INT4 87 A3 114 R/ WR 7 RD5 34 VDD 61 INT5 88 A4 115 AS 8 RD6 35 NC 62 IOLINT0 89 A5 116 DS 9 RD7 36 RA14 63 IOLINT1 90 A6 117 BGACK 10 RD8 37 RA15 64 D0 91 A7 118 BRQ 11 RD9 38 RA16/OD3 65 NC 92 A8 119 BGNT 12 RD10 39 RA17/OD2 66 VSS 93 A9 120 BUSY 13 RD11 40 RA18/OD1 67 VDD 94 A10 121 DTACK 14 RD12 41 RA19/CS 68 NC 95 A11 122 BTERR 15 RD13 42 OE 69 D1 96 A12 123 MPROT 16 RD14 43 WE 70 D2 97 A13 124 MPAR 17 RD15 44 NUI2 71 D3 98 NC 125 SYSFLT 18 RA0 45 M1750 72 D4 99 VSS 126 NUO3 19 RA1 46 TEST 73 D5 100 VDD 127 UARTIN 20 RA2 47 MRST 74 D6 101 NC 128 UARTOUT 21 RA3 48 CONSOLE 75 D7 102 A14 129 NUI1 22 RA4 49 MME 76 D8 103 A15 130 RD0 23 RA5 50 OSCIN 77 D9 104 AS0 131 NC 24 RA6 51 OSCOUT 78 D10 105 AS1 132 VDD 25 RA7 52 SYSCLK 79 D11 106 AS2 26 RA8 53 TIMCLK 80 D12 107 AS3 27 RA9 54 STATE1 81 D13 108 PS0 All Y FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 18 FIGURE 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 19 FIGURE 4. Test circuit and timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 20 SYMBOL PARAMETER ta INPUT ↑ to response ↑ tb INPUT ↓ to response ↓ tc INPUT ↑ to response ↓ td INPUT ↓ to response ↑ te INPUT ↓ to data valid tf INPUT ↓ to high Z tg INPUT ↑ to high Z th INPUT ↑ to data valid FIGURE 4. Test circuit and timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 21 FIGURE 4. Test circuit and timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 22 FIGURE 4. Test circuit and timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 23 NOTES: 1. BGNT must be active and BUSY high at this clock edge or wait states will occur. 2. To avoid wait states, DTACK must be active here. FIGURE 4. Test circuit and timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 24 FIGURE 4. Test circuit and timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 25 Case outline Open VDD = 5 V ± 0.5 V C1, C7, D1, F1, F2, G13, H3, H14, J14, K13, K15, L14, N9, N12, P12, P13, P14 X A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, C2, C3, C4, C5, C6, C9, C10, C11, C12, C13, C14, C15, D2, D3, D4, D13, D14, D15, E1, E13, E14, E15, F13, F14, F15, G1, G3, G14, G15, H1, H2, H15, J1, J2, K1, K2, K3, L1, L2, L3, L15, M1, M2, M3, M13, M14, N1, N2, N3, N4, N5, N6, N7, N10, N14, N15, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P15, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R15 34, 44, 46, 48, 50, 55, 57, 59, 61, 63, 67, 100, 120, 122, 124, 127, 132 Y 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 41, 42, 43, 51, 52, 54, 64, 65, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 126, 128, 129, 130, 131 Ground C8, E2, E3, F3, G2, H13, J3, J13, J15, K14, L13, M15, N8, N11, N13, R14 1, 33, 45, 47, 49, 53, 56, 58, 60, 62, 66, 99, 119, 121, 123, 125 Each pin except C7, C8, G13, H3, H13, J3, N8, and N9 (for case outline X) and 1, 33, 34, 66, 67, 99, 100, and 132 (for case outline Y) will have a resistor of 2.49 kΩ ±5% for irradiation testing. FIGURE 5. Radiation exposure connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 26 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). c. Subgroup 4 (CIN, COUT, and CI/O measurements) shall be measured only for the initial test and after process or design changes which may affect input capacitance. A minimum sample of 5 devices with zero failures shall be required. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 27 TABLE IIA. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M Device class Q Device class V Interim electrical parameters (see 4.2) --- --- --- Final electrical parameters (see 4.2) 1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 3/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 7, 8 1, 2, 7, 8 1, 2, 7, 8 3/ Group D end-point electrical parameters (see 4.4) 1, 2, 7, 8 1, 2, 7, 8 1, 2, 7, 8 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Group A test requirements (see 4.4) 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 3/ Delta limits, as specified in table IIB herein, shall be required when specified and the delta values shall be completed with reference to the zero hour electrical parameter. TABLE IIB. Burn-in delta parameters (+25°C). Parameter Symbol Condition Quiescent current QIDD TA = 25°C Limits ±10% of measured value or 35 µA whichever is greater NOTE: If device is tested at or below 35 µA, no deltas are required. Deltas are performed at room temperture. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A and as specified herein. 4.4.4.1.1 Accelarated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accoradance with test method 1020 of MIL-STD-883 and as specified herein (see 1.5). Tests shall be performed on devices, SEC, or approved test structures at technology qualification and after any design or process changes which may affect the RHA capability of the process. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 28 4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accoradance with test method 1021 of MIL-STD883 and herein (see 1.5). a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified. b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved radiation hardness assurance plan and MIL-PRF-38535. 4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (See 1.5). SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehice as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upse or latchup characteristics. The recommended test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed. b. The fluence shall be≥ 100 errors or ≥ 106 ions/cm2. c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be ≥ 20 microns in silicon. e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. h. For SEP test limits, see table IB herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 29 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as shown in table III herein. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Additional information. A copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of transients (SEP). e. Occurrence of latchup (SEP). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL A SHEET 30 TABLE III. Pin Descriptions. Pin Name Active 1/ Type 2/ Description OSCILLATOR AND CLOCK SIGNALS OSCIN --- OSC Oscillator Input. A 50% duty cycle crystal-drive input for driving the device. OSCOUT --- CO Oscillator Output. A 50% duty cycle, single-phase clock output at the same frequency as the OSCIN input. SYSCLK --- TO System Output. The buffered equivalent of the OSCOUT signal. Not used input 1. Tie either high or low. PROCESSOR STATUS NUI1 --- TI NUI2 --- TUI Not used input 2. Tie low. M1750 AH TDI Mode Select RISC/1750. A high on M1750 places the UT1750AR into the MIL-STD-1750A emulation mode. A low on M1750 places the UT1750AR into the RISC mode. It is tied to an internal pull-down resistor. NUO3 --- TTO Not used output 3. NUO3 enter high impedance state when the device is in the test mode ( TEST = 0). --- STATE1 TTO Processor State. This signal indicates the internal state of the device. A low on STATE1 indicates the device is executing a new instruction. A high on STATE1 indicates the device is fetching an instruction. STATE1 enters a high impedance state when the device is in the test mode ( TEST = 0). OPERAND DATA BUS ARBITRATION AL BRQ TTO Bus Request. The device asserts this signal to indicate it is requesting control of the Operand data bus (D0-D15). BRQ enters a high-impedance state when the device is in the test mode ( TEST = 0). BGNT AL TUI Bus Grant. When asserted, this signal indicates the device may take control of the Operand data bus. It is tied to an internal pull-up resistor. BUSY AL TUI Bus Busy. A bus master asserts this input to inform the device that another bus master is using the Operand data bus. It is tied to an internal pull-up resistor. BGACK AL TTO Bus Grant Acknowledge Output. The device asserts this signal to indicate it is the current bus master. When low, BGACK inhibits other devices from becoming the bus master. When the device relinquishes control of the bus, BGACK enters a high-impedance state. See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 31 TABLE III. Pin Descriptions - Continued. Pin Name Active 1/ Type 2/ Description OPERAND DATA BUS CONTROL AL DTACK TUI Data Transfer Acknowledge. This signal tells the device that a data transfer has been acknowledged and the device can complete the bus cycle. To assure the device operates with no wait states, DTACK can be tied low. DTACK is tied to an internal pull-up resistor. Operand/Instruction. This indicates whether the UT1750AR’s current bus cycle is for Data (high) or Instruction (low) acquisition. OP/IN remains in a high state whenever a bus cycle (Memory or I/O) is not an instruction fetch. Address Strobe. Indicates a valid address on the Operand Address bus. UT1750AR places AS in a high-impedance state when it does not control the Operand busses. OP/IN --- TTO AS AL TTO M/ IO --- TTO Memory or I/O . Indicates whether the current bus cycle is for memory (high) or TTO I/O (low). It remains in the high-impedance state during bus cycles when the device does not control the Operand buses. Read /Write. Indicates the direction of data flow with respect to the device. --- R/ RW R/ RW high means the device is attempting to read data from an external device, and R/ RW low means the device is attempting to write data to an external device. AL DS TTO R/ RW remains in a high-impedance state when the device does not control the Operand buses. Data Strobe. Indicates valid data is on the Operand Data bus. The device places DS in a high-impedance state when it does not control the Operand buses. RISC MEMORY CONTROL AL OE TTO Output Enable Instruction Memory. This signal allows memory to place data on the instruction data bus. The Store Register to Instruction Memory (STRI) instruction removes OE during the CK2 internal clock cycle. OE enters a high- AL WE TTO impedance state when the device is in test mode ( TEST = 0). Write Enable Memory. This signal allows the device to write to instruction memory. The Store Register to Instruction Memory (STRI) instruction assets WE during the CK2 internal clock cycle. WE enters a high-impedance state when the device is in the test mode ( TEST = 0). UART CONTROL/TIMER CLOCK UARTIN AH TUI UARTOUT AH TTO MME AH TDI TIMCLK --- TI UART Input. The device receives serial data through tihis input. The serial data is stored in the device's Receiver Buffer Register (RCVR). It is tied to an internal pull-up resistor. UART Output. The serial data stored in the device's Transmitter Buffer Register (TXMT) is transmitted through this output. The UART output is fixed at 9600 baud, with eight data bits, odd-parity, and one stop bit. UARTOUT enters a high-impedance state when the device is in the test mode ( TEST = 0). (9600 baud @ TIMCLK = 12 MHz). Memory Management Enable. This signal indicates to the UT1750AR that a Memory Management Unit (MMU) is present and that the memory management option is enabled. MME is tied to an internal pull-down resistor. Timer Clock. This 12 MHz clock input generates the baud rate for the device's internal UART. The input also provides the clock for the device's two internal timers (TIMER A and TIMER B). See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 32 TABLE III. Pin Descriptions - Continued. Pin Name Active 1/ Type 2/ Description UART CONTROL/TIMER CLOCK – Continued Test (Input). Asserting this input places the device into a test mode. In this mode, AL TUI TEST all the device's outputs, except OSCOUT and SYSCLK, enter a high-impedance state. When using TEST , the device must have a MRST . MRST must be held active for at least one SYSCLK period after TEST is deasserted to assure proper CONSOLE AH TDI operation. TEST is tied to an internal pull-up resistor. Console (Command). Asserting this input sets bit 3 in the System Status Register. Bit 3 is read with the Input Register Instruction (INR). When UT1750AR is operating in the MIL-STD-1750 mode, asserting CONSOLE during a Master Reset invokes the maintenance console option. Tied to an internal pull-down resistor. PROCESSOR MODE AS0 AS1 AS2 AS3 AH TTO PS0 PS1 PS2 PS3 AH TTO Address State. These outputs indicate the current address state of the UT1750AR. Using these outputs with a Memory Management Unit (MMU) allows selecting the MMU’s page register group. These outputs enter a high impedance state when the UT1750AR is placed in the test mode (TEST = 0) or during bus cycles not assigned to this processor. Processor State. These outputs indicate the current state of the processor. These outputs enter a high-impedance state when the UT1750AR is in the test mode (TEST = 0) or during bus cycles not assigned to this processor. INTERRUPTS/EXCEPTIONS SYSFLT AH TUI System Fault. This positive edge-triggered input sets bit 8 (MCHNE1) in the device's Fault Register. Under no circumstances should MCHNE1 be tied in its active state. It is tied to an internal pull-up resistor. Interrupt is not cleared via software until the negation of the input signal. BTERR AL TUI Bus Time Error. It is asserted when a bus error or a timeout occurs. During I/O bus cycles, an active BTERR sets bit 10 of the Fault Register. During Memory bus cycles, an active BTERR sets bit 7 of the Fault Register. Under no circumstances should BTERR be tied in its active state. It is tied to an internal pull-up resistor. Interrupt is not cleared via software until the negation of the input signal MPAR AH TDI Memory Parity (Error). Asserting this input indicates a machine error. Bit 13 of the device's Fault Register is set when MCHNE2 is active. Under no circumstances should MCHNE2 be tied in its active state. It is tied to an internal pull-down resistor. Interrupt is not cleared via software until the negation of the input signal. MPROT AH TUI Memory Protect Fault. When asserted, it informs the device that a memoryprotect fault has occurred on the Operand Data Bus. An access fault, a writeprotect fault, or an execute-protect fault causes a memory-protect fault. If the device is using the bus and MPROT is asserted, bit 15 of the Fault Register (CPU Fault) is set. If the device is not using the bus and MPROT is asserted, bit 14 of the Fault Register (DMA Error) is set. It is tied to an internal pull-up resistor. Interrupt is not cleared via software until the negation of the input signal. See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 33 TABLE III. Pin Descriptions - Continued. Pin Name Active 1/ Type 2/ Description INTERRUPTS/EXCEPTIONS – Continued AL INT0 - TUI INT5 User Interrupts. These interrupts are active on a negative-going edge and each will set, when active, its associated bit in the Pending Interrupt Register. The interrupts are maskable by setting the associated bits in the Interrupt Mask Register. Asserting MRST resets all interrupts. They are tied to an internal pull-up resistor. I/O Level Interrupts. These inputs are active on a negative going edge and each sets, when active, its associated bit in the Pending Interrupt Register. The interrupts are maskable by setting the associated bits in the Interrupt Mask Register. Asserting MRST resets all interrupts. They are tied to an internal pull-up resistor. --- TUI PFAIL AL TUI Power Fail (Interrupt). Asserting this input informs the device that a powere failure has occured and the present process will be interrupted. This input sets bit 15 in the Pending Interrupt Register. A Power Fail Interrupt (bit 15) cannot be disabled or masked. It is tied to an internal pull-up resistor. MRST AL TUI Master Reset. This input initializes the device to a reset state. The device must be reset after power (VCC) is within specification and stable to ensure proper IOLINT0 IOLINT1 operation. The system must hold MRST active for at least one period of SYSCLK to assure the device will be reset. It is tied to an internal pull-up resistor. OPERAND BUSES A0 – A15 --- TTO Address Bus-Operand. When asserted, this bus is unidirectional and represents the Operand Address. The bus is in the high-impedance state when the device does not control the bus. A15 is the most significant bit. The Operand Address enters a high-impedance state when the device is in the test mode ( TEST = 0). D0 - D15 --- TTB Data Bus-Operand. This bidirectional data bus remains in a high-impedance state when the device does not control the bus. D15 is the most significant bit. The Operand Data Bus enters a high-impedance state when the device is in the test mode ( TEST = 0). RISC BUSES RA0 - RA15 --- TTO Instruction Address Bus. This unidirectional bus represents the address of the data in instruction memory. RA19 is the most significant bit. The address enters a high-impedance state only ehen the device is in the test mode ( TEST = 0). RA16/OD3 RA17/OD2 RA18/OD1 RA19/CS AH TTO RISC Instruction Address Bus/Output Discretes. When the UT1750AR is operating in the RISC mode (M1750 = 0) these four bits represent the four most significant address bits. In the MIL-STD-1750A mode (M1750 = 1) these four bits are user programmable output discretes defined as follows: RA19/CS = Chip Select (AL) RA18/OD1 = Output Discrete 1 RA17/OD2 = Output Discrete 2 RA16/OD3 = Output Discrete 3 These output discretes are programmed with the Output Register (OTR) RISC opcode. These signals enter a high-impedance state when the UT1750AR is in the test mode (TEST = 0). See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 34 RISC BUSES – Continued RD0 - RD15 --- TTB Instruction Data Bus. This bidirectional data bus is the interface with the memory. RD15 is the most significant bit. The Data Bus enters a high-impedance state only when the device is in the test mode ( TEST = 0). POWER AND GROUND VDD --- --- +5 V DC Power. Power supply input. VSS --- --- Reference Ground. Zero Volts DC, logic ground. 1/ AH = Active High; AL = Active Low. 2/ TO = TTL output; TI = TTL input; TUI = TTL input (pull-up); TDI = TTL input (pull-down); TTO = Three-state TTL output; TTB = Three-state TTL bidirectional; CO = CMOS output; OSC = Oscillator input to a Pierce Oscillator inverter. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-01502 A REVISION LEVEL SHEET 35 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 01-03-28 Approved sources of supply for SMD 5962-01502 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and/or QML-38535 during the next revision. MIL-HDBK-103 and/or QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and/or QML-38535. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-0150201QXA 65342 UT1750AR12GCA 5962-0150201QXC 65342 UT1750AR12GCC 5962-0150201QYC 65342 UT1750AR12WCC 5962H0150201QXA 65342 UT1750AR12GCAH 5962H0150201QXC 65342 UT1750AR12GCCH 5962H0150201QYC 65342 UT1750AR12WCCH 5962H0150201VXA 65342 UT1750AR12GCAH 5962H0150201VXC 65342 UT1750AR12GCCH 5962H0150201VYC 65342 UT1750AR12WCCH 5962-0150202QXA 65342 UT1750AR16GCA 5962-0150202QXC 65342 UT1750AR16GCC 5962-0150202QYC 65342 UT1750AR16WCC 5962H0150202QXA 65342 UT1750AR16GCAH 5962H0150202QXC 65342 UT1750AR16GCCH See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962H0150202QYC 65342 UT1750AR16WCCH 5962H0150202VXA 65342 UT1750AR16GCAH 5962H0150202VXC 65342 UT1750AR16GCCH 5962H0150202VYC 65342 UT1750AR16WCCH 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 65342 Vendor name and address UTMC Microelectronic Systems Inc. 4350 Centennial Boulevard Colorado Springs, CO 80907-3486 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.