ETC ADSP

PRELIMINARY TECHNICAL DATA
a
ADSP-21535
Preliminary Technical Data
SUMMARY
300 MHz High-Performance Blackfin DSP Core
Two 16-Bit MACs, Two 40-Bit ALUs, Two 40-Bit
Accumulators, Four 8-Bit Video ALUs, and a 40-Bit
Shifter
RISC-Like Register and Instruction Model for Ease of
Programming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.9–1.5 V Core VDD with Dynamic Power Management
3.3 V I/O
0ºC To +85ºC Case Commercial Temperature Range
-40ºC To +105ºC Case Industrial Temperature Range (200
MHz)
260-Lead PBGA Package
MEMORY
4G-Byte Unified Address Range
308K Bytes of On-Chip Memory:
16K Bytes of Instruction SRAM/Cache
32K Bytes of Data SRAM/Cache
4K Bytes of Scratchpad SRAM
256K Bytes of Full Speed, Low Latency SRAM
Memory DMA Controller
Memory Mgmt Unit Providing Memory Protection
Glueless External Memory Controllers
Synchronous SDRAM Support
Asynchronous with SRAM, Flash, ROM Support
PERIPHERALS
32-Bit, 33-MHz, 3.3 V, PCI 2.2-compliant Bus Interface
with Master and Slave Support
Integrated USB 1.1-compliant Device Interface
Two UARTs, One with IrDA®
Two SPI-compatible Ports
Two Full-Duplex Synchronous Serial Ports (SPORTs)
FUNCTIONAL BLOCK DIAGRAM
JTAG TEST AND
EMULATION
INTERRUPT
CONTROLLER/
TIMER
WATCHDOG TIMER
32
BLACKFIN
CORE
REAL TIME CLOCK
256K BYTES SRAM
UART PORT 0
IrDA ®
UART PORT 1
64
SYSTEM BUS
INTERFACE UNIT
TIMER0, TIMER1,
TIMER2
32
PROGRAMMABLE
FLAGS
32
USB INTERFACE
DMA
CONTROLLER
SERIAL PORTS
(2)
SPI PORTS
(2)
BOOT ROM
32
PCI BUS INTERFACE
32
EXTERNAL PORT
FLASH
SDRAM CONTROL
REV. PrC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise agreed to in
writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2002
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
Four Timer/Counters, Three with PWM Support
Sixteen Bi-Directional Programmable Flag I/O Pins
Watchdog Timer
Real-Time Clock
On-Chip PLL with 1x To 31x Frequency Multiplier
General Note
This data sheet provides preliminary information for the
ADSP-21535 Blackfin DSP.
GENERAL DESCRIPTION
The ADSP-21535 is a member of the Blackfin DSP family
of products, incorporating the Micro Signal Architecture
(MSA), jointly developed by Analog Devices, Inc. and Intel
Corporation. The architecture combines a dual-MAC
state-of-the-art DSP engine, the advantages of a clean,
orthogonal RISC-like microprocessor instruction set, and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.
By integrating a rich set of industry leading system peripherals and memory, Blackfin DSPs are the platform of choice
for next generation applications that require RISC like programmability, multimedia support and leading edge signal
processing in one integrated DSP.
Portable Low-Power Architecture
Blackfin DSPs provide world class power dissipation and
performance compared to other Digital Signal Processors.
Blackfin DSPs are designed in a Low-Power and Low-Voltage Design Methodology and feature Dynamic Power
Management, the ability to vary both the voltage and
frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result
in a three-fold reduction in power consumption, by comparison to just varying the frequency of operation. This
translates into longer battery life for portable appliances.
System Integration
The ADSP-21535 is a highly integrated system-on-a-chip
solution for the next generation of digital communication
and portable Internet appliances. By combining industry-standard interfaces with a high performance Digital
Signal Processing core, users can develop cost effective
solutions quickly without the need for costly external components. The ADSP-21535 system peripherals include
UARTs, SPIs, SPORTs, General Purpose Timers, a
Real-Time Clock, Programmable Flags, Watchdog Timer,
and USB and PCI buses for glueless peripheral expansion.
ADSP-21535 Peripherals
The ADSP-21535 contains a rich set of peripherals
connected to the core via several high bandwidth buses,
providing flexibility in system configuration as well as
excellent overall system performance. See Functional Block
Diagram on page 1. The base peripherals include general
purpose functions such as UARTs, Timers with PWM
(Pulse Width Modulator) and pulse measurement capability, general purpose flag I/O pins, a Real-Time Clock, and
2
June 2002
a Watchdog Timer. This set of functions satisfies a wide
variety of typical system support needs and is augmented by
the system expansion capabilities of the part. In addition to
these general-purpose peripherals, the ADSP-21535
contains high speed serial ports for interfaces to a variety of
audio and modem CODEC functions. It also contains an
event handler for flexible management of interrupts from
the on-chip peripherals and external sources and power
management control functions to tailor the performance
and power characteristics of the processor and system to
many application scenarios.
The on-chip peripherals can be easily augmented in many
system designs with little or no glue logic due to the
inclusion of several interfaces providing expansion on industry-standard buses. These include a 32-bit, 33-MHz,
V2.2-compliant PCI bus, SPI serial expansion ports and a
device type USB port. These enable the connection of a
large variety of peripheral devices to tailor the system design
to specific applications with a minimum of design
complexity.
All of the peripherals, except for programmable flags,
Real-Time Clock, and timers, are supported by a flexible
DMA structure with individual DMA channels integrated
into the peripherals. There is also a separate memory DMA
channel dedicated to data transfers between the DSP's
various memory spaces including external SDRAM and
asynchronous memory, internal Level 1 and Level 2 SRAM
and PCI memory spaces. Multiple on-chip 32-bit buses
running at up to 133 MHz provide adequate bandwidth to
keep the processor core running along with activity on all of
the on-chip and external peripherals.
Blackfin DSP Core
As shown in Figure 1, the Blackfin DSP core contains two
multiplier/accumulators (MACs), two 40-bit ALUs, four
video ALUs, and a single shifter. The computational units
process 8-bit, 16-bit, or 32-bit data from the register file.
Each MAC performs a 16-bit by 16-bit multiply in every
cycle, with an accumulation to a 40-bit result, providing
8 bits of extended precision.
The ALUs perform a standard set of arithmetic and logical
operations. With two ALUs capable of operating on 16- or
32-bit data, the flexibility of the computation units covers
the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be
regarded as two 16-bit halves, so each ALU can accomplish
very flexible single 16-bit arithmetic operations. By viewing
the registers as pairs of 16-bit operands, dual 16-bit or single
32-bit operations can be accomplished in a single cycle. By
further taking advantage of the second ALU, quad 16-bit
operations can be accomplished simply, accelerating the per
cycle throughput.
The powerful 40-bit shifter has extensive capabilities for
performing shifting, rotating, normalization, extraction,
and depositing of data.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
June 2002
ADSP-21535
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
I3
L3
B3
M3
I2
L2
B2
M2
I1
I0
L1
L0
B1
B0
M1
M0
DAG0
DAG1
SEQUENCER
P1
P0
ALIGN
DECODE
R7
R6
R5
R4
R3
R2
R1
R0
LOOP BUFFER
16
16
8
8
BARREL
SHIFTER
40
A0
8
8
CONTROL
UNIT
40
A1
DATA ARITHMETIC UNIT
Figure 1. Blackfin DSP Core
The data for the computational units is found in a
multi-ported register file of sixteen 16-bit entries or eight
32-bit entries.
A powerful program sequencer controls the flow of instruction execution, including instruction alignment and
decoding. The sequencer supports conditional jumps and
subroutine calls, as well as zero-overhead looping. A loop
buffer stores instructions locally, eliminating instruction
memory accesses for tight looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The
DAGs share a register file containing four sets of 32-bit
Index, Modify, Length, and Base registers. Eight additional
32-bit registers provide pointers for general indexing of
variables and stack locations.
Blackfin DSPs support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1
(L1) memories are those that typically operate at the full
processor speed with little or no latency. Level 2 (L2)
memories are other memories, on-chip or off-chip, that may
take multiple processor cycles to access. At the L1 level, the
instruction memory holds instructions only. The two data
memories hold data, and a dedicated scratchpad data
memory stores stack and local variable information. At the
L2 level, there is a single unified memory space, holding
both instructions and data.
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In addition, the L1 instruction memory and L1 data
memories may be configured as either Static RAMs
(SRAMs) or caches. The Memory Management Unit
(MMU) provides memory protection for individual tasks
that may be operating on the core and may protect system
registers from unintended access.
The architecture provides three modes of operation: user
mode, supervisor mode, and emulation mode. User mode
has restricted access to certain system resources, thus
providing a protected software environment, while supervisor mode has unrestricted access to the system and core
resources.
The Blackfin DSP instruction set has been optimized so that
16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin
DSPs support a limited multi-issue capability, where a
32-bit instruction can be issued in parallel with two 16-bit
instructions, allowing the programmer to use many of the
core resources in a single instruction cycle.
The Blackfin DSP assembly language uses an algebraic
syntax for ease of coding and readability. The architecture
has been optimized for use in conjunction with the C-compiler, resulting in fast and efficient software
implementations.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
June 2002
Memory Architecture
The L1 memory system is the primary highest-performance
memory available to the Blackfin DSP core. The L2
memory provides additional capacity with slightly lower
performance. Lastly, the off-chip memory system, accessed
through the External Bus Interface Unit (EBIU), provides
expansion with SDRAM, flash memory, and SRAM,
optionally accessing more than 768M bytes of physical
memory.
The memory DMA controller provides high-bandwidth
data-movement capability. It can perform block transfers of
code or data between the internal L1/L2 memories and the
external memory spaces (including PCI memory space).
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
RESERVED
0xFFA0 4000
INSTRUCTION SRAM (16K BYTE)
0xFFA0 0000
RESERVED
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
0xFF90 0000
RESERVED
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
0xFF80 0000
INTERNAL MEM ORY MAP
The ADSP-21535 views memory as a single unified
4G-byte address space, using 32-bit addresses. All resources
including internal memory, external memory, PCI address
spaces, and I/O control registers occupy separate sections
of this common address space. The memory portions of this
address space are arranged in a hierarchical structure to
provide a good cost/performance balance of some very fast,
low-latency memory as cache or SRAM very close to the
processor, and larger, lower-cost and performance-memory
systems farther away from the processor. See Figure 2.
RESERVED
0xF003 FFFF
L2 SRAM MEMORY (256K BYTE)
0xF000 0000
RESERVED
0xEF00 0000
PCI CONFIG SPACE PORT (4 BYTE)
0xEEFF FFFC
PCI CONFIG REGISTERS (64K BYTE)
0xEEFF FF00
RESERVED
0xEEFE FFFF
The ADSP-21535 has four blocks of on-chip memory
providing high-bandwidth access to the core.
The first is the L1 instruction memory consisting of
16K bytes of 4-way set-associative cache memory. In
addition the memory may be configured as an SRAM. This
memory is accessed at full processor speed.
PCI IO SPACE (64K BYTE)
0xEEFE 0000
RESERVED
0xE7FF FFFF
PCI MEMORY SPACE (128M BYTE)
0xE000 0000
RESERVED
0x2FFF FFFF
ASYNC MEMORY BANK 3 (64M BYTE)
0x2C00 0000
ASYNC MEMORY BANK 2 (64M BYTE)
The second on-chip memory block is the L1 data memory,
consisting of two banks of 16K bytes each. Each L1 data
memory bank can be configured as one way of a two-way
set associative cache or as an SRAM, and is accessed at full
speed by the core.
0x2800 0000
The third memory block is a 4K-byte scratchpad RAM
which runs at the same speed as the L1 memories, but is
only accessible as data SRAM (it cannot be configured as
cache memory and is not accessible via DMA).
0x1000 0000
The fourth on-chip memory system is the L2 SRAM
memory array which provides 256K bytes of high speed
SRAM at the full bandwidth of the core, and slightly longer
latency than the L1 memory banks. The L2 memory is a
unified instruction and data memory and can hold any
mixture of code and data required by the system design.
The Blackfin DSP core has a dedicated low-latency 64-bit
wide datapath port into the L2 SRAM memory. For
example, at a core frequency of 300 MHz, the peak data
transfer rate across this interface is up to 2.4G bytes per
second.
4
ASYNC MEMORY BANK 1 (64M BYTE)
0x2400 0000
ASYNC MEMORY BANK 0 (64M BYTE)
0x2000 0000
0x1800 0000
0x0800 0000
0x0000 0000
EXT ERNAL M EMO RY M AP
Internal (On-chip) Memory
SDRAM MEMORY BANK 3
(16M BYTE - 128M BYTE) *
SDRAM MEMORY BANK 2
(16M BYTE - 128M BYTE) *
SDRAM MEMORY BANK 1
(16M BYTE - 128M BYTE) *
SDRAM MEMORY BANK 0
(16M BYTE - 128M BYTE) *
* THE ADDRESSES SHOWN FOR THE SDRAM BANKS REFLECT
A FULLY POPULATED SDRAM ARRAY WITH 512M BYTES OF
MEMORY. IF ANY BANK CONTAINS LESS THAN 128M BYTES OF
MEMORY, THAT BANK WOULD EXTEND ONLY TO THE LENGTH
OF THE REAL MEMORY SYSTEMS, AND THE END ADDRESS
WOULD BECOME THE START ADDRESS OF THE NEXT BANK.
THIS WOULD CONTINUE FOR ALL FOUR BANKS, WITH ANY
REMAINING SPACE BETWEEN THE END OF MEMORY BANK 3
AND THE BEGINNING OF ASYNC MEMORY BANK 0, AT
ADDRESS 0x2000 0000, TREATED AS RESERVED ADDRESS
SPACE.
Figure 2. Internal/External Memory Map
External (Off-Chip) Memory
External memory is accessed via the External Bus Interface
Unit (EBIU). This interface provides a glueless connection
to up to four banks of synchronous DRAM (SDRAM) as
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
For current information contact Analog Devices at 800-262-5643
well as up to four banks of asynchronous memory devices
including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed to interface to up to four banks of SDRAM, with
each bank containing between 16M bytes and 128M bytes
providing access to up to 512M bytes of SDRAM. Each
bank is independently programmable and is contiguous
with adjacent banks regardless of the sizes of the different
banks or their placement. This allows flexible configuration
and upgradability of system memory while allowing the core
to view all SDRAM as a single, contiguous, physical address
space.
The asynchronous memory controller can also be programmed to control up to four banks of devices with very
flexible timing parameters for a wide variety of devices. Each
bank occupies a 64M-byte segment regardless of the size of
the devices used so that these banks will only be contiguous
if fully populated with 64M bytes of memory.
PCI
The PCI bus defines three separate address spaces, which
are accessed through windows in the ADSP-21535 memory
space. These are PCI memory, PCI I/O, and PCI configuration space.
In addition, the PCI interface can either be used as a bridge
from the processor core as the controlling CPU in the
system, or as a host port where another CPU in the system
is the host and the ADSP-21535 is functioning as an intelligent I/O device on the PCI bus.
When the ADSP-21535 acts as the system controller, it
views the PCI address spaces through its mapped windows
and can initialize all devices in the system and maintain a
map of the topology of the environment.
The PCI memory region is a 4G-byte space that appears on
the PCI bus and can be used to map memory I/O devices
on the bus. The ADSP-21535 uses a 128M-byte window in
memory space to see a portion of the PCI memory space.
A base address register is provided to position this window
anywhere in the 4G-byte PCI memory space while its
position with respect to the processor addresses remains
fixed.
The PCI I/O region is also a 4G-byte space. However, most
systems and I/O devices only use a 64K-byte subset of this
space for I/O mapped addresses. The ADSP-21535 implements a 64K-byte window into this space along with a base
address register which can be used to position it anywhere
in the PCI I/O address space, while the window remains at
the same address in the processor's address space.
ADSP-21535
address in PCI configuration space. This window is fixed
and receives the address of the value, and the value if the
operation is a write. Otherwise the device returns the value
into the same address on a read operation.
I/O Memory Space
Blackfin DSPs do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped
into memory-mapped registers (MMRs) at addresses near
the top of the 4G-byte address space. These are separated
into two smaller blocks, one which contains the control
MMRs for all core functions, and the other which contains
the registers needed for setup and control of the on-chip
peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and
appear as reserved space by on-chip peripherals, as as well
as external devices accessing resources through the PCI bus.
The system MMRs are accessible by the core in supervisor
mode and can be mapped as either visible or reserved to
other devices, depending on the system protection model
desired.
Booting
The ADSP-21535 contains a small boot kernel, which configures the appropriate peripheral for booting. If the
ADSP-21535 is configured to boot from boot ROM
memory space, the DSP starts executing from the on-chip
boot ROM. For more information, see Booting Modes on
page 14.
Event Handling
The event controller on the ADSP-21535 handles all asynchronous and synchronous events to the processor. The
ADSP-21535 provides event handling that supports both
nesting and prioritization. Nesting allows multiple event
service routines to be active simultaneously. Prioritization
ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The
controller provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut
down of the system.
PCI configuration space is a limited address space, which is
used for system enumeration and initialization and which is
a very low-performance communication mode between the
processor and PCI devices. The ADSP-21535 provides a
one-value window to access a single data value at any
REV. PrC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
• Exceptions – Exceptions are events that occur synchronously to program flow, i.e., the exception will be taken
before the instruction is allowed to complete. Conditions
such as data alignment violations, undefined instructions,
etc. cause exceptions.
• Interrupts – Interrupts are events that occur asynchronously to program flow. They are caused by timers,
peripherals, input pins, etc.
Each event has an associated register to hold the return
address and an associated return-from-event instruction.
When an event is triggered, the state of the processor is saved
on the supervisor stack.
The ADSP-21535 event controller consists of two stages,
the Core Event Controller (CEC) and the System Interrupt
Controller (SIC). The Core Event Controller works with
the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the
general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts
(IVG15–7), in addition to the dedicated interrupt and
exception events. Of these general-purpose interrupts, the
two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers,
leaving seven prioritized interrupt inputs to support the
peripherals of the ADSP-21535. Table 1 describes the
inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.
Table 1. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
EVT Entry
Emulation/Test
Reset
Non-Maskable
Exceptions
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
June 2002
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt
sources, to the prioritized general-purpose interrupt inputs
of the CEC. Although the ADSP-21535 provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the
Interrupt Assignment Registers (IAR). Table 2 describes
the inputs into the SIC and the default mappings into the
CEC.
Table 2. System Interrupt Controller (SIC)
Peripheral Interrupt
Event
Peripheral
Interrupt ID
Default
Mapping
Real-Time Clock
Reserved
USB
PCI Interrupt
SPORT 0 Rx DMA
SPORT 0 Tx DMA
SPORT 1 Rx DMA
SPORT 1 Tx DMA
SPI 0 DMA
SPI 1 DMA
UART 0 Rx
UART 0 Tx
UART 1 Rx
UART 1 Tx
Timer 0
Timer 1
Timer 2
GPIO Interrupt A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
26–21
27
28
IVG7
IVG7
IVG7
IVG8
IVG8
IVG8
IVG8
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
IVG13
IVG14
IVG15
GPIO Interrupt B
Memory DMA
Software Watchdog Timer
Reserved
Software Interrupt 1
Software Interrupt 2
Event Control
The ADSP-21535 provides the user with a very flexible
mechanism to control the processing of events. In the CEC,
three registers are used to coordinate and control events.
Each of the registers,as follows, is 16-bits wide, while each
bit represents a particular event class:
• CEC Interrupt Latch Register (ILAT) – The ILAT
register indicates when events have been latched. The
appropriate bit is set when the processor has latched the
event and cleared when the event has been accepted into
the system. This register is updated automatically by the
controller but may be read while in supervisor mode.
• CEC Interrupt Mask Register (IMASK) – The IMASK
register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event
6
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
For current information contact Analog Devices at 800-262-5643
is unmasked and will be processed by the system when
asserted. A cleared bit in the IMASK register masks the
event thereby preventing the processor from servicing the
event even though the event may be latched in the ILAT
register. This register may be read from or written to while
in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI
and CLI instructions, respectively.)
• CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically by the controller but may be read while in supervisor
mode.
The SIC allows further control of event processing by
providing three 32-bit interrupt control and status registers.
Each register contains a bit corresponding to each of the
peripheral interrupt events shown in Table 2.
• SIC Interrupt Mask Register (SIC_IMASK) – This
register controls the masking and unmasking of each
peripheral interrupt event. When a bit is set in the register,
that peripheral event is unmasked and will be processed
by the system when asserted. A cleared bit in the register
masks the peripheral event thereby preventing the
processor from servicing the event.
• SIC Interrupt Status Register (SIC_ISTAT) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, a cleared bit indicates
the peripheral is not asserting the event.
• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
enabling the corresponding bit in this register, each
peripheral can be configured to wake up the processor,
should the processor be in a powered down mode when
the event is generated. (For more information, see
Dynamic Power Management on page 11.)
Because multiple interrupt sources can map to a single general-purpose interrupt, multiple pulse assertions can occur
simultaneously, before or during interrupt processing for an
interrupt event already detected on this interrupt input. The
IPEND register contents are monitored by the SIC as the
interrupt acknowledgement.
The appropriate ILAT register bit is set when an interrupt
rising edge is detected (detection requires two processor
clock cycles). The bit is cleared when the respective IPEND
register bit is set. The IPEND bit indicates that the event
has entered into the processor pipeline. At this point the
CEC will recognize and queue the next rising edge event on
the corresponding event input. The minimum latency from
the rising edge transition of the general-purpose interrupt
to the IPEND output asserted is three processor clock
cycles; however, the latency can be much higher, depending
on the activity within and the mode of the processor.
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ADSP-21535
DMA CONTROLLERS
The ADSP-21535 has multiple, independent DMA controllers that support automated data transfers with minimal
overhead for the DSP core. DMA transfers can occur
between the ADSP-21535's internal memories and any of
its DMA-capable peripherals. Additionally, DMA transfers
can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller, the
asynchronous memory controller and the PCI bus interface.
DMA-capable peripherals include the SPORTs, SPI ports,
UARTs, and USB port. Each individual DMA-capable
peripheral has at least one dedicated DMA channel. DMA
to and from PCI is accomplished by the memory DMA
channel.
To describe each DMA sequence, the DMA controller uses
a set of parameters, called a descriptor block. When successive DMA sequences are needed, these descriptor blocks
can be linked or chained together, so the completion of one
DMA sequence auto-initiates and starts the next sequence.
The descriptor blocks include full 32-bit addresses for the
base pointers for source and destination enabling access to
the entire ADSP-21535 address space.
In addition to the dedicated peripheral DMA channels,
there is a separate memory DMA channel provided for
transfers between the various memories of the ADSP21535 system. This enables transfers of blocks of data
between any of the memories including on-chip Level 2
memory, external SDRAM, ROM, SRAM and flash
memory, and PCI address spaces with little processor
intervention.
EXTERNAL MEMORY CONTROL
The External Bus Interface Unit (EBIU) on the
ADSP-21535 provides a high performance, glueless
interface to a wide variety of industry-standard memory
devices. The controller is made up of two sections: the first
is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs, while the
second is an asynchronous memory controller intended to
interface to a variety of memory devices.
PC133 SDRAM Controller
The SDRAM controller provides an interface to up to four
separate banks of industry-standard SDRAM devices or
DIMMs, at speeds up to fSCLK. Fully compliant with the
PC133 SDRAM standard, each bank can be configured to
contain between 16M bytes and 128M bytes of memory.
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single
address space, even if different size devices are used in the
different banks. This enables system designs that are
delivered with an initial configuration that can be upgraded
at a future time with either similar or different memories.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
7
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For current information contact Analog Devices at 800-262-5643
June 2002
A set of programmable timing parameters is available to
configure the SDRAM banks to support slower memory
devices. The memory banks can be configured as either
32-bits wide for maximum performance and bandwidth or
16-bits wide for minimum device count and lower system
cost.
windowed approach is employed, with separate windows in
the ADSP-21535 address space used for accessing the three
PCI address spaces. Base address registers are provided so
that these windows can be positioned to view any range in
the PCI address spaces while they remain fixed in position
in the ADSP-21535 processor's address range.
All four banks share common SDRAM control signals and
have their own bank select lines providing a completely
glueless interface for most system configurations.
For devices on the PCI bus viewing the ADSP-21535's
resources, several mapping registers are provided to enable
resources to be viewed in the PCI address space. The
ADSP-21535’s external memory space, internal L2, and
some I/O MMRs can be selectively enabled as memory
spaces that devices on the PCI bus can use as targets for PCI
memory transactions.
Asynchronous Controller
The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or
I/O devices. Each bank can be independently programmed
with different timing parameters, enabling connection to a
wide variety of memory devices including SRAM, ROM,
and flash EPROM, as well as I/O devices that interface with
standard memory control lines. Each bank occupies a
64M-byte window in the processor’s address space but, if
not fully populated, these are not made contiguous by the
memory controller logic. The banks can also be configured
as 16-bit wide or 32-bit wide buses for ease of interfacing to
a range of memories and I/O devices tailored either to high
performance or to low cost and power.
PCI INTERFACE
The ADSP-21535 provides a glueless logical and electrical,
33-Mhz, 3.3 V, 32-bit PCI (Peripheral Component Interconnect), Revision 2.2-compliant interface. The PCI
interface is designed for a 3-volt signalling environment.
The PCI interface provides a bus bridge function between
the processor core and on-chip peripherals and an external
PCI bus. The PCI interface of the ADSP-21535 supports
two PCI functions, as follows
• A Host to PCI Bridge function, in which the
ADSP-21535 resources (the processor core, internal and
external memory, and the memory DMA controller)
provide the necessary hardware components to emulate
a host PC PCI interface, from the perspective of a PCI
target device.
• A PCI Target function, in which an ADSP-21535 based
intelligent peripheral can be designed to easily interface
to a Revision 2.2-compliant PCI bus.
PCI Host Function
As the PCI host, the ADSP-21535 provides the necessary
PCI host (platform) functions required to support and
control a variety of off-the-shelf PCI I/O devices (e.g.,
Ethernet controllers, bus bridges, etc.) in a system in which
the ADSP-21535 processor is the host.
Note that the Blackfin DSP architecture defines only
memory space (no I/O or config address spaces). The three
address spaces of PCI space (memory, IO, and configuration space) are mapped into the flat 32-bit memory space
of the ADSP-21535. Because the PCI memory space is as
large as the ADSP-21535 memory address space, a
8
PCI Target Function
As a PCI target device, the PCI host processor can configure
the ADSP-21535 subsystem during enumeration of the PCI
bus system. Once configured, the ADSP-21535 subsystem
acts as an intelligent I/O device. When configured as a target
device, the PCI controller uses the memory DMA controller
to perform DMA transfers as required by the PCI host.
USB DEVICE
The ADSP-21535 provides a USB 1.1- compliant device
type interface to support direct connection to a host system.
The USB core interface provides a flexible programmable
environment with up to eight endpoints. Each endpoint can
support all of the USB data types including Control, Bulk,
Interrupt, and Isochronous. Each endpoint provides a
memory-mapped buffer for transferring data to the application. The ADSP-21535 USB port has a dedicated DMA
controller and interrupt input to minimize processor polling
overhead and to enable asynchronous requests for CPU
attention only when transfer management is required.
REAL-TIME CLOCK
The ADSP-21535 Real-Time Clock (RTC) provides a
robust set of digital watch features, including current time,
stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-21535. The RTC
peripheral has dedicated power supply pins, so that it can
remain powered up and clocked, even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per
second, minute, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed
alarm time.
The 32.768 KHz input clock frequency is divided down to
a 1 Hz signal by a prescaler. The counter function of the
timer consists of four counters: a 6-bit second counter, a
6-bit minute counter, a 5-bit hours counter, and an 8-bit
day counter.
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When enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value
in the alarm control register. There are two alarms: The first
alarm is for a time of day. The second alarm is for a day and
time of that day.
The stopwatch function counts down from a programmed
value, with one minute resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is
generated.
Like the other peripherals, the RTC can wake up the
ADSP-21535 processor from a low-power state upon generation of any interrupt.
Connect RTC pins XTALI and XTALO with external components, as shown in Figure 3.
XTALI
XTALO
X1
C2
C1
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC-405 12.5 pF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 3. External Components for RTC
WATCHDOG TIMER
The ADSP-21535 includes a 32-bit timer, which can be
used to implement a software watchdog function. A
software watchdog can improve system availability by
forcing the processor to a known state, via generation of a
hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being
reset by software. The programmer initializes the count
value of the timer, enables the appropriate interrupt, then
enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown
state where software, which would normally reset the timer,
has stopped running due to an external noise condition or
software error.
After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit
in the timer control register, which is set only upon a
watchdog generated reset.
The timer is clocked by the system clock (SCLK), at a
maximum frequency of fSCLK.
ADSP-21535
TIMERS
There are four programmable timer units in the
ADSP-21535. Three general-purpose timers have an
external pin that can be configured either as a Pulse Width
Modulator (PWM) or timer output, as an input to clock the
timer, or for measuring pulse widths of external events. Each
of the three general-purpose timer units can be independently programmed as a PWM, internally or externally
clocked timer, or pulse width counter.
The general-purpose timer units can be used in conjunction
with the UARTs to measure the width of the pulses in the
data stream to provide an auto-baud detect function for a
serial channel.
The general-purpose timers can generate interrupts to the
processor core providing periodic events for synchronization, either to the processor clock or to a count of external
signals.
In addition to the three general-purpose programmable
timers, a fourth timer is also provided. This extra timer is
clocked by the internal processor clock (CCLK) and is
typically used as a system tick clock for generation of
operating system periodic interrupts.
SERIAL PORTS (SPORTS)
The ADSP-21535 incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the
following features:
• Bidirectional operation – Each SPORT has independent
transmit and receive pins.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
• Clocking – Each transmit and receive port can either use
an external serial clock or generate its own, in frequencies
ranging from (fSCLK/131070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 16 bits in length transferred in a format of most
significant bit first or least significant bit first.
• Framing – Each transmit and receive port can run with
or without frame sync signals for each data word. Frame
sync signals can be generated internally or externally,
active high or low, and with either of two pulsewidths and
early or late frame sync.
• Companding in hardware – Each SPORT can perform
A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.
• DMA operations with single-cycle overhead – Each
SPORT can automatically receive and transmit multiple
buffers of memory data. The DSP can link or chain
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sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the descriptor blocks that set up the
chain.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128
channels and is compatible with the H.100, H.110,
MVIP-90, and HMVIP standards.
5.
June 2002
In non-DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCKx line generates the programmed clock pulses
for simultaneously shifting data out on MOSIx and
shifting data in on MISOx. In DMA mode only, transfers
continue until the SPI DMA word count transitions from
1 to 0.
In slave mode, the DSP performs the following sequence to
set up the SPI port to receive data from a master transmitter:
1.
Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
The ADSP-21535 has two SPI-compatible ports that enable
the processor to communicate with multiple SPI-compatible devices.
2.
Defines and generates a receive TCB in the DSP’s
memory space to interrupt at the end of the data transfer (optional in DMA mode only).
The SPI interface uses three pins for transferring data: two
data pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,
SCKx). Two SPI chip select input pins (SPISSx) let other
SPI devices select the DSP, and fourteen SPI chip select
output pins (SPIxSEL7–1) let the DSP select other SPI
devices. The SPI select pins are reconfigured Programmable
Flag pins. Using these pins, the SPI ports provide a full
duplex, synchronous serial interface, which supports both
master and slave modes and multimaster environments.
3.
Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4.
Starts receiving the data on the appropriate SPI SCKx
edges after receiving an SPI chip select on an SPISSx
input pin (reconfigured Programmable Flag pin) from
a master.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
Each SPI port’s baud rate and clock phase/polarities are
programmable (see Figure 4), and each has an integrated
DMA controller, configurable to support transmit or receive
data streams. The SPI’s DMA controller can only service
unidirectional accesses at any given time.
f SCLK
SPI Clock Rate = --------------------------------------2 × SPIBAUD
Figure 4. SPI Clock Rate Calculation
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
In master mode, the DSP performs the following sequence
to set up and initiate SPI transfers:
1.
Enables and configures the SPI port’s operation (data
size, and transfer format).
2.
Selects the target SPI slave with an SPIxSELy output
pin (reconfigured Programmable Flag pin).
3.
Defines one or more TCBs in the DSP’s memory space
(optional in DMA mode only).
4.
Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
10
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. The DSP can
continue, by queuing up the next command TCB.
A slave mode transmit operation is similar, except the DSP
specifies the data buffer in memory from which to transmit
data, generates and relinquishes control of the transmit
TCB, and begins filling the SPI port’s data buffer. If the SPI
controller isn’t ready on time to transmit, it can transmit a
“zero” word.
UART PORT
The ADSP-21535 provides two full duplex Universal Asynchronous Receiver/Transmitter (UART) ports (UART0
and UART1) fully compatible with PC-standard UARTs.
The UART ports provide a simplified UART interface to
other peripherals or hosts, supporting full duplex, DMA
supported, asynchronous transfers of serial data. Each
UART port includes support for 5 to 8 data bits; 1 or 2 stop
bits; and none, even, or odd parity. The UART ports
support two modes of operation, as follows:
• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double-buffered on
both transmit and receive.
• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for recieve.
These DMA channels have lower priority than most
DMA channels because of their relatively low service
rates.
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Each UART port’s baud rate (see Figure 5), serial data
format, error code generation and status, and interrupts are
programmable:
• Supporting bit rates ranging from (fSCLK/ 1048576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured
to generate maskable interrupts to the processor.
f SCLK
UART Clock Rate = ----------------16 × D
Figure 5. UART Clock Rate Calculation1
1
Where D = 1 to 65536
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of UART0 are further extended with
support for the InfraRed Data Association (IrDA®) Serial
InfraRed Physical Layer Link Specification (SIR) protocol.
PROGRAMMABLE FLAGS (PFX)
The ADSP-21535 has 16 bi-directional, general-purpose
I/O, Programmable Flag (PF15–0) pins. The Programmable Flag pins have special functions for clock multiplier
selection, SROM boot mode, and SPI port operation. For
more information, see Serial Peripheral Interface (SPI)
Ports on page 10 and Clock Signals on page 13. Each programmable flag can be individually controlled as follows by
manipulation of the flag control, status, and interrupt
registers:
• Flag Direction Control Register – Specifies the direction
of each individual PFx pin as input or output.
• Flag Control and Status Registers – Rather than forcing
the software to use a read-modify-write process to control
the setting of individual flags, the ADSP-21535 employs
a "write one to set" and "write one to clear" mechanism
that allows any combination of individual flags to be set
or cleared in a single instruction, without affecting the
level of any other flags. Two control registers are provided,
one register is written to in order to set flag values while
another register is written to in order to clear flag values.
Reading the flag status register allows software to interrogate the sense of the flags.
ADSP-21535
• Flag Interrupt Mask Registers – The two Flag Interrupt
Mask Registers allow each individual PFx pin to function
as an interrupt to the processor. Similar to the two Flag
Control Registers that are used to set and clear individual
flag values, one Flag Interrupt Mask Register sets bits to
enable interrupt function, and the other Flag Interrupt
Mask register clears bits to disable interrupt function.
PFx pins defined as inputs can be configured to generate
hardware interrupts, while output PFx pins can be configured to generate software interrupts.
• Flag Interrupt Sensitivity Registers – The two Flag
Interrupt Sensitivity Registers specify whether individual
PFx pins are level- or edge-sensitive and specify-if
edge-sensitive-whether just the rising edge or both the
rising and falling edges of the signal are significant. One
register selects the type of sensitivity, and one register
selects which edges are significant for edge-sensitivity.
DYNAMIC POWER MANAGEMENT
The ADSP-21535 provides four operating modes, each with
a different performance/power-dissipation profile. In
addition, Dynamic Power Management provides the
control functions, with the appropriate external power regulation capability, to dynamically alter the processor core
supply voltage, further reducing power dissipation. Control
of clocking to each of the ADSP-21535 peripherals also
reduces power dissipation. See Table 3 for a summary of
the power settings for each mode.
Full On Operating Mode – Maximum Performance
In the Full On mode, the PLL is enabled, and is not
bypassed, providing the maximum operational frequency.
This is the normal execution state in which maximum performance can be achieved. The processor core and all
enabled peripherals run at full speed.
Active Operating Mode – Moderate Power Savings
In the Active mode, the PLL is enabled, but bypassed. The
input clock (CLKIN) is used to generate the clocks for the
processor core (CCLK) and peripherals (SCLK). When the
PLL is bypassed, CCLK runs at one-half the CLKIN frequency. Significant power savings can be achieved with the
processor running at one-half the CLKIN frequency. In this
mode the PLL multiplication ratio can be changed by
setting the appropriate values in the SSEL fields of the PLL
control register (PLL_CTL).
When in the Active mode, system DMA access to appropriately configured L1 memory is supported.
Table 3. Operating Mode Power Settings
Mode
PLL
PLL Bypassed
Core Clock (CCLK)
System Clock (SCLK)
Full On
Active
Sleep
Deep-Sleep
Enabled
Enabled
Enabled
Disabled
No
Yes
Yes or No
–
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
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Sleep Operating Mode – High Power Savings
Power Savings
The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system
clock (SCLK) however, continue to operate in this mode.
Any interrupt, typically via some external event or RTC
activity, will wake up the processor. When in the Sleep
mode, assertion of any interrupt will cause the processor to
sense the value of the bypass bit (BYPASS) in the PLL
control register (PLL_CTL). If bypass is disabled, the
processor will transition to the Full On mode. If bypass is
enabled, the processor will transition to the Active mode.
As shown in Table 4, the ADSP-21535 supports five
different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating
the internal logic of the ADSP-21535 into its own power
domain, separate from the PLL, RTC, PCI, and other I/O,
the processor can take advantage of dynamic power management, without affecting the PLL, RTC, or other I/O
devices.
When in the Sleep mode, system DMA access to L1
memory is not supported.
Deep-Sleep Operating Mode – Maximum Power Savings
The Deep-Sleep mode maximizes power savings by
disabling the clocks to the processor core (CCLK) and to
all synchronous systems (SCLK). Asynchronous systems,
such as the RTC, may still be running but will not be able
to access internal resources or external memory. This
powered down mode can only be exited by assertion of the
reset interrupt (RESET) or by an asynchronous interrupt
generated by the RTC. When in Deep-Sleep mode,
assertion of RESET causes the processor to sense the value
of the BYPASS pin. If bypass is disabled, the processor will
transition to the Full On mode. If bypass is enabled, the
processor will transition to the Active mode. When in
Deep-Sleep mode, assertion of the RTC asynchronous
interrupt causes the processor to transition to the Full On
mode, regardless of the value of the BYPASS pin.
The DEEPSLEEP output is asserted in this mode.
Mode Transitions
The available mode transitions diagrammed in Figure 6 are
accomplished either by the interrupt events described in the
sections below or by programming the PLLCTL register
with the appropriate values and then executing the PLL
programming sequence.
This instruction sequence takes the processor to a known,
idle state, with the interrupts disabled. Note that all DMA
activity should be disabled during mode transitions.
Table 4. Power Domains
Power Domain
VDD Range
All internal logic, except PLL and RTC
Analog PLL internal logic
RTC internal logic and crystal I/O
PCI I/O
All other I/O
VDDINT
VDDPLL
VDDRTC
VDDPCIEXT
VDDEXT
The power dissipated by a processor is largely a function of
the clock frequency of the processor and the square of the
operating voltage. For example, reducing the clock
frequency by 25% results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power
dissipation by more than 40%. Further, these power savings
are additive, in that if the clock frequency and power are
both reduced the power savings are dramatic.
Dynamic Power Management allows both the processor’s
input voltage (VDDINT) and clock frequency (fCLK) to be
dynamically controlled.
As explained above, the savings in power dissipation can be
modeled by the following equation:
Power Dissipation Factor=(fCCLKRED /fCCLKNOM) ⴛ
(VDDINTRED /VDDINTNOM)2
where
• fCCLKNOM is the nominal core clock frequency
(300 MHz)
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
(1.5 V)
• VDDINTRED is the reduced internal supply voltage
As an example of how significant the power savings of
Dynamic Power Management are, when both frequency and
voltage are reduced, consider an example where the
frequency is reduced from its nominal value to 50 MHz and
the voltage is reduced from its nominal value to 1.2 V. At
this reduced frequency and voltage, the processor dissipates
about 10% of the power dissipated at nominal frequency
and voltage.
12
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SLEEP
STOPCK=1 &
PDWN=0
ADSP-21535
WAKEUP &
BYPASS=0
STOPCK=1 &
PDWN=0
WAKEUP &
BYPASS=1
BYPASS=0 & PLL_OFF=0 &
STOPCK=0 & PDWN=0
ACTIVE
FULL-ON
BYPASS=1 & STOPCK=0 &
PDWN=0
PDWN=1
PDWN=1
RTC_WAKEUP
DEEP
SLEEP
HARDWARE
RESET
RESET
MSEL=NEW & PLL_OFF=0 &
BYPASS=1
MSEL=NEW & PLL_OFF=0 &
BYPASS=0
Figure 6. Mode Transitions
Peripheral Power Control
CLOCK SIGNALS
The ADSP-21535 provides additional power control capability by allowing dynamic scheduling of clock inputs to each
of the peripherals. Clocking to each of the peripherals listed
below can be enabled or disabled by appropriately setting
the peripheral’s control bit in the Peripheral Clock Enable
Register (PLL_IOCK). The Peripheral Clock Enable
Register allows individual control for each of the following
peripherals:
The ADSP-21535 can be clocked by a sine wave input, or
a buffered, shaped clock derived from an external clock
oscillator.
• PCI
• EBIU controller
• Programmable flags
• MemDMA controller
• SPORT 0
• SPORT 1
• SPI 0
• SPI 1
• UART 0
If a buffered, shaped clock is used, this external clock
connects to the DSP's CLKIN pin. CLKIN input cannot
be halted, changed, or operated below the specified
frequency during normal operation. This clock signal
should be a TTL-compatible signal. The DSP provides a
user-programmable 1x to 31x multiplication of the input
clock, to support external to internal (DSP core) clock
ratios. The MSEL6–0, BYPASS, and DF pins decide the
PLL multiplication factor at reset. At runtime, the multiplication factor can be controlled in software. The
combination of pullup and pull-down resistors in Figure 7
sets up a core clock ratio of 6:1, which, for example,
produces a 150-MHz core clock from the 25-MHz input.
For other clock multiplier settings, see the ADSP-21535
DSP Hardware Reference.
The peripheral clock is supplied to the CLKOUT_SCLK0
pin.
• UART 1
• Timer 0, Timer 1, Timer 2
• USB CLK
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ADSP-21535
June 2002
be changed dynamically by writing the appropriate values
to the PLL control register (PLL_CTL), as described in the
ADSP-21535 DSP Hardware Reference.
CLKIN
CLKOUT
BOOTING MODES
VDD
MSEL0
(PF0)
VDD
MSEL1
(PF1)
The ADSP-21535 has three mechanisms (listed in Table 6)
for automatically loading internal L2 memory after a reset.
A fourth mode is provided to execute from external
memory, bypassing the boot sequence.
ADSP-21535
Table 6. Booting Modes
MSEL2
(PF2)
MSEL3
(PF3)
MSEL4
(PF4)
BMODE2–0
Description
000
Execute from 16-bit external memory
(Bypass Boot ROM)
Boot from 8-bit flash
Boot from SPI0 serial ROM (8-bit
address range)
Boot from SPI0 serial ROM (16-bit
address range)
Reserved
001
010
MSEL5
(PF5)
011
MSEL6
(PF6)
THE PULL-UP/PULLDOWN RESISTORS ON
THE MSEL, DF, AND
BYPASS PINS SELECT
THE CORE CLOCK
RATIO.
DF (PF7)
BYPASS
RESET
SOURCE
HERE, THE SELECTION
(6:1) AND 25MHz INPUT
CLOCK PRODUCE A
150MHz CORE CLOCK.
RESET
Figure 7. Clock Ratio Example
All on-chip peripherals operate at the rate set by the system
clock (SCLK). The system clock frequency is programmable by means of the SSEL pins. At run time the system clock
frequency can be controlled in software by writing to the
SSEL fields in the PLL control register (PLL_CTL). The
values programmed into the SSEL fields define a divide
ratio between the core clock (CCLK) and the system clock.
Table 5 illustrates the system clock ratios.
Table 5. System Clock Ratios
Signal
Name
SSEL1– 0
Divider
Ratio
CCLK/
SCLK
Example Frequency
Ratios (MHz)
CCLK
SCLK
00
01
10
11
2:1
2.5:1
3:1
4:1
266
275
300
300
133
110
100
75
The maximum frequency of the system clock is fSCLK. Note
that the divisor ratio must be chosen to limit the system clock
frequency to its maximum of fSCLK. The reset value of the
SSEL1–0 is determined by sampling the Programmable
Flag input pins (PF9–8) during reset. The SSEL value can
14
100 –111
The BMODE pins of the Reset Configuration Register,
sampled during power on resets and software initiated
resets, implement the following modes:
• Execute from 16-bit external memory – Execution
starts from address 0x2000000 with 16-bit packing.
The boot ROM is bypassed in this mode.
• Boot from 8-bit external flash memory – The 8-bit flash
boot routine located in boot ROM memory space is set
up using asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible
(3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
• Boot from SPI serial EEPROM (8-bit addressable) –
The SPI0 uses PF10 output pin to select a single SPI
EPROM device, submits a read command at address
0x00, and begins clocking data into the beginning of L2
memory. An 8-bit addressable SPI-compatible
EPROM must be used.
• Boot from SPI serial EEPROM (16-bit addressable) –
The SPI0 uses PF10 output pin to select a single SPI
EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of
L2 memory. A 16-bit addressable SPI-compatible
EPROM must be used.
For each of the boot modes described above, a four-byte
value is first read from the memory device. This value is
used to specify a subsequent number of bytes to be read into
the beginning of L2 memory space. Once each of the loads
is complete, the processor jumps to the beginning of L2
space and begins execution.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
For current information contact Analog Devices at 800-262-5643
In addition, the Reset Configuration Register can be set by
application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly
to the beginning of L2 memory space.
To augment the boot modes described above, a secondary
software loader is provided that adds additional booting
mechanisms. This secondary loader provides the capability
to boot from 16-bit flash memory, fast flash, variable baud
rate, etc.
INSTRUCTION SET DESCRIPTION
The Blackfin DSP family assembly language instruction set
employs an algebraic syntax that was designed for ease of
coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded
instruction set that compiles to a very small final memory
size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use
many of the DSP core resources in a single instruction.
Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling
C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a
supervisor (O/S kernel, device drivers, debuggers, ISRs)
mode of operations, allowing multiple levels of access to
core DSP resources.
ADSP-21535
The VisualDSP++ project management environment lets
programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on
an algebraic syntax, an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. A key point for
these tools is C/C++ code efficiency. The compiler has been
developed for efficient translation of C/C++ code to
Blackfin DSP assembly. The Blackfin DSP has architectural
features that improve the efficiency of
compiled C/C++ code.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following
advantages:
The VisualDSP++ debugger has a number of important
features. Data visualization is enhanced by a plotting
package that offers a significant level of flexibility. This
graphical representation of user data enables the programmer to quickly determine the performance of an algorithm.
As algorithms grow in complexity, this capability can have
increasing significance on the designer’s development
schedule, increasing productivity. Statistical profiling
enables the programmer to nonintrusively poll the processor
as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather
important code execution metrics without interrupting the
real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance, and
take corrective action.
• Seamlessly integrated DSP/CPU features are optimized
for both 8-bit and 16-bit operations.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• A super-pipelined multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four
8-bit ALU + two load/store + two pointer updates per
cycle.
• View mixed C/C++ and assembly code (interleaved
source and object information)
• All registers, I/O, and memory are mapped into a unified
4G-byte memory space providing a simplified programming model.
• Insert break-points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Microcontroller features, such as arbitrary bit and
bit-field manipulation, insertion, and extraction; integer
operations on 8-, 16-, and 32-bit data-types; and separate
user and kernel stack pointers.
• Perform linear or statistical profiling of program
execution
• Code density enhancements, which include intermixing
of 16- and 32-bit instructions (no mode switching, no
code segregation). Frequently used instructions are
encoded as 16-bits.
• Create custom debugger windows
DEVELOPMENT TOOLS
The ADSP-21535 is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and the VisualDSP++™ development
environment. The same emulator hardware that supports
other Analog Devices JTAG DSPs, also fully emulates the
ADSP-21535.
REV. PrC
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all
development tools, including Color Syntax Highlighting in
the VisualDSP++ editor. These capabilities permit programmers to:
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
15
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
The VisualDSP++ Kernel (VDK) incorporates scheduling
and resource management tailored specifically to address
the memory and timing constraints of DSP programming.
These capabilities enable engineers to develop code more
effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK
features include Threads, Critical and Unscheduled
regions, Semaphores, Events, and Device flags. The VDK
also supports Priority-based, Pre-emptive, Cooperative and
Time -Sliced scheduling approaches. In addition, the VDK
was designed to be scalable. If the application does not use
a specific feature, the support code for that feature is
excluded from the target system.
Because the VDK is a library, a developer can decide
whether to use it or not. The VDK is integrated into the
VisualDSP++ development environment, but can also be
used via standard command line tools. When the VDK is
used, the development environment assists the developer
with many error-prone tasks and assists in managing system
resources, automating the generation of various VDK based
objects, and visualizing the system state, when debugging
an application that uses the VDK.
Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21535 to monitor and control
the target board processor during emulation. The emulator
provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of
the processor’s JTAG interface—the emulator does not
affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin DSP family.
Hardware tools include the ADSP-21535 EZ-KIT Lite™
standalone evaluation/development cards. Third Party
software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board
(Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and
software systems. Analog Devices has supplied an IEEE
1149.1 JTAG Test Access Port (TAP) on the ADSP-21535.
The emulator uses the TAP to access the internal features
of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and
commands, but once an operation has been completed by
the emulator, the DSP system is set running at full speed
with no impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.
16
June 2002
Target Board Header
The emulator interface to an Analog Devices’ JTAG DSP
is a 14-pin header, as shown in Figure 8. The customer must
supply this header on the target board in order to communicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on
0.1" ⴛ 0.1" spacing, with a minimum post length of 0.235".
Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the target
board.
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
1
2
EMU
GND
3
4
5
6
7
8
9
10
KEY (NO PIN)
GND
TMS
BTMS
BTCK
TCK
BTRST
TRST
11
12
BTDI
TDI
13
14
GND
TDO
TOP VIEW
Figure 8. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in
Place)
As can be seen in Figure 8, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 9. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 10 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure 11 displays the keep-out
area for a target board header. The keep-out area allows the
pod connector to properly seat onto the target board header.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
GND
1
2
3
4
0.10"
GND
KEY (NO PIN)
5
6
BTMS
TMS
7
8
BTCK
TCK
9
BTRST
10
TRST
9
11
12
BTDI
GND
EMU
ADSP-21535
TDI
13
14
TDO
TOP VIEW
Figure 9. JTAG Target Board Connector with No Local
Boundary Scan
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
0.15"
Figure 11. JTAG Pod Connector Keep-Out Area
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68”. This document is
updated regularly to keep pace with improvements to
emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-21535 architecture and functionality. For detailed
information on the Blackfin DSP Family core architecture
and instruction set, refer to the ADSP-21535 Hardware
Reference and the Blackfin DSP Family Instruction Set
Reference.
0.64"
0.88"
0.24"
Figure 10. JTAG Pod Connector Dimensions
REV. PrC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
17
PRELIMINARY TECHNICAL DATA
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ADSP-21535
PIN DESCRIPTIONS
ADSP-21535 pin definitions are listed in Table 7. The
following pins are asynchronous: ARDY, PF15–0,
USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI,
XTALO.
June 2002
The following symbols appear in the Type column of
Table 7: I = Input, O = Output, T = Three-State, P =
Power, and G = Ground.
Table 7. Pin Descriptions
Pin
Type
Function
ADDR25–2
O/T
External address bus.
DATA31–01
I/O/T
External data bus.
ABE
/SDQM3–0
O/T
Asynchronous memory byte enables, SDRAM data masks.
AMS3–0
O/T
Chip selects for asynchronous memories.
ARDY1, 2
I
Acknowledge signal for asynchronous memories.
AOE
O/T
Memory output enable for asynchronous memories.
ARE
O
Read enable for asynchronous memories.
AWE
O
Write enable for asynchronous memories.
CLKOUT
/SCLK1
O
SDRAM clock output pin. Same frequency and timing as SCLK0. Provided to reduce
capacitance loading on SCLK0. Connect to SDRAM’s CK pin.
SCLK0
O
SDRAM clock output pin 0. Switches at system clock frequency. Connect to the
SDRAM’s CK pin.
SCKE
O/T
SDRAM clock enable pin. Connect to SDRAM’s CKE pin.
SA10
O/T
SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device
during host bus requests. Connect to SDRAM’s A10 pin.
SRAS
O/T
SDRAM row address strobe pin. Connect to SDRAM’s RAS pin.
SCAS
O/T
SDRAM column address select pin. Connect to SDRAM’s CAS pin.
SWE
O/T
SDRAM write enable pin. Connect to SDRAM’s WE or W buffer pin.
SMS3–0
O/T
Memory select pin of external memory bank configured for SDRAM. Connect to
SDRAM’s chip select pin.
TMR02
I/O/T
Timer 0 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR12
I/O/T
Timer 1 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR22
I/O/T
Timer 2 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
PF15
/SPI1SEL72
I/O/T
Programmable flag pin. SPI output select pin.
PF14
/SPI0SEL72
I/O/T
Programmable flag pin. SPI output select pin.
PF13
/SPI1SEL62
I/O/T
Programmable flag pin. SPI output select pin.
18
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
ADSP-21535
Table 7. Pin Descriptions (Continued)
Pin
Type
Function
PF12
/SPI0SEL62
I/O/T
Programmable flag pin. SPI output select pin.
PF11
/SPI1SEL52
I/O/T
Programmable flag pin. SPI output select pin.
PF10
/SPI0SEL52
I/O/T
Programmable flag pin. SPI output select pin (used during SPI boot).
PF9
/SPI1SEL4
/SSEL13
I/O
Programmable flag pin. SPI output select pin. Sampled during reset to determine core
clock to system clock ratio.
PF8
/SPI0SEL4
/SSEL03
I/O
Programmable flag pin. SPI output select pin. Sampled during reset to determine core
clock to system clock ratio.
PF7
/SPI1SEL3
/DF3
I/O
Programmable flag pin. SPI output select pin.Sensed for configuration state during
hardware reset, used to configure the PLL. DF=1 is for high frequency clock and divides
the input clock by 2. DF=0 passes input clock directly to PLL phase detector.
PF6
/SPI0SEL3
/MSEL63
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF5
/SPI1SEL2
/MSEL53
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF4
/SPI0SEL2
/MSEL43
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF3
/SPI1SEL1
/MSEL33
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF2
/SPI0SEL1
/MSEL23
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF1
/SPISS1
/MSEL13
I/O
Programmable flag pin. SPI slave select input pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF0
/SPISS0
/MSEL03
I/O
Programmable flag pin. SPI slave select input pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
RSCLK02
I/O/T
Receive serial clock for SPORT0.
I/O/T
Receive frame synchronization for SPORT0.
I
Serial data receive for SPORT0.
I/O/T
Transmit serial clock for SPORT0.
TFS02
I/O/T
Transmit frame synchronization for SPORT0.
DT0
O
Serial data transmit for SPORT0.
RFS0
2
DR03
TSCLK0
2
REV. PrC
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19
PRELIMINARY TECHNICAL DATA
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ADSP-21535
June 2002
Table 7. Pin Descriptions (Continued)
Pin
Type
Function
RSCLK12
I/O/T
Receive serial clock for SPORT1.
RFS12
I/O/T
Receive frame synchronization for SPORT1.
I
Serial data receive for SPORT1.
I/O/T
Transmit serial clock for SPORT1.
I/O/T
Transmit frame synchronization for SPORT1.
DR1
3
TSCLK12
TFS1
2
DT1
O
Serial data transmit for SPORT1.
2
I/O
Master out slave in pin for SPI0. Supplies the output data from the master device and
receives the input data to a slave device.
MISO02
I/O
Master in slave out pin for SPI0. Supplies the output data from the slave device and
receives the input data to the master device.
SCK04
MOSI0
I/O
Clock line for SPI0. Master device output clock signal. Slave device input clock signal.
2
I/O
Master out slave in pin for SPI1. Supplies the output data from the master device and
receives the input data to a slave device.
MISO12
I/O
Master in slave out pin for SPI1. Supplies the output data from the slave device and
receives the input data to the master device.
SCK14
I/O
Clock line for SPI1. Master device output clock signal. Slave device input clock signal.
I
UART0 receive pin.
O
UART0 transmit pin.
I
UART1 receive pin.
O
UART1 transmit pin.
I
USB clock.
I
Single ended receive data output from USB transceiver to the USBD module.
I
Differential D+ receive data output from the USB transceiver to the UBD module.
I
Differential D- receive data output from the USB transceiver to the USBD module.
TXDPLS
O
Transmitted D+ from the USBD module to the USB transceiver.
TXDMNS
O
Transmitted D- from the USBD module to the USB transceiver.
TXEN
O
Transmit enable from the USBD module to the USB transceiver.
SUSPEND
O
Suspend mode enable output from the USBD module to the USB transceiver. This signal
can also be routed internally by the SoC to support low power operations.
NMI4
I
Non-maskable interrupt.
TCK2
I
JTAG clock.
TDO
O/T
JTAG serial data out.
TDI2
I
JTAG serial data in.
I
Test mode select.
I
JTAG reset.
MOSI1
RX0
3
TX0
RX1
3
TX1
USB_CLK4
XVER_DATA
DPLS4
DMNS
TMS2
TRST
20
4
4
4
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
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June 2002
ADSP-21535
Table 7. Pin Descriptions (Continued)
Pin
Type
Function
RESET
I
When this pin is asserted to logic zero level for at least 10 CLKIN cycles, a hardware
reset is initiated. The minimum pulse width for power-on reset is 40 µsec.
CLKIN1
I
Clock in.
BYPASS
I
Dedicated mode pin. May be permanently strapped to VDD or VSS. Bypasses the on-chip
PLL.
DEEPSLEEP
O
Denotes that the Blackfin DSP Core is in Deep-Sleep mode.
BMODE2–0
I
Dedicated mode pin. May be permanently strapped to VDD or VSS. Configures the boot
mode that is employed following hardware reset or software reset.
PCI_AD31–02
I/O/T
PCI address and data bus.
PCI_CBE3–02
I/O/T
PCI byte enables.
PCI_FRAME
I/O/T
PCI frame signal. Used by PCI initiators for signalling the beginning and end of a PCI
transaction.
I/O/T
PCI initiator ready signal.
I/O/T
PCI target ready signal.
I/O/T
PCI device select signal. Asserted by targets of PCI transactions to claim the transaction.
PCI_STOP2
I/O/T
PCI stop signal.
PCI_PERR
I/O/T
PCI parity error signal.
PCI_PAR2
I/O/T
PCI parity signal.
PCI_REQ
O
PCI request signal. Used for requesting the use of the PCI bus.
PCI_SERR2
I/O/T
PCI system error signal. Requires a pullup on the system board.
PCI_RST
I/O/T
PCI reset signal.
I
PCI grant signal. Used for granting access to the PCI bus.
PCI_IDSEL4
I
PCI initialization device select signal. Individual device selects for targets of PCI configuration transactions.
PCI_LOCK2
I
PCI lock signal. Used to lock a target or the entire PCI bus for use by the master that
asserts the lock.
PCI_CLK4
I
PCI clock.
PCI_INTA2
I/O/T
PCI interrupt A line on PCI bus. Asserted by the ADSP-21535 as a device to signal an
interrupt to the system processor. Monitored by the ADSP-21535 when acting as the
system processor.
PCI_INTB2
I
PCI interrupt B line. Monitored by ADSP-21535 when acting as the system processor.
PCI_INTC2
I
PCI interrupt C line. Monitored by the ADSP-21535 when acting as the system
processor.
PCI_INTD2
I
PCI interrupt D line. Monitored by the ADSP-21535 when acting as the system
processor.
XTALI
I
Real-Time Clock oscillator input.
XTALO
O
Real-Time Clock oscillator output.
2
PCI_IRDY2
PCI_TRDY2
PCI_DEVSEL
2
2
PCI_GNT
2
REV. PrC
2
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Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
21
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ADSP-21535
June 2002
Table 7. Pin Descriptions (Continued)
Pin
Type
Function
EMU
O
Emulator acknowledge, open drain. Must be connected to the ADSP-21535 emulator
target board connector only.
VDDPLL
P
PLL power supply (1.5 V nominal).
VDDRTC
P
Real-Time Clock power supply (3.3 V nominal).
VDDEXT
P
I/O (except PCI) power supply (3.3 V nominal).
VDDPCIEXT
P
PCI I/O power supply (3.3 V nominal).
VDDINT
P
Internal power supply (1.5 V nominal).
GND
G
Power supply return.
1
Pin has a logic-level hold circuit that prevents the input from floating internally.
Pull pin high, if not used.
3
Pull pin high or low, if not used.
4
Pull pin low, if not used.
2
22
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REV. PrC
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June 2002
For current information contact Analog Devices at 800-262-5643
ADSP-21535
ADSP-21535—SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter 1
K Grade Parameter
Min
Nominal
Max
Unit
VDDINT
VDDEXT
VDDPLL
VDDRTC
VDDPCIEXT
VIH
VIL
VIHPCI
VILPCI
TCASE
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
PLL Power Supply Voltage
Real Time Clock Power Supply Voltage
PCI I/O Power Supply Voltage
High Level Input Voltage2, @ VDDEXT =max
Low Level Input Voltage2, @ VDDEXT =min
High Level Input Voltage3, @ VDDEXT =max
Low Level Input Voltage3, @ VDDINT =min
Case Operating Temperature
0.86
2.5
1.425
2.60
3.15
2.0
–0.3
0.5 VDDPCIEXT
–0.5
0
1.5
3.3
1.5
3.3
3.3
1.575
3.45
1.575
3.45
3.45
VDDEXT +0.5
0.6
VDDPCIEXT +0.5
0.3 VDDPCIEXT
85
V
V
V
V
V
V
V
V
V
ºC
1
Specifications subject to change without notice.
Applies to input and bidirectional pins, except PCI.
3
Applies to PCI input and bidirectional pins: PCI_AD31– 0, PCI_CBE3 – 0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP,
PCI_PERR, PCI_PAR, PCI_SERR, PCI_RST, PCI_GNT, PCI_IDSEL, PCI_LOCK, PCI_CLK, PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD.
2
ELECTRICAL CHARACTERISTICS
Parameter1
2
VOH
High Level Output Voltage
VOL
Low Level Output Voltage2
VOHPCI
IIH
PCI High Level Output
Voltage3
PCI Low Level Output
Voltage3
High Level Input Current4
IIL
Low Level Input Current4
IOZH
Three-State Leakage Current5
IOZL
Three-State Leakage Current5
CIN
Input Capacitance6, 7
VOLPCI
Test Conditions
Min
@ VDDEXT =min,
IOH = –0.5 mA
@ VDDEXT =min,
IOL = 2.0 mA
@ VDDEXT =min,
IOH = –0.5 mA
@ VDDEXT =min,
IOL = 1.5mA
@ VDDEXT =max,
VIN = VDD max
@ VDDEXT =max,
VIN = 0 V
@ VDDEXT = max,
VIN = VDD max
@ VDDEXT = max,
VIN = 0 V
fIN = 1 MHz,
TCASE = 25°C,
VIN = 2.5 V
2.4
Max
Unit
V
0.4
0.9 VDDPCIEXT
V
V
0.1 VDDPCIEXT
V
TBD
µA
TBD
µA
TBD
µA
TBD
µA
TBD
pF
1
Specifications subject to change without notice.
Applies to output and bidirectional pins, except PCI.
3
Applies to PCI output and bidirectional pins: PCI_AD31–0, PCI_CBE3–0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP,
PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA.
4
Applies to input pins.
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
2
REV. PrC
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23
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
June 2002
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 . . –0.3 V to +1.8 V
External (I/O) Supply Voltage (VDDEXT) . . . –0.3 V to +4.0 V
Input Voltage. . . . . . . . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Output Voltage Swing . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Core Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 MHz
Peripheral Clock (SCLK) . . . . . . . . . . . . . . . . . . 133 MHz
Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 seconds). . . . . . . . . . . . . . . . . .185ºC
1
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21535 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
Table 8 and Table 9 describe the timing requirements for the ADSP-21535 clocks. Take care in selecting MSEL and SSEL
ratios so as not to exceed the maximum core clock and system clock operating frequencies, as described in ABSOLUTE
MAXIMUM RATINGS. Table 9 describes Phase-Locked Loop operating conditions.
Table 8. Core and System Clock Requirements
Parameter
Description
Min
Max
Unit
tCCLK1.5
tCCLK1.4
tCCLK1.3
tCCLK1.2
tCCLK1.1
tCCLK1.0
tCCLK0.9
fCCLKNN
tSCLK
Core Cycle Period (VDDINT =1.5 V–5%)
Core Cycle Period (VDDINT =1.4 V–5%)
Core Cycle Period (VDDINT =1.3 V–5%)
Core Cycle Period (VDDINT =1.2 V–5%)
Core Cycle Period (VDDINT =1.1 V–5%)
Core Cycle Period (VDDINT =1.0 V–5%)
Core Cycle Period (VDDINT =0.9 V–5%)
Core Clock Frequency at tCCLKNN
System Clock Period
3.3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1/tCCLKNN
ns
ns
ns
ns
ns
ns
ns
Hz
ns
fSCLK
System Clock Frequency
1/tSCLK
Hz
Max. of (7.5 or
tCCLKNN ⴛ2)
Table 9. Phase-Locked Loop Operating Conditions
Parameter
Min
Nominal
Max
Unit
Operating Voltage
Jitter, Rising Edge To Rising Edge, Per Output
Jitter, Rising Edge To Falling Edge, Per Output
1.425
1.5
1.575
120
60
V
ps
ps
24
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Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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ADSP-21535
Table 9. Phase-Locked Loop Operating Conditions (Continued)
Parameter
Min
Skew, Rising Edge To Rising Edge, Any Two
outputs
Voltage Controlled Oscillator (VCO) Frequency
VDDPLL induced jitter
REV. PrC
40
Nominal
Max
Unit
120
ps
400
1
MHz
ps/mV
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
25
PRELIMINARY TECHNICAL DATA
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ADSP-21535
June 2002
Clock and Reset Timing
Table 10 and Figure 12 describe clock and reset operations. Per ABSOLUTE MAXIMUM RATINGS on page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 300/133 MHz.
Table 10. Clock and Reset Timing
Parameter
Description
Timing Requirements
tCKIN
CLKIN Period
CLKIN Low Pulse1
tCKINL
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulsewidth Low2
tPFD
Delay from RESET Asserted to PFx I/O Terminated3
tMSD
Delay from RESET Asserted to MSELx and DF Valid4
tMSS
MSELx/DF/BYPASS Stable Setup Before RESET
Deasserted5
MSELx/DF/BYPASS Stable Hold After RESET
tMSH
Deasserted
Switching Characteristics
CLKOUT Delay from CLKIN
tSCLKD
tSCLK
CLKOUT Period6
Min
Max
Unit
30.0
10.0
10.0
11ⴛtCKIN
100.0
TBD
ns
ns
ns
ns
ns
ns
ns
TBD
ns
TBD
TBD
TBD
7.5
TBD
ns
ns
1
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while
RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
3
From this point, the MSELx and DF values begin stabilizing to a valid state.
4
MSELx and DF values can change from this point, but the values must be valid.
5
MSELx and DF values must be held from this time, until the hold time expires.
6
The figure below shows a ⴛ2 ratio between tCKIN and tSCLK, but the ratio has many programmable options. For more information, see the System Design
chapter of the ADSP-21535 DSP Hardware Reference.
2
t CKI N
CLKIN
t CKI NH
t CKI NL
t WRST
RESET
t MSD
t MSS
t MS H
t PFD
MSEL6–0
BYPASS
DF
t SCLKD
t SCLK
CLKOUT
Figure 12. Clock and Reset Timing
26
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ADSP-21535
Programmable Flags Cycle Timing
Table 11 and Figure 13 describe programmable flag operations.
Table 11. Programmable Flags Cycle Timing
Parameter
Description
Switching Characteristic
tDFO
Flag output delay with respect to SCLK
tHFO
Flag output hold after SCLK high
Timing Requirement
Flag input hold is asynchronous
tHFI
Min
Max
Unit
TBD
6
TBD
ns
ns
3
ns
SCLK
tDFO
tDFO
PF
(OUTPUT)
FLAG OUTPUT
tHFI
PF
(INPUT)
FLAG INPUT
Figure 13. Programmable Flags Cycle Timing
REV. PrC
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27
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ADSP-21535
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June 2002
Timer PWM_OUT Cycle Timing
Table 12 and Figure 14 describe timer expired operations.
The input signal is asynchronous in “width capture mode”
and has an absolute maximum input frequency of TBD MHz.
Table 12. Timer PWM_OUT Cycle Timing
Parameter
1
Description
Min
Max
Unit
Switching Characteristic
Timer Pulsewidth Output1
tHTO
7.5
(232–1) cycles
ns
32
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (2 –1) cycles.
SCLK
tHTO
PWM_OUT
Figure 14. Timer PWM_OUT Cycle Timing
28
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ADSP-21535
Asynchronous Memory Write Cycle Timing
Table 13. Asynchronous Memory Write Cycle Timing
Parameter
Description
Min
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
tDDAT
DATA31–0 Disable After CLKOUT
tENDAT
DATA31–0 Enable After CLKOUT
Switching Characteristic
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
Max
5.5
0.0
6.0
1.0
6.0
0.8
Unit
ns
ns
ns
ns
ns
ns
Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
t ENDAT
DATA15–0
t DDAT
WRITE DATA
AWE
t SARDY
t HARDY
ARDY
Figure 15. Asynchronous Memory Write Cycle Timing
REV. PrC
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June 2002
Asynchronous Memory Read Cycle Timing
Table 14. Asynchronous Memory Read Cycle Timing
Parameter
Description
Min
Timing Requirements
tSDAT
DATA31–0 Setup Before CLKOUT
tHDAT
DATA31–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristic
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
Max
Unit
2.1
0.8
5.5
0.0
ns
ns
ns
ns
6.0
ns
ns
0.8
Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
t SDAT
DATA15–0
t HDAT
READ
AOE
t DO
ARE
t SARDY
t HARDY
t HARDY
ARDY
Figure 16. Asynchronous Memory Read Cycle Timing
30
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SDRAM Interface Timing
Table 15. SDRAM Interface Timing
Parameter
Description
Min
Timing Requirement
tSSDAT
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
tHSDAT
Switching Characteristic
CLKOUT Period
tSCLK
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
tDCAD
Command, ADDR, Data Delay After CLKOUT1
tHCAD
Command, ADDR, Data Hold After CLKOUT1
tDSDAT
Data Disable After CLKOUT
Data Enable After CLKOUT
tENSDAT
1
Max
Unit
2.1
0.8
ns
ns
7.5
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
6.0
0.8
6.0
1.0
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
t SCLKH
t SCLK
CLKOUT
t SSDAT
t SCLKL
t HSDAT
DATA
(IN)
t DSDAT
t DCAD
t ENSDAT
t HCAD
DATA
(OUT)
t DCAD
CMND1
ADDR
(OUT)
t HCAD
NOTES
1COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SAIO, SCKE.
Figure 17. SDRAM Interface Timing
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Serial Ports
Table 16. Serial Ports—External Clock
Parameter
Description
Timing Requirements
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
tHFSE
TFS/RFS Hold After TCLK/RCLK1
tSDRE
Receive Data Setup Before RCLK1
tHDRE
Receive Data Hold Before RCLK1
tSCLKW
TCLK/RCLK Width
TCLK/RCLK Period
tSCLK
1
Min
Max
3.0
3.0
3.0
3.0
4.5
15.0
Unit
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
Table 17. Serial Ports—Internal Clock
Parameter
Description
Timing Requirements
tSFSI
TFS/RFS Setup Before TCLK/RCLK1
tHFSI
TFS/RFS Hold After TCLK/RCLK1
tSDRI
Receive Data Setup Before RCLK1
tHDRI
Receive Data Hold Before RCLK1
1
Min
Max
7.0
2.0
7.0
4.0
Unit
ns
ns
ns
ns
Referenced to sample edge.
Table 18. Serial Ports—External or Internal Clock
Parameter
Description
Switching Characteristics
tDFSE
RFS Delay After RCLK (Internally Generated RFS)1
tHOFSE
RFS Hold After RCLK (Internally Generated RFS)1
1
Min
Max
Unit
10.0
ns
ns
Max
Unit
10.0
ns
ns
ns
ns
6.0
Referenced to drive edge.
Table 19. Serial Ports—External Clock
Parameter
Description
Switching Characteristics
TFS Delay After TCLK (Internally Generated TFS)1
tDFSE
tHOFSE
TFS Hold After TCLK (Internally Generated TFS)1
tDDTE
Transmit Data Delay After TCLK1
tHDTE
Transmit Data Hold After TCLK1
1
Min
6.0
10.0
6.0
Referenced to drive edge.
Table 20. Serial Ports—Internal Clock
Parameter
Description
Switching Characteristics
tDFS
TFS Delay After TCLK (Internally Generated TFS)1
tHOFS
TFS Hold After TCLK (Internally Generated TFS)1
tDDT
Transmit Data Delay After TCLK1
Transmit Data Hold After TCLK1
tHDT
tSCLKIW
TCLK/RCLK Width
Min
I
I
1
Unit
4.0
ns
ns
ns
ns
ns
0.0
4.0
I
I
Max
0.0
4.5
Referenced to drive edge.
32
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Table 21. Serial Ports—Enable and Three-State
Parameter
Description
Switching Characteristics
tDTENE
Data Enable Delay from External TCLK1
tDDTTE
Data Disable Delay from External TCLK1
tDTENI
Data Enable Delay from Internal TCLK
tDDTTI
Data Disable Delay from Internal TCLK1
1
Min
Max
5.0
12.0
2.0
5.0
Unit
ns
ns
ns
ns
Referenced to drive edge.
REV. PrC
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DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
June 2002
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tSFSI
tDFSE
tHOFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tSFSI
TFS
tDFSE
tHOFSE
tHFSI
tSFSE
tHFSE
TFS
tHDTI
tDDTI
tHDTE
DT
tDDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
TCLK (EXT)
TFS ("LATE", EXT.)
DRIVE
EDGE
TCLK / RCLK
tDDTEN
tDDTTE
DT
DRIVE
EDGE
TCLK (INT)
TFS ("LATE", INT.)
DRIVE
EDGE
TCLK / RCLK
tDDTIN
tDDTTI
DT
Figure 18. Serial Ports
34
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Serial Peripheral Interface (SPI) Port—Master Timing
Table 22 and Figure 19 describe SPI port master operations.
Table 22. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Description
Min
Max
Unit
Timing Requirements
tSSPID
Data input valid to SCLK edge (data input setup)
tHSPID
SCLK sampling edge to data input invalid
1.6
1.6
ns
ns
Switching Characteristics
SPIxSEL low to first SCLK edge (x=0 or 1)
tSDSCIM
tSPICHM
Serial clock high period
tSPICLM
Serial clock low period
tSPICLK
Serial clock period
tHDSM
Last SCLK edge to SPIxSEL high (x=0 or 1)
tSPITDM
Sequential transfer delay
SCLK edge to data out valid (data out delay)
tDDSPID
tHDSPID
SCLK edge to data out invalid (data out hold)
2tSCLK
2tSCLK
2tSCLK
4tSCLK
2tSCLK
2tSCLK
0
0
ns
ns
ns
ns
ns
ns
ns
ns
6
5
SPIxSEL
(OUT PU T)
(x = 0 or 1)
tSDSCIM
tSPICHM
tSPICLM
tSPI-
t S P IC H M
tHDSM
tSPICLK
t S P I TD M
SC LK
(CPO L = 0)
(O UTPUT )
C LM
SCL K
(CPOL = 1)
(O UTPUT )
tDDSPID
MOSI
( OUT PUT )
tHDSPID
MSB
CPHA=1
t S S PI D
MISO
(INPUT)
LSB
tHSPID
tSSPID
MSB
VALID
LSB
VALID
tD D S P I D
MO SI
( OU TPUT)
CPHA=0
MISO
(IN PUT )
tH D S P I D
MSB
tSSPID
tHSPID
L SB
tHSPID
MSB
VAL ID
LSB
VALID
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
REV. PrC
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Serial Peripheral Interface (SPI) Port—Slave Timing
Table 23 and Figure 20 describe SPI port slave operations.
Table 23. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Description
Min
Max
Timing Requirements
tSPICHS
Serial clock high period
tSPICLS
Serial clock low period
tSPICLK
Serial clock period
Last SPICLK edge to SPISS not asserted
tHDS
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS assertion to first SCLK edge
tSSPID
Data input valid to SCLK edge (data input setup)
tHSPID
SCLK sampling edge to data input invalid
2tSCLK
2tSCLK
4tSCLK
2tSCLK
2tSCLK
2tSCLK
1.6
1.6
Switching Characteristics
tDSOE
SPISS assertion to data out active
tDSDHI
SPISS deassertion to data high impedance
tDDSPID
SCLK edge to data out valid (data out delay)
tHDSPID
SCLK edge to data out invalid (data out hold)
0
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
6
6
5
5
ns
ns
ns
ns
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCLK
(CPOL = 0)
(INPUT)
tSDSCI
SCLK
(CPOL = 1)
(INPUT)
tDSOE
tDDS-
tHDSPID
tDDSPID
tDSDHI
PID
MISO
(OUTPUT)
MSB
CPHA=1
tSSPID
MOSI
(INPUT)
tHSPID
LSB
VALID
tDDSPID
tDSDHI
LSB
MSB
CPHA=0
MOSI
(INPUT)
tSSPID
tHSPID
MSB
VALID
tDSOE
MISO
(OUTPUT)
LSB
tSSPID
MSB
VALID
tHSPID
LSB
VALID
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
36
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Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
Figure 21 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in
Figure 21 there is some latency between the generation internal UART interrupts and the external data operations. These
latencies are negligible at the data transmission rates for the UART.
SCL K
(SAMPLE
CL OCK)
RXD
DA TA( 5–8)
ST OP
RECEIVE
INT ER NAL
UART RECEIVE
IN TERRUPT
UART R ECEIVE BIT SET BY DAT A
STO P; CLEARED BY F IFO R EAD
START
T XD
TRA NSMIT
DA TA( 5–8)
STO P (1–2)
AS DA TA
WRI TEN TO
BUF FER
INTERN AL
U ART T RANSMIT
INT ER RUPT
UART TRANSMIT B IT SET BY PROG RAM;
CLEAR ED B Y WRIT E T O T RANSMIT
Figure 21. UART Port—Receive and Transmit Timing
REV. PrC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
37
PRELIMINARY TECHNICAL DATA
ADSP-21535
For current information contact Analog Devices at 800-262-5643
June 2002
JTAG Test And Emulation Port Timing
Table 24 and Figure 22 describe JTAG port operations.
Table 24. JTAG Port Timing
Parameter
Description
Min
Timing Parameters
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
tSSYS
tHSYS
System Inputs Hold After TCK Low1
tTRSTW
TRST Pulsewidth2
4
Switching Characteristics
TDO Delay from TCK Low
tDTDO
tDSYS
System Outputs Delay After TCK Low3
0
Max
Unit
4
4
4
5
ns
ns
ns
ns
ns
ns
4
5
ns
ns
20
1
System Inputs=DATA31-0, ADDR25-2, ARDY, TMR2-0, PF15-0, RSCLK0, RFS0, DR0, TSCLK0, TFS0, RSCLK1, RFS1, DR1, TSCLK1, TFS1,
MOSI0, MISO0, SCK0, MOSI1, MISO1, SCK1, RX0, RX1, TSB_CLK, XVER_DATA, DPLS, DMNS, NMI, RESET, BYPASS, BMODE2-0,
PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_SERR, PCI_RST,
PCI_GNT, PCI_IDSEL, PCI_LOCK, PCI_CLK, PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD.
2
50 MHz max.
3
System Outputs=DATA31-0, ADDR25-2, ABE/SDQM3-0, AOE, ARE, AWE, CLKOUT/SCLK1, SCLK0, SCKE, SA10, SRAS, SCAS, SWE, SMS3-0,
TMR2-0, PF15-0, RSCLK0, RFS0, TSCLK0, TFS0, DT0, RSCLK1, RFS1, TSCLK1, TFS1, DT1, MOSI0, MISO0, SCK0, MOSI1, MISO1, SCK1,
TX0, TX1, TXDPLS, TXDMNS, TXEN, SUSPEND, DEEPSLEEP, PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY,
PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA, EMU.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 22. JTAG Port Timing
38
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrC
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
June 2002
Power Dissipation
Total power dissipation has two components, one due to
internal circuitry (PINT) and one due to the switching of
external output drivers (P ). Table 25 shows the power
EXT
ADSP-21535
dissipation for internal circuitry. Internal power dissipation
is dependent on the instruction execution sequence and the
data operands involved. Table 26 lists the conditions under
which the values in Table 25 are obtained.
Table 25. Internal Power Dissipation
1
Parameter
Test Conditions
Typical (VDDINT =1.5 V)1
Typical (VDDINT =1.0 V)1
Units
IDDHIGH
IDDTYP
IDDLOW
IDDSYS
IDDEFR
IDDACTIVE
IDDSLEEP
IDDDEEPSLEEP
tCCLKMIN, 25ºC
tCCLKMIN, 25ºC
tCCLKMIN, 25ºC
tCCLKMIN, 25ºC
tCCLKMIN, 25ºC
25ºC
25ºC
25ºC
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
Typical IDD data is specified for nominal VDDINT and typical process parameters.Maximum IDD is within TBD% of typical values.
Table 26. Internal Power Dissipation Conditions
Parameter
1
IDDHIGH
IDDTYP1
IDDLOW1
IDDSYS2
IDDEFR3
IDDACTIVE
IDDSLEEP
IDDDEEPSLEEP
Mode
PLL
CCLK
SCLK
Activity
Full-On
Full-On
Full-On
Full-On
Full-On
Active
Sleep
Deep-Sleep
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled/Bypassed
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
TBD
TBD
TBD
TBD
Algorithm-dependent
TBD
TBD
TBD
1
TBD instruction mix.
TBD instruction mix and system DMA every cycle.
3
Implementation of Enhanced Full Rate (EFR) GSM algorithm, instruction and data fetch from L1/L2 memories and cache.
2
The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on
• The number of output pins that switch during each cycle
(O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (VDDEXT)
The external component is calculated using
PEXT =O ⴛ C ⴛ VDD ⴛ f
The frequency f includes driving the load high and then back
low. For example: DATA31–0 pins can drive high and low
at a maximum rate of 1/(2 ⴛtSCLK) while in SDRAM burst
mode.
A typical power consumption can now be calculated for
these conditions by adding a typical internal power dissipation.
PTOTAL =PEXT +(IDD ⴛ VDDINT )
REV. PrC
Note that the conditions causing a worst-case PEXT differ
from those causing a worst-case P . Maximum P cannot
occur while 100% of the output pins are switching from all
ones (1s) to all zeros (0s). Note also that it is not common
for an application to have 100%,or even 50%, of the outputs
switching simultaneously.
INT
INT
Environmental Conditions
The ADSP-21535 is offered in a 260-lead PBGA package.
The ADSP-21535 is specified for a case temperature
(TCASE). To ensure that TCASE is not exceeded, an airflow
source may be used. TCASE is calculated using
TCASE =TAMB +(PD ⴛ θCA)
TCASE =Case temperature (measured on top surface of
package
PD =Power dissipation in W (this value depends upon the
specific application)
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
39
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
June 2002
SeeTable 27 for three instances of linear feet per minute of
airflow.
Table 27. Airflow
Linear Ft/Min
0
200
400
θCA (ºC/W)
TBD
TBD
TBD
ADSP-21535 260-Lead PBGA Pinout
Table 28 lists the PBGA pinout by signal name. Table 29
on page 43 lists the pinout by pin number.
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal)
SIGNAL
PIN #
ABE0/SDQM0
ABE1/SDQM1
ABE2/SDQM2
ABE3/SDQM3
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
ADDR24
ADDR25
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BMODE0
BMODE1
E02
B01
G03
H07
A06
B06
D06
C06
A05
B05
A04
C05
D05
B04
A01
C04
D04
A03
B03
A02
C03
D03
B02
C02
E03
C01
F03
D02
F02
D01
H03
G02
E01
R01
F01
G01
B14
A14
REV. PrC
ADSP-21535
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal) (Continued)
SIGNAL
PIN #
BMODE2
BYPASS
CLKIN1
CLKOUT/SCLK1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
DMNS
DPLS
DR0
DR1
DT0
DT1
EMU
GND
GND
GND
GND
GND
GND
GND
GND
B13
C12
D09
H01
N02
M03
T01
P02
N03
R02
P03
U01
U02
T02
V02
V03
R04
U03
T03
T04
U04
V04
V05
R05
T05
U05
V06
R06
U06
T06
V07
V08
U07
R07
T07
V09
D08
C09
V14
U15
R14
V17
A13
C13
H02
H08
H10
H11
J07
J08
J09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
40
PRELIMINARY TECHNICAL DATA
June 2002
For current information contact Analog Devices at 800-262-5643
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal) (Continued)
SIGNAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO0
MISO1
MOSI0
MOSI1
N/C
N/C
N/C
N/C
NMI
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
REV. PrC
ADSP-21535
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal) (Continued)
PIN #
SIGNAL
PIN #
J10
J11
J12
K02
K07
K08
K09
K10
K11
K12
L07
L08
L09
L10
L11
M07
M09
M10
T16
U18
U16
T17
A18
R03
V01
V18
B11
E17
E18
G16
F17
F18
G18
G17
H18
J18
H17
K18
H16
L18
J17
M18
K17
J16
K16
N18
P18
L17
L16
R18
T18
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0
PCI_CBE1
PCI_CBE2
PCI_CBE3
PCI_CLK
PCI_DEVSEL
PCI_FRAME
PCI_GNT
PCI_IDSEL
PCI_INTA
PCI_INTB
PCI_INTC
PCI_INTD
PCI_IRDY
PCI_LOCK
PCI_PAR
PCI_PERR
PCI_REQ
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
PF0
/SPISS0
/MSEL0
PF1
/SPISS1
/MSEL1
PF2
/SPI0SEL1
/MSEL2
PF3
/SPI1SEL1
/MSEL3
PF4
/SPI0SEL2
/MSEL4
M17
M16
N17
P17
P15
N16
R17
P16
F16
F15
E16
D17
D14
C16
C17
C18
B18
C14
B15
A15
D13
E15
A16
C15
D15
D16
D18
B16
A17
B17
U08
PF5
/SPI1SEL2
/MSEL5
PF6
/SPI0SEL3
/MSEL6
R09
R08
T08
V10
U09
T09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
41
PRELIMINARY TECHNICAL DATA
June 2002
For current information contact Analog Devices at 800-262-5643
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal) (Continued)
ADSP-21535
Table 28. 260-Lead PBGA Pin Assignment
(Alphabetically by Signal) (Continued)
SIGNAL
PIN #
SIGNAL
PIN #
PF7
/SPI1SEL3
/DF
PF8
/SPI0SEL4
/SSEL0
PF9
/SPI1SEL4
/SSEL1
PF10
/SPI0SEL5
PF11
/SPI1SEL5
PF12
/SPI0SEL6
PF13
/SPI1SEL6
PF14
/SPI0SEL7
PF15
/SPI1SEL7
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RX0
RX1
SA10
SCAS
SCK0
SCK1
SCKE
SCLK0
SLEEP
SMS0
SMS1
SMS2
SMS3
SRAS
SUSPEND
SWE
TCK
TDI
TDO
R11
B09
U13
V16
R13
U14
A07
B08
M01
L03
U17
R16
L01
K01
D12
M02
P01
N01
K03
L02
A11
J03
D10
C11
D11
TRST
TSCLK0
TSCLK1
TX0
TX1
TXDMNS
TXDPLS
TXEN
USB_CLK
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDPCIEXT
VDDPCIEXT
VDDPCIEXT
VDDPCIEXT
VDDPCIEXT
VDDPLL
VDDRTC
VSSPLL
VSSRTC
XTALI
XTALO
XVER_DATA
B12
V15
T15
A08
C08
G10
B10
C10
G07
E04
G04
G08
J01
J02
J04
K04
L04
M04
P04
F04
G11
G12
G15
H04
H09
H12
L12
M08
M11
M12
N04
N15
H15
J15
K15
L15
M15
G09
U10
A10
V11
R10
T10
A09
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
T14
R15
B07
C07
D07
A12
REV. PrC
T11
U11
V12
T12
R12
U12
V13
T13
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
42
PRELIMINARY TECHNICAL DATA
June 2002
For current information contact Analog Devices at 800-262-5643
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number)
ADSP-21535
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number) (Continued)
PIN #
SIGNAL
PIN #
SIGNAL
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
ADDR12
ADDR17
ADDR15
ADDR8
ADDR6
ADDR2
RX0
TX0
XVER_DATA
VSSPLL
SUSPEND
TMS
EMU
BMODE1
PCI_INTC
PCI_LOCK
PCI_STOP
N/C
ABE1/SDQM1
ADDR20
ADDR16
ADDR11
ADDR7
ADDR3
TMR0
RX1
RESET
TXDPLS
NMI
TRST
BMODE2
BMODE0
PCI_INTB
PCI_SERR
PCI_TRDY
PCI_IDSEL
ADDR23
ADDR21
ADDR18
ADDR13
ADDR9
ADDR5
TMR1
TX1
DPLS
TXEN
TDI
BYPASS
GND
PCI_INTA
PCI_PAR
C16
C17
C18
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
E01
E02
E03
E04
E15
E16
E17
E18
F01
F02
F03
F04
F15
F16
F17
F18
G01
G02
G03
G04
G07
G08
G09
G10
G11
G12
G15
G16
PCI_DEVSEL
PCI_FRAME
PCI_GNT
AMS1
ADDR25
ADDR19
ADDR14
ADDR10
ADDR4
TMR2
DMNS
CLKIN1
TCK
TDO
SLEEP
PCI_INTD
PCI_CLK
PCI_PERR
PCI_REQ
PCI_CBE3
PCI_RST
AOE
ABE0/SDQM0
ADDR22
VDDEXT
PCI_IRDY
PCI_CBE2
PCI_AD0
PCI_AD1
ARE
AMS0
ADDR24
VDDINT
PCI_CBE1
PCI_CBE0
PCI_AD3
PCI_AD4
AWE
AMS3
ABE2/SDQM2
VDDEXT
USB_CLK
VDDEXT
VDDPLL
TXDMNS
VDDINT
VDDINT
VDDINT
PCI_AD2
PCI_AD6
PCI_AD5
REV. PrC
G17
G18
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
43
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
June 2002
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number) (Continued)
ADSP-21535
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number) (Continued)
PIN #
SIGNAL
PIN #
SIGNAL
H01
H02
H03
H04
H07
H08
H09
H10
H11
H12
H15
H16
H17
H18
J01
J02
J03
J04
J07
J08
J09
J10
J11
J12
J15
J16
J17
J18
K01
K02
K03
K04
K07
K08
K09
K10
K11
K12
K15
K16
K17
K18
L01
L02
L03
L04
L07
CLKOUT/SCLK1
GND
AMS2
VDDINT
ABE3/SDQM3
GND
VDDINT
GND
GND
VDDINT
VDDPCIEXT
PCI_AD11
PCI_AD9
PCI_AD7
VDDEXT
VDDEXT
SWE
VDDEXT
GND
GND
GND
GND
GND
GND
VDDPCIEXT
PCI_AD16
PCI_AD13
PCI_AD8
SCLK0
GND
SMS3
VDDEXT
GND
GND
GND
GND
GND
GND
VDDPCIEXT
PCI_AD17
PCI_AD15
PCI_AD10
SCKE
SRAS
SCAS
VDDEXT
GND
L12
L15
L16
L17
L18
M01
M02
M03
M04
M07
M08
M09
M10
M11
M12
M15
M16
M17
M18
N01
N02
N03
N04
N15
N16
N17
N18
P01
P02
P03
P04
P15
P16
P17
P18
R01
R02
R03
R04
R05
R06
R07
R08
VDDINT
VDDPCIEXT
PCI_AD21
PCI_AD20
PCI_AD12
SA10
SMS0
DATA1
VDDEXT
GND
VDDINT
GND
GND
VDDINT
VDDINT
VDDPCIEXT
PCI_AD25
PCI_AD24
PCI_AD14
SMS2
DATA0
DATA4
VDDINT
VDDINT
PCI_AD29
PCI_AD26
PCI_AD18
SMS1
DATA3
DATA6
VDDEXT
PCI_AD28
PCI_AD31
PCI_AD27
PCI_AD19
ARDY
DATA5
N/C
DATA12
DATA19
DATA23
DATA29
PF1
/SPISS1
/MSEL1
R09
L08
L09
L10
L11
GND
GND
GND
GND
PF5
/SPI1SEL2
/MSEL5
XTALI
REV. PrC
R10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
44
PRELIMINARY TECHNICAL DATA
June 2002
For current information contact Analog Devices at 800-262-5643
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number) (Continued)
ADSP-21535
Table 29. 260-Lead PBGA Pin Assignment
(Numerically by Pin Number) (Continued)
PIN #
SIGNAL
PIN #
SIGNAL
R11
PF7
/SPI1SEL3
/DF
PF12
/SPI0SEL6
RSCLK0
DT0
TFS1
SCK1
PCI_AD30
PCI_AD22
DATA2
DATA9
DATA14
DATA15
DATA20
DATA25
DATA30
PF2
/SPI0SEL1
/MSEL2
PF6
/SPI0SEL3
/MSEL6
XTALO
PF8
/SPI0SEL4
/SSEL0
PF11
/SPI1SEL5
PF15
/SPI1SEL7
TFS0
TSCLK1
MISO0
MOSI1
PCI_AD23
DATA7
DATA8
DATA13
DATA16
DATA21
DATA24
DATA28
PF0
/SPISS0
/MSEL0
U11
PF9
/SPI1SEL4
/SSEL1
PF13
/SPI1SEL6
RFS0
RSCLK1
DR1
MOSI0
SCK0
MISO1
N/C
DATA10
DATA11
DATA17
DATA18
DATA22
DATA26
DATA27
DATA31
PF3
/SPI1SEL1
/MSEL3
VSSRTC
PF10
/SPI0SEL5
PF14
/SPI0SEL7
DR0
TSCLK0
RFS1
DT1
N/C
R12
R13
R14
R15
R16
R17
R18
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
REV. PrC
U12
U13
U14
U15
U16
U17
U18
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
PF4
/SPI0SEL2
/MSEL4
VDDRTC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
45
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
June 2002
ADSP-21535
OUTLINE DIMENSIONS
Dimensions in Figure 23 are shown in millimeters.
19.05
19.00 SQ
18.95
18
16 14 12 10 8
6 4
2
17 15 13 11 9
7
5
3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
BALL A1
INDICATOR
17.05
16.95 SQ
16.85
17.00
BSC
SQ
1.00
BSC
TOP VIEW
1.00 BSC
BALL PITCH
1.00 BSC
DETAIL A
BOTTOM VIEW
2.50
MAX
NOTES
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. THE ACTUAL POSITION OF THE BALL GRID
IS WITHIN 0.25 OF THE IDEAL POSITION
RELATIVE TO THE PACKAGE EDGES.
3. THE ACTUAL POSITION OF EACH BALL IS
WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE
TO THE BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL.
1.22
MAX
0.65
0.55
0.45
0.63
0.40
0.55
0.50
0.45
BALL DIAMETER
0.20
MAX, TYP
SEATING
PLANE
DETAIL A
Figure 23. 260-Lead Metric Plastic Ball Grid Array (PBGA) (B-260)
ORDERING GUIDE
Part Number
Case Temperature Range
Instruction Rate
Operating Voltage
ADSP-21535PKB-300
0ºC to 85ºC
300 MHz
ADSP-21535PBB-200
-40ºC to +105ºC
200 MHz
0.9 V to 1.5 V internal,
3.3 V I/O
0.9 V to 1.5 V internal,
3.3 V I/O
REV. PrC
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
46