EDI8F32259C 256Kx32 SRAM Module 256Kx32 Static RAM CMOS, High Speed Module Features 256Kx32 bit CMOS Static Random Access Memory • Access Times BiCMOS: 10 and 12ns CMOS: 15, 20, 25, and 35ns • Individual Byte Selects • Fully Static, No Clocks • TTL Compatible I/O High Density Package with JEDEC Standard Pinouts • 72 Pin SIMM No. 175 (Angle) • 72 Pin ZIP No. 176 • 72 Pin SIMM, No. 354 (Straight) Single +5V (±10%) Supply Operation Pin Configurations and Block Diagram NC PD4 PD1 DQØ DQ1 DQ2 DQ3 VCC A7 A8 A9 DQ4 DQ5 DQ6 DQ7 W A14 EØ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 E2 A16 VSS DQ16 DQ17 DQ18 DQ19 A10 A11 A12 A13 DQ20 DQ21 DQ22 DQ23 VSS NC NC 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 NC PD3 VSS PD2 DQ8 DQ9 DQ10 DQ11 AØ A1 A2 DQ12 DQ13 DQ14 DQ15 VSS A15 E1 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 E3 A17 G DQ24 DQ25 DQ26 DQ27 A3 A4 A5 VCC A6 DQ28 DQ29 DQ30 DQ31 NC NC The EDI8F32259C is a high speed 8 megabit Static RAM module organized as 256K words by 32 bits. This module is constructed from eight 256Kx4 Static RAMs in SOJ packages on an epoxy laminate (FR4) board. Four chip enables (EØ-E3) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The EDI8F32259C is offered in 72 pin ZIP/SIMM package which enables eight megabits of memory to be placed in less than 1.3 square inches of board space. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. The ZIP and SIMM modules contain four PD (Presence Detect) pins which are used to identify module memory density in applications where alternate modules can be interchanged. Pin Names 72 Pin PD 1,2 - VSS PD 3,4 - Open AØ-A17 EØ-E3 W, G DQØ-DQ31 VCC VSS Address Inputs Chip Enables Write Enables Output Enable Common Data Input/Output Power (+5V±10%) Ground W G 4 DQØ-DQ3 4 DQ4-DQ7 EØ 4 DQ8-DQ11 4 DQ12-DQ15 DQ16-DQ19 4 DQ20-DQ23 DQ24-DQ27 4 DQ28-DQ31 E1 4 E2 4 E3 Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 • Electronic Designs Europe Ltd. • Shelley House, The Avenue • Lightwater, Surrey GU18 5RF United Kingdom • 01276 472637 • FAX: 01276 473748 1 EDI8F32259C Rev. 1 12/97 ECO #9619 Absolute Maximum Ratings* Recommended DC Operating Conditions Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial. Industrial Storage Temperature, Plastic Power Dissipation Output Current. Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL -0.5V to 7.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C 7.5 Watt 20 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Min 4.5 0 2.2 -0.3 Typ Max Units 5.0 5.5 V 0 0 V -- VCC+0.3V V -0.8 V AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V 1TTL, CL = 30pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC Electrical Characteristics Parameter Sym Conditions Min Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current CMOS Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ICC1 ICC2 ICC3 W, E = VIL, II/O = 0mA, Min Cycle E ≥ VIH, VIN ≤ VIL or VIN ≥ VIH E ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA --2.4 — ILI ILO VOH VOL Max 10-12 1360 480 80 Max 15ns 1280 240 80 Max 20 1440 200 40 ±80 ±80 ±80 ±20 ±20 ±20 — — — 0.4 0.4 0.4 Max Units 25-35 ns 1280 mA 200 mA 40 mA ±80 µA ±20 µA — V 0.4 V *Typical: TA = 25°C, VCC = 5.0V Capacitance Truth Table E H L L L W X H L H G X L X H Mode Standby Read Write Output Deselect Output HIGH Z DOUT DIN HIGH Z Power ICC3 ICC1 ICC1 ICC1 (f=1.0MHz, VIN=VCC or VSS) Parameter Address Lines Data Lines Chip Enable Line Write Control Line Sym CI CD/Q CC CN These parameters are sampled, not 100% tested. EDI8F32259C 256Kx32 SRAM Module 2 EDI8F32259C Rev. 1 12/97 ECO #9619 Max 60 20 20 60 Unit pF pF pF pF EDI8F32259C 256Kx32 SRAM Module AC Characteristics Read Cycle Parameter Read Cycle Time Address Access Time Chip Enable Access Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1) Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ Note 1: Parameter guaranteed, but not tested. 10ns* Min Max 10 10 10 3 5 3 5 0 4 12ns* Min Max 12 12 12 3 6 3 5 0 4 Min 15 15ns Max 15 15 3 8 3 8 0 5 *BICMOS Read Cycle 1 - W High, G, E Low TAVAV ADDRESS 1 A TAVQV Q ADDRESS 2 TAVQX DATA 1 DATA 2 Read Cycle 2 - W High TAVAV A E TAVQV TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q 3 EDI8F32259C Rev. 1 12/97 ECO #9619 Units ns ns ns ns ns ns ns ns ns AC Characteristics Read Cycle Parameter Read Cycle Time Address Access Time Chip Enable Access Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ 20ns Min Max 20 20 20 3 10 3 13 0 8 25ns Min Max 25 25 25 3 12 3 15 0 10 Min 35 35ns Max 35 35 3 15 3 20 0 12 Note 1: Parameter guaranteed, but not tested. Read Cycle 1 - W High: G, E Low Read Cycle 1 W High; G, E Low TAVAV ADDRESS 1 A ADDRESS 2 TAVQV Q TAVQX DATA 1 DATA 2 Read Cycle 2 - W High Read Cycle 2 W High TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q EDI8F32259C 256Kx32 SRAM Module 4 EDI8F32259C Rev. 1 12/97 ECO #9619 Units ns ns ns ns ns ns ns ns ns EDI8F32259C 256Kx32 SRAM Module AC Characteristics Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Note 1: Parameter guaranteed, but not tested. Symbol JEDEC Alt. TAVAV TWC TELWH TCW TWLEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TELEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ 10ns* Min Max 10 7 7 0 0 7 7 7 7 0 0 3 3 0 5 5 5 2 12ns* Min Max 12 8 8 0 0 8 8 8 8 0 0 3 3 0 6 6 6 2 Min 15 12 10 0 0 10 10 10 10 0 0 3 3 0 7 7 2 15ns Max 20ns Min Max 20 15 15 0 0 15 15 15 15 0 0 3 3 0 10 12 12 3 25ns Min 25 20 20 0 0 20 20 20 20 0 0 3 3 0 15 15 3 35ns Min 35 30 30 0 0 30 30 30 30 0 0 3 3 0 20 20 3 9 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *BICMOS AC Characteristics Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. TAVAV TWC TELWH TCW TWLEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TELEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ Note 1: Parameter guaranteed, but not tested. 5 EDI8F32259C Rev. 1 12/97 ECO #9619 Max 12 Max 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle 1 - W Controlled TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TWHDX TDVWH D DATA VALID TWLQZ HIGH Z Q TWHQX Write Cycle 2 - E Controlled TAVAV A TAVEL TELEH E TEHAX TAVEH TWLEH W TDVEH DATA VALID D Q HIGH Z EDI8F32259C 256Kx32 SRAM Module 6 EDI8F32259C Rev. 1 12/97 ECO #9619 TEHDX EDI8F32259C 256Kx32 SRAM Module Ordering Information Part Number BICMOS EDI8G32259B10MNC EDI8G32259B12MNC CMOS EDI8F32259C15MNC EDI8F32259C20MNC EDI8F32259C25MNC EDI8F32259C35MNC Part Number BICMOS EDI8G32259B10MZC EDI8G32259B12MZC CMOS EDI8F32259C15MZC EDI8F32259C20MZC EDI8F32259C25MZC EDI8F32259C35MZC Speed (ns) Package No. 10 12 176 176 15 20 25 35 176 176 176 176 Speed (ns) Package No. 10 12 175 175 15 20 25 35 175 175 175 175 Part Number BICMOS EDI8G32259B10MMC EDI8G32259B12MMC CMOS EDI8F32259C15MMC EDI8F32259C20MMC EDI8F32259C25MMC EDI8F32259C35MMC Speed (ns) Package No. 10 354 12 354 15 20 25 35 354 354 354 354 Note: For Gold SIMM, Change from EDI8F to EDI 8G. Package Description Package No. 175 72 Pin ZIP 3.865 MAX. .360 MAX. .050 .590 MAX. .050 P1 .250 TYP. .020 .100 TYP. .052 TYP. 7 EDI8F32259C Rev. 1 12/97 ECO #9619 .175 .125 .100 TYP. Package No. 176 72 Pin SIMM Angled 4.255 MAX. 3.984 1.992 .400 .225 MIN. .680 MAX. .250 P1 .250 TYP. .062 R. 2.045 .062 R. .050 TYP. .125 MIN. 3.750 .360 MAX. Package No. 354 72 Pin SIMM Straight .125 DIA (2x) 4.255 Max 3.984 R.# J4 .250 J2 J1 P1 164 .400 .050 TYP. .250 TYP. 3.750 2.045 .360 MAX. .600 MAX. 1.992 .125 MIN. .062 R. (2x) Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581 USA • 508-366-5151 • FAX 508-836-4850 • Electronic Designs Europe Ltd. • Shelley House, The Avenue • Lightwater, Surrey GU18 5RF United Kingdom • 01276 472637 • FAX: 01276 473748 http://www.electronic-designs.com Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301 256Kx32 SRAM Module 8 EDI8F32259C Rev. 1 12/97 ECO #9619 EDI8F32259C