ETC HYM72V16M656LT6-P

16Mx64 bits
PC100 SDRAM SO DIMM
based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V16M656T6 Series
DESCRIPTION
The HYM72V16M656T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit
Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy
printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V16M656T6 -Series are gold plated socket type Dual In-line Memory Modules suitable for easy interchange
and addition of 128M bytes memory. All inputs and outputs are synchronized with the rising edge of the clock input. The
data paths are internally pipelined to achieve very high bandwidth.
FEATURES
•
•
•
•
•
•
•
•
1.00(31.75mm) PCB Height
One Row of SDRAMs on SO DIMM
144-Pin Unbuffered SO DIMM
Serial Presence Detect with Serial E2PROM
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
• All inputs and outputs referenced to positive edge
of system clock
• Internal four banks operation
• Programmable Burst Length and Burst Type
- 1,2,4,8 and Full page for Sequential Burst
- 1,2,4 and 8 for Interleave Burst
• Programmable /CAS latency ; 2,3 clocks
• Data mask function by DQM
ORDERING INFORMATION
Part No.
Clock
Frequency
HYM72V16M656T6-8
125MHz
HYM72V16M656T6-P
100MHz
HYM72V16M656T6-S
100MHz
HYM72V16M656LT6-8
125MHz
HYM72V16M656LT6-P
100MHz
HYM72V16M656LT6-S
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
TSOP-II
Gold
Normal
4 Banks
8K
Low Power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.0/Dec.99
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CK0, CK1
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/S0
Chip Select
Enables or disables all inputs except CK, CKE and DQM
BA0, BA1
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A0 ~ A12
Address
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ63
Data Input/Output
Multiplexed data input / output pin
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~2
SPD Address Input
Serial Presence Detect Address Input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
No connection
Rev. 1.0/Dec.99
2
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
1
VSS
3
DQ0
5
7
FRONT SIDE
BACK SIDE
NAME
PIN NO.
NAME
PIN NO.
2
VSS
71
NC
72
NC
4
DQ32
73
NC
74
*CK1
DQ1
6
DQ33
75
VSS
76
VSS
DQ2
8
DQ34
77
NC
78
NC
9
DQ3
10
DQ35
79
NC
80
NC
11
VCC
12
VCC
81
VCC
82
VCC
13
DQ4
14
DQ36
83
DQ16
84
DQ48
15
DQ5
16
DQ37
85
DQ17
86
DQ49
17
DQ6
18
DQ38
87
DQ18
88
DQ50
19
DQ7
20
DQ39
89
DQ19
90
DQ51
21
VSS
22
VSS
91
VSS
92
VSS
23
DQM0
24
DQM4
93
DQ20
94
DQ52
25
DQM1
26
DQM5
95
DQ21
96
DQ53
27
VCC
28
VCC
97
DQ22
98
DQ54
29
A0
30
A3
99
DQ23
100
DQ55
31
A1
32
A4
101
VCC
102
VCC
33
A2
34
A5
103
A6
104
A7
35
VSS
36
VSS
105
A8
106
BA0
37
DQ8
38
DQ40
107
VSS
108
VSS
39
DQ9
40
DQ41
109
A9
110
BA1
41
DQ10
42
DQ42
111
A10/AP
112
A11
43
DQ11
44
DQ43
113
VCC
114
VCC
45
VCC
46
VCC
115
DQM2
116
DQM6
47
DQ12
48
DQ44
117
DQM3
118
DQM7
49
DQ13
50
DQ45
119
VSS
120
VSS
51
DQ14
52
DQ46
121
DQ24
122
DQ56
53
DQ15
54
DQ47
123
DQ25
124
DQ57
55
VSS
56
VSS
125
DQ26
126
DQ58
57
NC
58
NC
127
DQ27
128
DQ59
59
NC
60
NC
129
VCC
130
VCC
131
DQ28
132
DQ60
DQ61
Voltage Key
NAME
133
DQ29
134
61
CK0
62
CKE0
135
DQ30
136
DQ62
63
VCC
64
VCC
137
DQ31
138
DQ63
65
/RAS
66
/CAS
139
VSS
140
VSS
67
/WE
68
NC
141
SDA
142
SCL
69
/S0
70
A12
143
VCC
144
VCC
Note : * CK1 are connected with termination R/C (Refer to the Block Diagram)
Rev. 1.0/Dec.99
3
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
2. The padding capacitance of termination R/C for CK1 is 10pF
Rev. 1.0/Dec.99
4
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
NOTE
-8
-P
-S
-8
-P
-S
BYTE0
# of Bytes Written into Serial Memory at Module
Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
SDRAM
04h
BYTE3
# of Row Addresses on This Assembly
13
0Dh
BYTE4
# of Column Addresses on This Assembly
9
09h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
BYTE9
SDRAM Cycle Time @/CAS Latency=3
8ns
10ns
10ns
80h
A0h
A0h
BYTE10
Access Time from Clock @/CAS Latency=3
6ns
6ns
6ns
60h
60h
60h
BYTE11
DIMM Configuration Type
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
BYTE14
Error Checking SDRAM Width
BYTE15
Minimum Clock Delay Back to Back Random Column
Address
BYTE16
Burst Lenth Supported
BYTE17
# of Banks on Each SDRAM Device
BYTE18
SDRAM Device Attributes, /CAS Lataency
BYTE19
SDRAM Device Attributes, /CS Lataency
BYTE20
SDRAM Device Attributes, /WE Lataency
BYTE21
SDRAM Module Attributes
LVTTL
1
01h
None
00h
7.8125us
/ Self Refresh Supported
82h
x16
10h
None
00h
tCCD = 1 CLK
01h
1,2,4,8,Full Page
8Fh
4 Banks
04h
/CAS Latency=2,3
06h
/CS Latency=0
01h
/WE Latency=0
01h
Neither Buffered nor Registered
00h
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
0Eh
2
BYTE22
SDRAM Device Attributes, General
BYTE23
SDRAM Cycle Time @/CAS Latency=2
12ns
10ns
12ns
C0h
A0h
C0h
BYTE24
Access Time from Clock @/CAS Latency=2
6ns
6ns
6ns
60h
60h
60h
BYTE25
SDRAM Cycle Time @/CAS Latency=1
-
-
-
00h
00h
00h
BYTE26
Access Time from Clock @/CAS Latency=1
-
-
-
00h
00h
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
14h
14h
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
16ns
20ns
20ns
10h
14h
14h
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
20ns
20ns
14h
14h
14h
BYTE30
Minimum /RAS Pulse Width (tRAS)
48ns
50ns
50ns
30h
32h
32h
BYTE31
Module Bank Density
BYTE32
Command and Address Signal Input Setup Time
2ns
2ns
2ns
20h
20h
20h
BYTE33
Command and Address Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE34
Data Signal Input Setup Time
2ns
2ns
2ns
20h
20h
20h
BYTE35
Data Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE36
~61
Superset Information (may be used in future)
BYTE62
SPD Revision
BYTE63
Checksum for Byte 0~62
BYTE64
Manufacturer JEDEC ID Code
BYTE65
~71
....Manufacturer JEDEC ID Code
BYTE72
Manufacturing Location
Rev. 1.0/Dec.99
128MB
20h
-
00h
Intel SPD 1.2A
-
12h
07h
0Dh
Hyundai JEDED ID
ADh
Unused
FFh
HEI (Korea)
HEA (United States)
HEU (Europe)
01h
02h
03h
3, 8
2Dh
5
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
Continued
BYTE
NUMBER
FUNCTION
DESCRIPTION
BYTE73
Manufacturer’s Part Number (Component)
BYTE74
Manufacturer’s Part Number (128Mb based)
BYTE75
Manufacturer’s Part Number (Voltage Interface)
BYTE76
Manufacturer’s Part Number (Memory Width)
BYTE77
BYTE78
BYTE79
Manufacturer’s Part Number (Refresh, SDRAM Bank)
BYTE80
Manufacturer’s Part Number (Generation)
BYTE81
Manufacturer’s Part Number (Package Type)
BYTE82
Manufacturer’s Part Number (Component Configuration)
BYTE83
Manufacturer’s Part Number (Hyphent)
BYTE84
Manufacturer’s Part Number (Min. Cycle Time)
BYTE85
~90
Manufacturer’s Part Number
BYTE91
BYTE92
BYTE93
Manufacturing Date
BYTE94
....Manufacturing Date
BYTE95
~98
BYTE99
~125
FUNCTION
-8
-P
VALUE
-S
-8
-P
NOTE
-S
7 (SDRAM)
37h
4, 5
1
31h
4, 5
V (3.3V, LVTTL)
56h
4, 5
8
38h
4, 5
Manufacturer’s Part Number (Data Width)
6
36h
4, 5
....Manufacturer’s Part Number (Data Width)
5
35h
4, 5
5 (4K Refresh, 4Banks)
35h
4, 5
A
41h
4, 5
8
T
54h
4, 5
16 (x16 based)
58h
4, 5
- (Hyphen)
2Dh
4, 5
P
S
38h
50h
53h
4, 5
Blanks
20h
4, 5
Revision Code (for Component)
Process Code
-
4, 6
....Revision Code (for PCB)
Process Code
-
4, 6
Work Week
-
3, 6
Year
-
3, 6
Serial Number
-
6
None
00h
Assembly Serial Number
Manufacturer Specific Data (may be used in future)
BYTE126
System Frequency Support
BYTE127
Intel Specification Details for 100MHz Support
BYTE128
~256
Unused Storage Locations
100MHz
Refer to Note7
-
64h
A7h
A7h
7, 8
A5h
7, 8
00h
Note :
1. The bank address is excluded
2. 1, 2, 4, 8 for Interleave Burst Type
3. BCD adopted
4. ASCII adopted
5. Basically HYUNDAI writes Part No. except for H
‘ YM’in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90
6. Not fixed but dependent
7. CK0, CK2 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to Intel SPD Specification 1.2A
9. In the case of L-Part, character L‘ ’will be added between byte 80 and byte 81
Rev. 1.0/Dec.99
6
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to V SS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1
Input High voltage
VIH
2.0
3.0
VDDQ + 0.3
V
1,2
Input Low voltage
VIL
-0.3
0
0.8
V
1,3
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 1.0/Dec.99
7
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
CAPACITANCE (TA=25°C, f=1MHz)
-8/P/S
Parameter
Pin
Input Capacitance
Data Input / Output Capacitance
Symbol
Unit
Min
Max
CK0, CK1
CI1
15
30
pF
CKE0
CI2
20
35
pF
/S0, /S1
CI3
15
35
pF
A0~12, BA0, BA1
CI4
30
60
pF
/RAS, /CAS, /WE
CI5
30
60
pF
DQM0~DQM7
CI 6
5
25
pF
DQ0 ~ DQ63
CI/O
5
20
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
DC Output Load Circuit
Rev. 1.0/Dec.99
50pF
AC Output Load Circuit
8
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-4
4
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under V IN =0V
2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Speed
Parameter
Operating Current
Symbol
IDD1
Test Condition
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
-8
-P
-S
400
400
400
CKE ≤ VIL(max), tCK = min
4
CKE ≤ VIL(max), tCK = ∞
4
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
80
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
16
IDD3P
CKE ≤ VIL(max), tCK = min
12
IDD3PS
CKE ≤ VIL(max), tCK = ∞
12
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
100
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
60
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Precharge Standby Current IDD2P
in Power Down Mode
IDD2PS
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Unit
Note
mA
1
mA
mA
mA
mA
CL=3
480
400
400
CL=2
440
480
480
mA
1
720
mA
2
8
mA
3
4
uA
4
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM72V16M656T6-8/P/S
4. HYM72V16M656LT6-/8/P/S
Rev. 1.0/Dec.99
9
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-8
Parameter
CAS Latency = 3
tCK3
Max
8
Min
Max
10
1000
CAS Latency = 2
-S
Unit
Min
System Clock
Cycle Time
-P
Symbol
Min
10
1000
ns
1000
tCK2
10
Clock High Pulse Width
tCHW
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
3
-
3
-
3
-
ns
1
CAS Latency = 3
tAC3
-
6
-
6
-
6
ns
CAS Latency = 2
tAC2
-
6
-
6
-
6
ns
Data-Out Hold Time
tOH
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
ns
CAS Latency = 3
tOHZ3
3
6
3
6
3
6
ns
CAS Latency = 2
tOHZ2
3
6
3
6
3
6
ns
Access Time
From Clock
CLK to Data
Output in High-Z
Time
10
Note
Max
12
ns
2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.0/Dec.99
10
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
AC CHARACTERISTICS II
-8
Parameter
-P
-S
Symbol
Unit
Min
Max
Min
Max
Min
Max
Operation
tRC
68
-
70
-
70
-
ns
Auto Refresh
tRRC
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
20
-
20
-
20
-
ns
RAS Active Time
tRAS
48
100K
50
100K
50
100K
ns
RAS Precharge Time
tRP
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
16
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
1
-
1
-
1
-
CLK
Data-In to Active Command
tDAL
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
ms
Note
RAS Cycle Time
Precharge to Data
Output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.0/Dec.99
11
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
DEVICE OPERATING OPTION TABLE
HYM72V16M656T6(L)T-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
HYM72V16M656(L)T6-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
HYM72V16M656(L)T6-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
Rev. 1.0/Dec.99
12
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
Note
V
L
CA
Read with Autoprecharge
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Precharge selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Entry
H
L
L
L
X
H
X
Exit
L
H
H
L
H
H
L
X
L
V
X
V
X
H
X
X
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
X
X
Self Refresh1
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 1.0/Dec.99
13
PC100 SDRAM SO DIMM
HYM72V16M656T6 Series
PACKAGE DEMENSION
Rev. 1.0/Dec.99
14