ETC IP113M

IP113M
Managed 10/100Base-TX / FX Media Converter
1. Feature
A 10/100BASE-TX/ 100BASE-FX converter
with a SMI port for management
Built in a 10/100BASE-TX transceiver
Built in a PHY for 100BASE-FX
Built in a 2-port switch
– Pass all packets without address and CRC
check (optional)
– Supports modified cut-through frame
forwarding for low latency
– Supports pure converter mode data
forwarding for extreme low latency
– Supports flow control for full and half duplex
operation
– Bandwidth control
– Forward 1600 bytes packet for
management
– Optional forward fragments
Built in 128Kb RAM for data buffer
Supports 3.3v I/O tolerance SMI (MDC, MDIO)
and MII registers for management
– Configure local and remote IP113M through
local SMI
– Monitor local and remote IP113M through
local SMI
– Configure/ monitor TP port support
(auto-negotiation or force 10M/100M,
full/half)
– Configure/ monitor flow control, bandwidth
– Supports loop back test (In-band or
out-band, auto or program)
– The maintenance frame is compatible to
TS-1000 standard (the Telecommunication
Technology Committee, TTC)
Supports Statistic Counters
Supports auto MDI-MDIX function
Supports link fault pass through function
Supports far end fault function
LED display for link/activity, full/half, 10/100
Built in a watchdog timer to monitor internal
switch error
Supports EEPROM Configuration
0.25-um CMOS technology
Single 2.5v power supply48-pin LQFP
package
1/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
preliminary, Specification subject to change without notice.
2. General Description
IP113M can be a 10/100BASE-TX to 100BASE-FX
converter or a 100BASE-FX to 100BASE-FX repeater
with an SMI port for management. It consists of a
2-port switch controller, a fast Ethernet transceiver
and a PHY for 100BASE-FX. The transceivers in
IP113M are designed in DSP approach with advance
0.25um technology; this results in high noise immunity
and robust performance.
Besides store and forward mode, IP113M supports
modified cut through mode and pure converter mode
for low latency data forwarding. IP113M can forward
packets up to 1600 bytes to meet requirement of extra
long packets.
IP113M supports remote management function.
Besides remote monitor and loop back test function
defined in TS-1000, IP113M supports remote access
functions. Local IP113M can access the MII register of
remote IP113M by programming local IP113M’s MII
registers via SMI. IP113M implements the
management function using the maintenance frame
defined in TS-1000.
IP113M supports IEEE802.3x, collision base
backpressure, and various LED functions, etc.
These functions can be configured to fit the different
requirements by feeding operation parameters via
EEPROM interface or pull up/down resistors on
specified pins.
IP113M-DS-R02
May. 19, 2003
IP113M
3. Block Diagram
MDC
MDIO
MII registers
RXIP
RXIM
TXOP
TXOM
10/100M TX
PHY
SCL
SDA
EEPROM
I/F
SSRAM
MII
Two port switch
Forward Mode
Control
PLL/ Clock
Generator
MII
100M FX
LED
I/F
FXSD
FXRDP
FXRDM
FXTDP
FXTDM
LED
Remote
Control
4. Application Diagram
FX
Fiber Module
Fiber Module
IP113M
IP113M
TX
2/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
5. Applications
5.1.
Managed converter (up to 31 pieces of IP113M in a chassis)
VCC
MDIX_EN
FAST_FWD
MDC, MDIO
uC
IP113M
(for management)
X1
X 31
5.2.
Un-managed converter
VCC
100BASE-TX
100BASE-FX
PHY1
PHY2
SWITCH
(un-used)
RAM
(un-used)
DIRECT_WIRE
TP_FORCE
SPEED_MODE
DUPLEX_MODE
IP113M
5.3.
Fiber Repeater
VCC
100BASE-FX
PHY1
100BASE-FX
PHY2
SWITCH
TWO_FIBER
RAM
IP113M
IP113M-DS-R02
May. 19, 2003
3/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
AVCC
MDIO
MDC
SCL / ADDR0
SDA
VCC
GND
GND
OSCI
X2
VCC
LED_FX_SD/ SPEED_MODE
LED_FX_FDX/ ADDR2
48
47
46
45
44
43
42
41
40
39
38
37
6. PIN Diagram
1
36
LED_FX_LINK/ FX_FULL
GND_IO
BGRES
2
35
AUTO_TEST
3
34
VCC_IO
GND
4
33
LED_TP_SPD/ TWO_FIBER/ MDIX
RXIP
5
32
LED_TP_FDX/ ADDR3
RXIM
6
31
LED_TP_LINK/ ADDR4
AVCC
7
30
LED_FX_FEF_DET/ DUPLEX_MODE
27
TSE
11
26
TSM
12
25
LED_RMT_TP_SPD/ AUTO_SEND
15
16
17
18
19
20
21
22
23
24
INTB
FXTDP
FXTDM
FXSD
VCC
GND
LFP
DIRECT_WIRE
FAST_FWD
LED_RMT_TP_FDX/ TP_FORCE
ADDR1
10
9
14
AVCC
RESETB
FXRDM
GND
LED_RMT_TP_LINK/ X_EN
28
8
13
TXOM
29
FXRDP
TXOP
IP113M
4/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
7. PIN Description
Type
I
Description
Input pin
O
Output pin
IPL
IPH
Input pin with internal pull low
Input pin with internal pull high
Pin no.
Label
Type
Description
Transceiver
5, 6
RXIP, RXIM
I
TP receive
8, 9
TXOP, TXOM
O
TP transmit
2
BGRES
O
Band gap resistor
It is connected to GND through a 6.19k (1%) resistor in
application circuit.
18
FXSD
I
100Base-FX signal detect
Fiber signal detect. It is an input signal from fiber MAU. Fiber
signal detect is active if the voltage of FXSD is higher than 1.2v.
13, 14
FXRDP, FXRDM
I
Fiber receiver data pair
16, 17
FXTDP, FXTDM
O
Fiber transmit data pair
IP113M-DS-R02
May. 19, 2003
5/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
7.
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins
31
LED_TP_LINK
O
TP port link LED
On: link ok, Off: link fail, Flash: link ok & activity
(Flash: on for 20ms and off for 80ms)
33
LED_TP_SPD
O
TP port speed LED
On: 100M, Off: 10M
32
LED_TP_FDX
O
TP port full duplex LED
On: full, Off: half,
Flash: half & collision happens
(Flash: on for 20ms and off for 80ms)
36
LED_FX_LINK
O
Fiber port link LED
On: link ok, Off: link fail, Flash: link ok & activity
(Flash: on for 20ms and off for 80ms)
37
LED_FX_FDX
O
Fiber port full duplex LED
On: full, Off: half, Flash: half & collision happens
(Flash: on for 20ms and off for 80ms)
38
LED_FX_SD
O
Fiber port signal detect
On: fiber signal detected, Off: fiber unplugged
30
LED_FX_FEF_DET
O
Far end fault pattern received
It’s on: for 80ms and off for 20ms if a far end fault pattern
received.
Off: there is no far end fault pattern received.
29
LED_RMT_TP_LINK
O
LED for link status of TP port of remote IP113M
When AUTO_TEST is logic low,
On: link ok,
Off: link fail
When AUTO_TEST is pulled high, it is always flash in a period
of 100ms (On: 80ms, Off: 20ms)
25
LED_RMP_TP_SPD
O
LED for speed of TP port of remote IP113M
When AUTO_TEST is logic low,
On: 100M,
Off: 10M
When AUTO_TEST is pulled high,
On: loop back test complete,
Off: during loop back test
24
LED_RMT_TP_FDX
O
LED for full duplex of TP port of remote IP113M
When AUTO_TEST is logic low,
On: full,
Off: half
When AUTO_TEST is pulled high,
On: loop back test ok,
Off: loop back test fail
Note: The output of LED pin is logic low when the LED is on.
6/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
7.
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins used as initial setting mode during reset
29
X_EN
IPH
IEEE 802.3X enable on TP port and fiber port
1: enable (default),
0: disable
24
TP_FORCE
IPL
Local TP port auto negotiation enable
1: TP port supports auto-negotiation with limited capability
defined in SPEED_MODE and DUPLEX_MODE.
0: TP port supports auto-negotiation with 10M/100M, full/ half
capability (default)
The default value may be updated by programming EEPROM
register 3.5 or MII register 20.13, too.
38
SPEED_MODE
IPH
Local TP port speed
1: TP port has the 100Mb speed ability
0: TP port has the 10Mb speed ability only
It is valid only if TP_FORCE is enabled.
30
DUPLEX_MODE
IPH
Local TP port duplex
1: TP port has the Full duplex ability
0: TP port has the Half duplex ability only
It is valid only if TP_FORCE is enabled.
25
AUTO_SEND
IPL
Auto send the status to the remote IP113M
1: enable
0: disable (default)
36
FX_FULL
IPH
Set the duplex of fiber port
1: full duplex (default)
0: half duplex
3
AUTO_TEST
IPL
Auto loop back test
1: enable
When IP113M detects a low-to-high transition on this pin, it will
perform loop back test for once.
0: disable (default)
IP113M-DS-R02
May. 19, 2003
7/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
7.
PIN Description (continued)
Pin no.
Label
Type
Description
LED pins used as initial setting mode during reset
33
TWO_FIBER
IPL
Two fiber ports
1: IP113M supports two-fiber ports mode. Both port 1 and port 2
are fiber ports. RXIP and RXIM are used as FXRDP and
FXRDM for the second fiber port. TXOP and TXOM are used
as FXTDP and FXTDM for the second fiber port.
A special requirement for the fiber MAU of port1 in this
application is that the output of FXRDP and FXRDM should
be kept silent when fiber is unplugged.
For some fiber MAUs, there are amplified noisy signals on
FXRDP and FXRDM when fiber is unplugged. These
amplified noisy signals, which include coupled idle patterns
from FXTDP and FXTDM will cause the LEDs of port1
malfunction
Generally, a 3.3-V small form factor type fiber MAUs (e.g.
Agilent HFBR-5903) can meet this special requirement, but
5-V duplex-SC and -ST type fiber MAUs cannot. Port2 is not
limited by this special requirement.
0: IP113M supports one fiber port and one TP port. Port 1 is a
TP port and port 2 is a fiber port.
8/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
7.
PIN Description (continued)
Pin no.
Label
Type
Description
MC operation mode
21
LFP
IPL
Link fault pass through (LFP)
1: enable
Link status of one port is forwarded to the other port.
0: disable (default)
22
DIRECT_WIRE
IPL
23
FAST_FWD
IPL
Store and forward switch mode:
IP113M begins to forward a frame at the end of receiving a
frame completely.
Modified cut-through switch mode:
IP113M begins to forward a frame after the first 64 bytes data
received. TP port should be forced at 100M at this mode.
Converter mode:
Incoming frames are not buffered in IP113M to achieve the min
latency. TP port should be forced at 100M at this mode.
Auto-change-forward function:
IP113M will change forward mode itself if it detects the speed is
different in TP port and FX port.
In converter mode, IP113M forwards IEEE802.3x pause frame
directly. In the other modes, IP113M doesn’t forward
IEEE802.3x pause frame directly, it sends out pause frame
when its internal buffer is full.
DIRECT_
WIRE
IP113M-DS-R02
May. 19, 2003
FAST_FW
D
Function
0
0
Store and forward switch mode
(default)
0
1
Modified cut-through switch mode
1
0
Converter mode
1
1
Converter mode with
auto-change-forward function
9/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
7.
PIN Description (continued)
Pin no.
Label
Type
Description
47, 48
MDC, MDIO
I, IO
SMI interface
The external MAC device uses the interface to program
IP113M. MDIO is an open drain.
31, 32,
37, 12, 46
ADDR[4:0]
IPL
PHY address
The external MAC device uses the address to identify each
IP113M in a chassis.
Type
Description
SMI interface
Pin no.
Label
EEPROM interface
45, 46
SDA, SCL
Pin no.
Label
IPH, O EEPROM interface
Type
Description
Misc.
28
RESETB
I
41, 40
OSCI, X2
I, O
Reset
It is low active.
Crystal pins
OSCI and X2 are connected to a 25Mhz crystal.
If a 25MHz oscillator is used, OSCI is connected to the oscillator’s
output and X2 should be left open.
26, 27
TSM, TSE
I
Scan pins
15
INTB
O
Interrupt
0: an interrupt happens. Its output is low.
1: no interrupt. Its output is high impedance and it needs an
external pull up resistor.
10/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
8. Functional Description
Modified cut-through mode
Pure converter mode
IP113M achieves the minimum latency in this mode.
It forwards the received data immediately when it
begins to receive a frame. Both transceivers are
interconnected via internal MIIs and the internal
switch engine and data buffer are not used. TP port
should be forced at 100M in this application. The
packet length is not limited at this mode. Please see
pin description of DIRECT_WIRE for configuration
information.
IP113M begins to forward the received data when it
receives the first 64 bytes of the frame. The latency
is about 512 bits. The maximum packet length is up
to1600 bytes at this mode. Please see pin
description of FAST_FWD for configuration
information.
Fragment forwarding
IP113M forwards CRC error packets but it will filter
fragments when it works in modified cut-through
mode. IP113M forwards fragments if user turns on
bit 3 of MII register 20.
Data forwarding
IP113M supports three types of data forwarding
mode, store & forward mode, modified cut-through
mode and pure converter mode. It forwards frame in
spite of its address and CRC error. IP113M begins
to forward the received data when it receives the
frame completely. The latency depends on the
packet length.
TP port force mode
The TP port of IP113M can work at auto mode or force mode. The following table shows all of the combination
of its TP port.
TP_FORCE
SPEED_MODE
DUPLEX_MODE
0
1
1
100/10M, Full/Half with auto-negotiation
IP113M’s capability
0
1
0
100/10M, Half with auto-negotiation
0
0
1
10M, Full/Half with auto-negotiation
0
0
0
10M, Half with auto-negotiation
1
1
1
100M, Full with auto-negotiation
1
1
0
100M, Half with auto-negotiation
1
0
1
10M, Full with auto-negotiation
1
0
0
10M, Half with auto-negotiation
IP113M-DS-R02
May. 19, 2003
11/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Remote management
IP113M supports remote monitor and configuration function. IP113M implement the function by exchanging
maintenance frames on fiber ports between a pair of IP113Ms. The maintenance frames are not forwarded to
TP ports. The frame format follows the TS-1000 standard.
Maintenance frame format at MII
TXD0
F0 F4 C0 C4 C8
C12 S0 S4 S8
S12 M0 M4 M8
M12 M16 M20 M24 M28 M32 M36 M40 M44 E0 E4
TXD1
F1 F5 C1 C5 C9
C13 S1 S5 S9
S13 M1 M5 M9
M13 M17 M21 M25 M29 M33 M37 M41 M45 E1 E5
TXD2
F2 F6 C2 C6 C10 C14 S2 S6 S10 S14 M2 M6 M10 M14 M18 M22 M26 M30 M34 M38 M42 M46 E2 E6
TXD3
F3 F7 C3 C7 C11 C15 S3 S7 S11 S15 M3 M7 M11 M15 M19 M23 M27 M31 M35 M39 M43 M47 E3 E7
TXEN
Bit definition of maintenance frame
Bit
Item
Description
Note
F7 – F0
Preamble
01010101
Fixed
C0
Discriminator for the
maintenance signal
0
Fixed
C1
Direction
0: terminal MC Æ central MC
1: central MC Æ terminal MC
(MC: media converter)
C3 – C2
Command
00: Reserved
10: Indication
01: Request
11: Acknowledge
C7 – C4
Version
0000
C15 – C8
Control signal
00 00 00
00 00 00
00 00 00
addr[4:0] RW
S0
Condition of power
0: normal, 1: power off
S1
Situation of receiving optical
power
0: normal, 1: abnormal
S2
Terminal/ network side link
0: link up, 1: link down
If S11=“1”, S2=”X”
S3
MC (media converter) fails
0: normal, 1: abnormal
S4
Informing way for optical
receiving power off
0: maintenance frame
1: Far end fault indication
S5
Status indication for loop test
0: normal mode, 1: under loop test
12/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
Fixed
01
00
10
11
: Loop test starts
: Loop test ends
: Status notice
: IP113M R/W reg.
IP113M-DS-R02
May. 19, 2003
IP113M
Bit definition of maintenance frame (continued)
Bit
Item
Description
S6
Information for notice of
terminal link status
(Available for option B or not)
0: terminal IP113M does not support option B.
1: terminal IP113M supports option B, which can
inform speed, duplex, and auto-negotiation in
terminal IP113M.
If S11 = “1”, S6=”X’
S8 – S7
Terminal link speed
00: 10 Mbps
01: 100 Mbps
10: 1000 Mbps
11: others
It is valid, if S6 = ”1”.
If S2 or S11 = “1”, S7, S8 = {X, X}
S9
Duplex for the terminal side
1: full duplex, 0: half duplex
It is valid, if S6 = ”1”.
If S6 =“0”, S9=“0”.
If {S7, S8} = {1,1}, S9=”X”
If S2 or S11 = “1”, S9=”X”
S10
Auto-negotiation capability
for the terminal side
1: available, 0: un-available
It is valid, if S6 = ”1”.
If S6 =“0”, S10=“0”.
If {S7, S8} = {1,1}, S10=”X”
If S11 = “1”, S10=”X”
S11
Number of interface in
Terminal/ network side
0: one UTP
1: more than one UTP
S15 – S12
Reserved
M23 – M0
Vender code
Vender code for TTC standard 24 bits
M47 – M24
Model number
Specified by vender
E7 – E0
FCS
CRC – 8
FCS calculation area: C0 - M47
IP113M-DS-R02
May. 19, 2003
13/48
Note
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Remote monitor
Users can instruct central IP113M to issue a status request frame to get status defined in TS-1000 by
programming MII register 24. The terminal IP113M receives the status request frame and sends out its current
status as a response frame onto the fiber port when it is available. The central IP113M receives the status frame
and stores the status of terminal IP113M to its MII register 23. An acknowledge maintenance frame is store to
MII register 26~30. The status of terminal IP113M is shown on LED of central IP113M.
(1)
TP
IP113M
(terminal)
Maintenance frame
(C1=1, C2-3=10, C8-15=01000000)
FX
IP113M
(central)
(MII reg 24, 23)
Maintenance frame
(C1=0, C2-3=11, C8-15=01000000)
TP
(2)
MDC, MDIO
Remote control read
Besides reading the status defined in TS-1000, users can instruct central IP113M to issue a remote control read
frame to read the MII register of terminal IP113M by programming MII register 24. The bit 24[11:7] is filled with
the address of register and bit 24[6:4] is filled with “011”. The terminal IP113M receives the frame and sends out
the content of the MII register to central IP113M when it is available. The central IP113M receives the frame and
stores the data to MII register 27. An acknowledge maintenance frame is stored to MII register 26~30. The
status of terminal IP113M is shown on LED of central IP113M.
TP
IP113M
(terminal)
Maintenance frame
(C1=1, C2-3=10, C8-15=110xxxxx)
FX
IP113M
(central)
(MII reg 24,27)
Maintenance frame
(C1=0, C2-3=11, C8-15=01000000)
TP
MDC, MDIO
Remote control write
Users can instruct central IP113M to issue a configure frame to write the MII register of terminal IP113M by
programming MII register 24 and 25. The bit 24[11:7] is filled with the address of register and bit14[6:4] is filled
with “111”. MII register 25 defines the data. The terminal IP113M receives the configure frame, configures itself
according to the content of the frame and sends out its current status as a response frame onto the fiber port
when it is available. The status of terminal IP113M is shown on LED of central IP113M.
TP
IP113M
(terminal)
Maintenance frame
(C1=1, C2-3=10, C8-15=111xxxxx)
FX
Maintenance frame
(C1=0, C2-3=11, C8-15=01000000)
14/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
(central)
(MII reg 24,25)
TP
MDC, MDIO
IP113M-DS-R02
May. 19, 2003
IP113M
Loop back test
IP113M supports two kind of loop back test function, in-band loop back test and out-band loop back test.
Out-band loop back test
Users can instruct central IP113M to issue a maintenance frame onto the fiber port by programming MII register
24 to request a loop back test. Central IP113M does not generate test frames and users need an external
packet source from PC.
1. Disconnect switch port and instruct the terminal IP113M to perform loop back and disable
terminal T2 timer by programming central IP113M through SMI
(1)
IP113M
(terminal)
TP
Maintenance frame
(C1=1, C2-3=10, C8-15=10000000)
FX
IP113M
(central)
TP
Switch
(MII reg 24)
(2)
Maintenance frame
(C1=0, C2-3=11, C8-15=10000000)
MDC, MDIO
2. Terminal IP113M runs at loop back mode
IP113M
(terminal)
TP
IP113M
(central)
FX
TP
Switch
(MII reg 0.14=1)
3. PC forces test frames to central IP113M and terminal IP113M loops back the frames.
IP113M
(terminal)
TP
test frame
IP113M
(central)
FX
TP
(MII reg 0.14=1)
PC
test frame
4. PC reports the loop back test result after sending all test frames.
IP113M
(terminal)
TP
(MII reg 0.14=1)
IP113M-DS-R02
May. 19, 2003
IP113M
(central)
FX
TP
PC
15/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
5. Reconnect switch and instruct the central IP113M to end loop back test and enable T2 timer.
(1)
IP113M
(terminal)
TP
Maintenance frame
(C1=1, C2-3=10, C8-15=00000000)
FX
IP113M
(central)
TP
Switch
(MII reg 24)
(2)
Maintenance frame
(C1=0, C2-3=11, C8-15=00000000)
16/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
MDC, MDIO
IP113M-DS-R02
May. 19, 2003
IP113M
Loop back test (continued)
In-band loop back test
Besides performing the loop back test with an external packet source, IP113M supports an easy alternative.
IP113M sends out private maintenance frame to do loop back test. All users have to do is to program MII
registers through SMI.
1. Disabe receive function of central TP port and instruct the terminal IP113M to perform loop back
and disable T2 timer by programming central IP113M through SMI
Maintenance frame
(C1=1, C2-3=10, C8-15=10000000)
IP113M
(terminal)
FX
TP
IP113M
(central)
TP
Switch
(MII reg 24)
MDC, MDIO
2. Terminal IP113M runs at loop back mode and acknowledges with maintenance frame
IP113M
(terminal)
TP
IP113M
(central)
FX
TP
Switch
(MII reg 0.14=1)
Maintenance frame
(C1=0, C2-3=11, C8-15=10000000)
3. Central IP113M forces test frames to terminal IP113M and terminal IP113M loops back the
test frames. Central IP113M checks the received test frame.
test frame
IP113M
(terminal)
TP
IP113M
(central)
FX
TP
Switch
(MII reg 24,25)
(MII reg 0.14=1)
test frame
MDC, MDIO
4. Central IP113M ends loop back test enables receive function of TP port and enable LP T2 timer
(1)
IP113M
(terminal)
TP
Maintenance frame
(C1=1, C2-3=10, C8-15=00000000)
FX
IP113M
(central)
TP
Switch
(MII reg 24)
(2)
Maintenance frame
(C1=0, C2-3=11, C8-15=00000000)
IP113M-DS-R02
May. 19, 2003
MDC, MDIO
17/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Loop back test (continued)
Programming procedure for In-band loop back test
Step Description
1
2a
Set local IP113M TP receive disable
Set loopback T2 timer disable:
maintenance frame
2
Set remote IP113M to be loop back
mode enable: maintenance frame
Remote IP113M sends back loop back
acknowledge
C1
C3~C2
C15~C8
Note
1
01
11 11 10 01
Set Reg. 20.14 off
TS-1000: T2 timer
disable
1
01
00 00 00 01
TS-1000: loop back set
0
11
00 00 00 01
4
Send loop back test maintenance frame 1
via SMI
01
11 01 10 11
Fill the S[15:0]
5
Remote link send back acknowledge
11
11 01 10 11
Send back S[15:0]
6
Local IP113M stores the loop back
maintenance to Reg. 26~30 and checks
CRC bit is in Reg. 26.12
--
7
Repeat step 4~6 continuously
--
8
Set remote IP113M to be loop back
mode disable: maintenance frame
Remote IP113M sends back loop back
acknowledge
3
9
10
0
--
1
01
00 00 00 00
TC-1000: loop back end
0
11
00 00 00 00
--
Set local IP113M TP receive enable
Set Reg. 20.14 on
Auto in-band loop back test
Step
Description
1
Set pin AUTO_TEST to “1” (The following step is executed automatically by IP113M)
1.1
Central IP113M sends loop back start request to remote IP113M and goes to CST2 state.
1.2
1.3
Remote IP113M sends loop back start acknowledge to Central IP113M and enters loop back test
mode.
Central IP113M goes to CST1 state and begins sending 15 frames in 64 bytes.
1.4
Remote IP113M loops back the received frames at the TP port’s PMD sub-layer.
1.5
Central IP113M checks the loop back frames and reports the result.
2
The LED pin LED_RMT_TP_LINK is Flash (on 80ms / off 20ms) during the auto loop back test period
(AUTO_TEST is “1”).
The LED pin LED_RMT_TP_SPD indicates the loop back test complete (on) (when AUTO_TEST is
“1”). The LED pin LED_RMT_TP_FDX indicates the loop back test ok (on) (when AUTO_TEST is “1”)
3
4
If another auto loop back test is needed, set AUTO_TEST to “0” and then “1”. That is, AUTO_TEST is
triggered whenever there is a low-to-high transition on this pin.
18/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
Remote monitor without SMI programming
Auto sends (Status change notice)
IP113M sends out status frame without receiving status request frame if pin AUTO_SEND is pulled high. It
sends out the first status frame onto the fiber port when the link status of fiber port is ok. It sends out status
frames when the status on TP port is changed. IP113M supports two types of frame. For a TS-1000
maintenance frame, C[9:8] is 2’b10 and S[15:0] is defined as that in TS-1000 standard. For an ICplus
maintenance frame, C[9:8] is 2’b11 and S[15:0] is the content of MII register 22. It carries ICplus private defined
information. User can select the frame type by programming MII register 20.10. Central IP113M uses the
mechanism to get the status of the remote IP113M even if there is no SMI programming.
Option A
Central IP113M sends indication frames to terminal IP113M if its status is changed.
Maintenance frame
(C1=1, C2-3=01, C8-9= 01)
IP113M
(terminal)
TP
IP113M
(central)
TP
FX
status changed !!
Option B
Terminal IP113M sends indication frames to central IP113M if its status is changed.
Maintenance frame
(C1=0, C2-3=01, C8-9= 01)
IP113M
(terminal)
TP
IP113M
(central)
TP
FX
status changed !!
CRC polynomial for maintenance frame: X8 + X2 + X + 1
data in
CRC + data
X0
X1
X2
X3
X4
X5
X6
X7
CRC calculation
IP113M-DS-R02
May. 19, 2003
19/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Link fault pass through
When the function is enabled, link status on TX port is propagated to the FX port and vice versa. If link fails on
TX port of local IP113M, the FX port sends non-idle pattern to notice the remote FX port. The remote FX port
forces its TX port link failure after receiving the non-idle pattern. Eventually, the link fault status of local TX port
of a converter is propagated to the TX port of the remote converter by the mechanism. The link status of the
remote TX port becomes off. Link LED is off for IP113M and its link partner. The operation is illustrated in the
following figures.
Switch1 or
NIC 1
UTP
disconnected
(5) remote TP
link is off
(3) fiber port gets remote
link fault information
(1) TP port link failed
local
IP113M
remote
Fiber
UTP
IP113M
Switch2 or
NIC 2
link off
(2) fiber port sends
non-idle pattern
(4) TP link fail
The procedure of link fault pass through
Normal case
remote
local
UTP
Switch1
LED
SW1
IP113M
LED_TP_LINK1
Fiber
LED_FX_LINK1
UTP
IP113M
LED_FX_LINK2
LED_TP_LINK2
Switch2
LED
SW2
Link LED
on SW1
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2
Link LED
on SW2
ON
ON
ON
ON
ON
ON
Remote TP port disconnected
UTP
disconnected
remote
Switch1
IP113M
LED
SW1
LED_TP_LINK1 LED_FX_LINK1
local
UTP
Fiber
Switch2
IP113M
LED_FX_LINK2 LED_TP_LINK2
LED
SW2
Link LED
on SW1
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2
Link LED
on SW2
Off
Off
Off
Off
Off
20/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
Off
IP113M-DS-R02
May. 19, 2003
IP113M
FX port disconnected
remote
local
UTP
Switch1
LED
SW1
IP113M
LED_TP_LINK1
Fiber
LED_FX_LINK1
UTP
IP113M
LED_FX_LINK2
LED_TP_LINK2
Switch2
LED
SW2
Link LED
on SW1
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2
Link LED
on SW2
Off
Off
Off
Off
Off
Off
LED diagnostic functions for fault indication
LED_TP_LINK
LED_FX_LINK
LED_FX_SD
LED_FX_FEF_DET
Status
On
Flash
On
Flash
On
On
Off
Off
Link ok
Link ok & activity
Off
Off
On
Off
Remote TP link off
Off
Off
Off
Off
Fiber RX off, Fiber TX/ RX off
Off
Off
On
Flash
Fiber TX off
Note
Flash: flash, period 100 ms
Link fault pass through is enabled.
IP113M-DS-R02
May. 19, 2003
21/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
EEPROM – store the initial value
IP113M supports two ways to load initial value of MII registers. The procedure is illustrated as below.
1. IP113M reads the default setting of MII register from pins
IP113M
pins
2. IP113M updates the default setting of MII by reading EEPROM. If there exists an EEPROM.
IP113M
EEPROM
3. After reading EEPROM, IP113M is virtually isolated from the EEPROM. Micro-controller can
program both MII register and EEPROM.
EEPROM
uC
SCL, SDA
IP113M
MDC, MDIO
4. IP113M reloads the content of EEPROM to recover the value in MII registers programmed
by Micro-controller after power on reset.
EEPROM
IP113M
22/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
Auto MDI_MDIX
IP113M supports auto MDI-MDIX. It is always enabled. The following is its application circuit for auto MDI-MDIX.
RXIP
RD +
TXOP
TD +
RXIM
RD -
TXOM
TD -
IP113M
IP113M
AVCC
50Ω
50Ω
CT
AVCC
50Ω
50Ω
MDI-MDIX
0.1u
CT
MDI-MDIX
transformer
0.1u
GND
transformer
GND
IP113M's application circuit (auto MDI-MDIX on)
IP113M-DS-R02
May. 19, 2003
23/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Serial management interface
User can access IP113M’s MII registers through serial management interface MDC and MDIO. A specific
pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle,
MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32
contiguous “1” and “start” on MDIO.
Syatem diagram
113M
MDC
MDIO
113M
MDC
113M
MDIO
MDC
MDIO
management
entity
Frame
format
<Idle><start><op code><IP113M’s address><Registers address><turnaround>
<data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
MDC
z
z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1
op
A A A A A R R R R R TA b b b
idle start
code
4 3 2 1 0 4 3 2 1 0
1 1 1
write
PHY address =
Reg address =
5 4 3
01h
00h
1
b
1
2
0
b
1
1
0 1 1 0 0 0 0 0 0 0 0 1..1
b b b b b b b b b b b idle
1 9 8 7 6 5 4 3 2 1 0
0
Register data
MDC
MDIO
z
z
z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
start
op
code
read
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
4 3 2 1 0 4 3 2 1 0
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
24/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
idle
IP113M-DS-R02
May. 19, 2003
IP113M
MII registers
Address
Control
Register Name
0
1
Control Register
Status Register
NWAY
NWAY
2
PHY identifier Register 1
NWAY
3
PHY identifier Register 2
NWAY
4
AN Advertisement Register
NWAY
5
AN Link Partner Base Page Ability Register
NWAY
6
7
AN Expansion Register
(Reserved)
NWAY
8
(Reserved)
9
(Reserved)
10
(Reserved)
11
12
(Reserved)
(Reserved)
13
(Reserved)
14
(Reserved)
15
(Reserved)
16
17
Special Control Register
Interrupt Register
NWAY
NWAY
18
Extended Status Register
NWAY
19
Statistic Counter Register
SWITCH
20
Switch Configuration Register 1
SWITCH
21
Switch Configuration Register 2
SWITCH
22
23
Local Switch Extended Register
Link Partner Switch Extended Status Register
SWITCH
SWITCH
24
Remote Control Transmit Register 1
RMC
25
Remote Control Transmit Register 2
RMC
26
Remote Control Receive Register 1
RMC
27
28
Remote Control Receive Register 2
Remote Control Receive Register 3
RMC
RMC
29
Remote Control Receive Register 4
RMC
30
Remote Control Receive Register 5
RMC
31
Switch Configuration Register 3
SWITCH
IP113M-DS-R02
May. 19, 2003
25/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
The basic MII registers
Type
R/W
SC
RO
MII
Description
Read/Write
Self-Clearing
Read Only
NAME
Type
RC
LL
LH
R/W
Description
Read and Clear
Latching Low
Latching High
DESCRIPTION
DEFAULT
MII control register (address 00h)
0.15
Reset
R/W
SC
1 = PHY reset
0 = normal operation
This bit is self-clearing, IP113M will return a value of 1
before reset process is completed, and will not accept any
write transaction of MII Management within reset process.
Make any change to Auto-Negotiation or speed mode will
cause IP113M reset again.
0
0.14
Loopback
R/W
1 = Loopback mode
0 = normal operation
When this bit set, IP113M will be isolated from the network
media, and the assertion of TXEN at the MII will not
transmit data on the network. All MII transmit data path will
return to MII receive data path in response to the assertion
of TXEN. MII COL signal will remain de-asserted at all
times, unless bit 0.7 (Collision Test) is set.
0
0.13
Speed Selection
RW
1 = 100Mbps
0 = 10Mbps
It is valid only if bit 0.12 is set to be 0.
1
0.12
Auto-Negotiation
Enable
RW
1 = Auto-Negotiation Enable
0 = Auto-Negotiation Disable
MII register 16.11 auto-MDI/MDIX should be disabled if
auto-negotiation is disabled.
1
0.11
Power Down
R/W
1 = power down
0 = normal operation
Setting this bit to 1 will cause IP113M into power down
mode, but still respond to management transactions.
0
0.10
Isolate
R/W
1 = electrically isolate PHY from MII
0 = normal operation
When this bit is setting to 1, IP113M will be isolated from
RMII, and not respond to the TXD[3:0] and TXEN and
keep CRS, RXDV and RXD[3:0] in high impedance, but
will respond to management transactions.
If PHY address of IP113M is setting to 0 at power-on reset,
this bit will be set to 1, otherwise will be set to 0.
0
26/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
MII control register (address 00h)
0.9
Restart AutoNegotiation
RW
1 = re-starting Auto-Negotiation
0 = Auto-Negotiation re-start complete
Setting this bit to logic high will cause IP113M to restart an
Auto-Negotiation cycle, but depend on the value of bit 0.12
(Auto-Negotiation Enable). If bit 0.12 is cleared then this
bit has no effect, and change to Read Only. When an
Auto-Negotiation cycle is being processed, write 0 into this
bit has no effect. This bit is self-clearing after
Auto-Negotiation process is completed.
0
0.8
Duplex mode
R/W
1 = full duplex
0 = half duplex
It is valid only if bit 0.12 is set to be 0.
0
0.7
Collision test
enable
R/W
1 = enable the collision test
0 = disable the collision test
If setting this bit to logic 1, when MII TXEN signal is
asserted, IP113M will assert the MII COL signal within
512BT (Bit Time, depend on 10Mbps or 100Mbps). When
MII TXEN is de-asserted, then TP110 will assert MII COL
signal within 4BT. Clearing this bit to logic 0 for normal
operation
0
0[6:0]
Reserved
R/W
Write as 0, ignore on read
-
IP113M-DS-R02
May. 19, 2003
27/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
MII status register (address 01h)
1.15
100Base-T4
capable
RO
1 = 100Base-T4 capable
0 = not 100Base-T4 capable
IP113M does not support 100Base-T4. This bit is fixed to
be 0.
0
1.14
100Base-X full
duplex Capable
RO
1 = 100Base-X full duplex capable
0 = not 100Base-X full duplex capable
The default of this bit will change depend on the external
setting of IP113M. If external pin setting without
100Base-X full duplex support, then this bit will change
default to logic 0.
1
1.13
100Base-X half
duplex Capable
RO
1 = 100Base-X half duplex capable
0 = not 100Base-X half duplex capable
The default of this bit will change depend on the external
setting of IP113M. If external pin setting without
100Base-X half duplex support, then this bit will change
default to logic 0
1
1.12
10Base-T full
duplex Capable
RO
1 = 10Base-T full duplex capable
0 = not 10Base-T full duplex capable
The default of this bit will change depend on the external
setting of IP113M. If external pin setting without
100Base-T full duplex support, then this bit will change
default to logic 0
1
1.11
10Base-T half
duplex Capable
RO
1 = 10Base-T half duplex capable
0 = not 10Base-T half duplex capable
The default of this bit will change depend on the external
setting of IP113M. If external pin setting without
100Base-X full duplex support, then this bit will change
default to logic 0
1
1[10:7]
Reserved
RO
Ignore on read
-
1.6
MF preamble
Suppression
RO
1 = preamble may be suppressed
0 = preamble always required
1
1.5
Auto-Negotiation
Complete
RO
1 = Auto-Negotiation complete
0 = Auto-Negotiation in progress
When read as logic 1, indicates that the Auto-Negotiation
process has been completed, and the contents of register
4, 5, 6 and 7 are valid. When read as logic 0, indicates that
the Auto-Negotiation process has not been completed,
and the contents of register 4, 5, 6 and 7 are meaningless.
If Auto-Negotiation is disabled (bit 0.12 set to logic 0), then
this bit will always read as logic 0.
0
28/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
MII status register (address 01h)
1.4
Remote fault
RO
LH
1 = remote fault detected
0 = not remote fault detected
When read as logic 1, indicates that IP113M has detected
a remote fault condition. This bit is set until remote fault
condition gone and before reading the contents of the
register. This bit is cleared after IP113M reset.
0
1.3
Auto-Negotiation
Ability
RO
1 = Auto-Negotiation capable
0 = not Auto-Negotiation capable
When read as logic 1, indicates that IP113M has the ability
to perform Auto-Negotiation. The value of this bit will
depend on the external mode setting of IP113M operation
mode.
1
1.2
Link Status
RO
LL
1 = Link Pass
0 = Link Fail
When read as logic 1, indicates that IP113M has
determined a valid link has been established. When read
as logic 0, indicates the link is not valid. This bit is cleared
until a valid link has been established and before reading
the contents of this registers.
0
1.1
Jabber Detect
RO
LH
1 = jabber condition detected
0 = no jabber condition detected
When read as logic 1, indicates that IP113M has detected
a jabber condition. This bit is always 0 for 100Mbps
operation and is cleared after IP113M reset. This bit is set
until jabber condition is cleared and reading the contents
of the register.
0
1.0
Extended
capability
RO
1 = Extended register capabilities
0 = No extended register capabilities
IP113M has extended register capabilities.
1
IP113M-DS-R02
May. 19, 2003
29/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
PHY Identifier (address 02h)
2[15:0]
PHY identifier
RO
IP113M OUI (Organizationally Unique Identifier) ID, the
msb is 3rd bit of IP113M OUI ID, and the lsb is 18th bit of
IP113M OUI ID. IP113M OUI is 0090C3.
0243h
MII
NAME
R/W
DESCRIPTION
DEFAULT
PHY Identifier (address 03h)
3[15:10]
PHY identifier
RO
IP113M OUI ID, the msb is 19th bit of IP113M OUI ID, and
lsb is 24th bit of IP113M OUI ID.
3h
3[9:4]
Manufacture’s
Model Number
RO
TP110 model number
6h
3[3:0]
Revision
Number
RO
IP113M revision number
0
30/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
Auto-Negotiation Advertisement register (address 04h)
4.15
Next Page
RW
1 = Next Page ability is supported
0 = Next Page ability is not supported
IP113M does not support next page, this bit is fixed to be
0.
0
4.14
Reserved
RW
Reserved by IEEE, write as 0, ignore on read
0
4.13
Remote Fault
R/W
1 = Advertises that this device has detected a remote fault
0 = No remote fault detected
0
4[12:11]
Reserved
RO
Reserved for future IEEE use, write as 0, ignore on read
0
4.10
Pause
RW
1 = Advertises that this device has implemented pause
function
0 = No pause function supported
0
4.9
100BASE-T4
RW
1 = 100BASE-T4 is supported
0 = 100BASE-T4 is not supported
0
4.8
100BASE-TX
full duplex
R/W
1 = 100BASE-TX full duplex is supported
0 = 100BASE-TX full duplex is not supported
0
4.7
100BASE-TX
R/W
1 = 100BASE-TX is supported
0 = 100BASE-TX is not supported
0
4.6
10BASE-T full
duplex
R/W
1 = 10BASE-T full duplex is supported
0 = 10BASE-T full duplex is not supported
0
4.5
10BASE-T
R/W
1 = 10BASE-T is supported
0 = 10BASE-T is not supported
0
4[4:0]
Selector Field
R/W
Use to identify the type of message being sent by
Auto-Negotiation.
IP113M-DS-R02
May. 19, 2003
31/48
00001
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
Link partner ability register (address 05h) Base Page
5.15
Next Page
RO
1 = Next Page ability is supported by link partner
0 = Next Page ability is not supported by link partner
0
5.14
Acknowledge
RO
1 = Link partner has received the ability data word
0 = Not acknowledge
0
5.13
Remote Fault
RO
1 = Link partner indicates a remote fault
0 = No remote fault indicate by link partner
If this bit is set to logic 1, then bit 1.4 (Remote fault) will set
to logic 1.
0
5[12:10]
Reserved
RO
Reserved by IEEE for future use, write as 0, read as 0.
0
5.9
100BASE-T4
RO
1 = Link partner support 100BASE-T4
0 = Link partner is not support 100BASE-T4
0
5.8
100BASE-TX
full duplex
RO
1 = Link partner support 100BASE-TX full duplex
0 = Link partner is not support 100BASE-TX full duplex
0
5.7
100BASE-TX
RO
1 = Link partner support 100BASE-TX
0 = Link partner is not support 100BASE-TX
0
5.6
10BASE-T full
duplex
RO
1 = Link partner support 10BASE-T full duplex
0 = Link partner is not support 10BASE-T full duplex
0
5.5
10BASE-T
RO
1 = Link partner support 10BASE-T
0 = Link partner is not support 10BASE-T
0
5[4:0]
Selector Field
RO
Protocol selector of the link partner
32/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
00000
IP113M-DS-R02
May. 19, 2003
IP113M
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
Auto-Negotiation Expansion register (address 06h)
6[15:5]
Reserved
RO
Reserved by IEEE, writes as 0, ignore on read.
0
6.4
Parallel
Detection Fault
RO
LH
1 = A fault has been detected via Parallel Detection
function
0 = A fault has not detected via Parallel Detection function
0
6.3
Link Partner
Next Page Able
RO
1 = Link Partner is Next Page able
0 = Link Partner is not Next Page able
0
6.2
Next Page Able
RO
1 = Local Device is Next Page able
0 = Local Device is not Next Page able
0
6.1
Page Received
RO
LH
1 = A New Page has been received
0 = A New Page has not been received
0
6.0
Link Partner
Auto-Negotiation
Able
RO
1 = Link Partner is Auto-Negotiation able
0 = Link Partner is not Auto-Negotiation able
0
IP113M-DS-R02
May. 19, 2003
33/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
EEPROM enable register 0 (EEPROM register 00D)
--
0[7:0]
MII
ROM
NAME
RO
EEPROM enable register 0
This register should be filled with 55. IP113M will
examine the specified pattern to confirm if there
is a valid EEPROM.
55
R/W
DESCRIPTION
DEFAULT
EEPROM enable register 1 (EEPROM register 01D)
--
1[7:0]
RO
EEPROM enable register 1
This register should be filled with AA. IP113M will
examine the specified pattern to confirm if there
is a valid EEPROM. The initial setting is updated
with the content of EEPROM only if the specified
pattern 55AA is found.
34/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
AA
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Reserved register
7
--
Reserved
8
--
Reserved
9
--
Reserved
10
--
Reserved
11
--
Reserved
12
--
Reserved
13
--
Reserved
14
--
Reserved
15
--
Reserved
IP113M-DS-R02
May. 19, 2003
35/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Special control register (16D)
16.0
--
mr_analog_off
R/W
ANALOG on/off (It is valid only if register
16.15=0.)
1: analog off, 0: analog on (default)
0
16.1
--
mr_lpds_mode
R/W
Low power mode disable (It is valid only if
16.15=0.)
1: disable, 0:enable (default)
0
16.2
--
mr_repeater_mode
R/W
REPEAT mode enable
1: enable, 0:disable (default)
0
16.3
--
mr_bypass_scram
ble
R/W
Bypass PCS scrambler (It is valid only if
16.15=1.)
1: bypass scrambler, 0: not bypass (default)
0
16.4
--
mr_bypass_100x
_coder
R/W
Bypass PCS 4B/5B coder (It is valid only if
16.15=1.)
1: bypass 4B/5B, 0: not bypass (default)
0
16.5
--
mr_bypass_dsp
_rst
R/W
Bypass DSP re-start function in PCS
1: bypass DSP re-start, 0: not bypass (default)
0
16.6
--
mr_tx_nlp_en
R/W
10Mb transmit NLP enable
1: enable (default), 0:disable
1
16.7
--
mr_analog_pwsv
_disable
R/W
Analog power save mode disable
1: disable, 0: enable (default)
0
16.8
--
mr_fef_disable
R/W
Far-End-Fault function disable
1: disable, 0: enable (default)
0
16.9
--
mr_jabber_enable
R/W
Jabber function enable
1: enable, 0:disable (default)
0
16.10
--
mr_heart_beat
_enable
R/W
Heart Beat function enable
1: enable, 0:disable (default)
0
16.11
--
mr_auto_cross
_disable
R/W
Auto Crossover function disable
1: disable, 0: enable (default)
It should be disabled if MII register 0.12
auto-negotiation is disabled.
0
16.12
--
mr_speed_up_dsp
R/W
Speed Up DSP (It is valid only if 16.15=1.)
1: enable, 0:disable (default)
0
16.13
--
mr_speed_up
R/W
Speed Up Digital Simulation (It is valid only if
16.15=1.)
1: enable, 0:disable (default)
0
16.14
--
Reserved
R/W
16.15
--
mr_debug_mode
R/W
0
DEBUG mode enable
1: enable, 0:disable (default)
36/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
0
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Interrupt register (17D)
17.0
--
intr_link
RO
RC
Link status change
It is logic “1” when link status changes on TP port
and it will active interrupt pin. It is self-clear after
reading the register.
1: Interrupt occur 0: nothing happen
0
17.1
--
intr_duplex
RO
RC
Duplex mode change
1: Interrupt occur 0: nothing happen
0
17.2
--
intr_speed
RO
RC
Speed mode change
1: Interrupt occur 0: nothing happen
0
17.3
--
intr_mf_rx_indicate
RO
RC
Maintenance frame receive indication
1: Interrupt occur 0: nothing happen
0
17.4
--
intr_cnt_overflow
RO
RC
Statistic counter overflow
1: Interrupt occur 0: nothing happen
0
17.5
--
intr_status
RO
RC
Interrupt status
1: Interrupt occur 0: nothing happen
It is logic “OR” of 17.0~17.4.
0
17.6
--
Intr_pwabn
RO/R
C
Interrupt status
1: remote link partner power abnormal
0: nothing happen
0
17.7
--
Intr_pwabn_en
RW
Remote LP power abnormal interrupt enable.
0
17.8
--
intr_link_mask
RW
Mask TP port link change Interrupt
1: mask, 0: not mask (default)
1
17.9
--
intr_duplex_mask
RW
Mask TP port duplex mode change Interrupt
1: mask interrupt (default), 0: not mask
1
17.10
--
intr_speed_mask
RW
Mask TP port speed mode change Interrupt
1: mask interrupt (default), 0: not mask
1
17.11
--
intr_mf_rx_indc
_mask
RW
Mask maintenance frame receive indication
Interrupt
1: mask interrupt (default), 0: not mask
1
17.12
--
intr_cnt_ov_mask
RW
Mask Statistic counter overflow Interrupt
1: mask interrupt (default), 0: not mask
1
17.13
--
intr_all_mask
RW
Mask all Interrupt
1: mask interrupt (default), 0: not mask
1
17[15:14]
--
Reserved
RW
IP113M-DS-R02
May. 19, 2003
0
37/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
PHY extended status register (18D)
18[3:0]
--
an_arbit_state[3:0]
RO
NWAY state machine
0
18[6:4]
--
Reserved[2:0]
RO
18.7
--
jabber
RO
Jabber status
1: jabber, 0: no jabber (default)
0
18.8
--
polarity
RO
Polarity status
1: polarity error, 0: polarity ok (default)
0
18.9
--
mdix_en
RO
MDI/MDIX status
0: MDI, 1:MDIX
0
18.10
--
link_real
RO
TP port link Status
1: link ok, 0; link fail (default)
0
18.11
--
resolved
RO
Resolve complete
1: Nway or force mode complete, 0: not
complete (default)
0
18.12
--
Reserved
RO
18.13
--
mr_duplex_mode
RO
TP port duplex mode (It is valid only if 18.11=1.)
1: full (default), 0: half
1
18.14
--
mr_speed_selection
RO
TP port operation speed (It is valid only if
18.11=1.)
1: 100M (default), 0: 10M
1
18.15
--
Reserved
RO
0
0
38/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
0
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Statistic counter registers (MII register 19D)
19[11:0]
--
mg_statistic_cnt
[11:0]
RO
Statistic Counter [11:0]
0
Cnt_index Content of statistic counter[11:0]
3'b000
TP port (port1) received packet count
3'b001
TP port (port1) received CRC error count
3'b010
TP port (port1) drop packet count
3'b011
TP port (port1) collision event count
3'b100
FX port (port2) received packet count
3'b101
FX port (port2) received CRC error count
3'b110
FX port (port2) drop packet count
3'b111
FX port (port2) collision event count
19[14:12]
--
cnt_index[2:0]
RW
The current counter index
0
19.15
--
cnt_loop_en
RW
The counter index loop enable
1: Each time reading of this register (MII register
19) will increase cnt_index[2:0] by one. The
content will be loop back to “0” after reading if it
is “7”.
0: cnt_index[2:0] is fixed to the setting value.
1
IP113M-DS-R02
May. 19, 2003
39/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Switch configuration register 1 (MII register 20D, EEPROM register 02~03D)
20.0
2.0
mg_auto_crossover
_en
R/W
Select TP to be MDIX or MDI. It is valid only if MII
register16.11 is disabled.
0: MDI
1: MDIX
20.1
2.1
mg_converter_mode
R/W
Pure converter mode enable (DIRECT_WIRE)
Pin (0)
20.2
2.2
mg_cut_through_en
R/W
Modify cut-through mode enable (FAST_FWD)
Pin (0)
20.3
2.3
mg_pass_fragment
_en
R/W
Pass fragment packet (>7B and <64B)
0
20.4
2.4
mg_col16_drop_en
R/W
Collision 16 times drop enable
0
20.5
2.5
mg_col_backoff
_en
R/W
Collision back-off enable
1: back after collision
0: not back off after collision
1
20.6
2.6
mg_bkpress_col
_crs
R/W
Half duplex backpressure mode selection
This bit must be 0 (collision base backpressure)
for normal operation.
0
20.7
2.7
p01_mg_backpress
_en
R/W
TP port backpressure control enable for half
duplex
1
20.8
3.0
mg_rem_ctrl_en
R/W
Remote control enable (TX/RX. ability for
maintenance frame)
1
20.9
3.1
mg_auto_tx_mf_en
R/W
Auto send status frame to remote partner enable
(AUTO_SEND)
Pin (0)
20.10
3.2
mg_auto_tx_ttc
_content
R/W
The content of auto send status frame
1: TTC (TS-1000)
The frame format is defined in TS-1000.
0: ICPLUS
The frame format is similar to the one defined in
TS-1000 except the bit definition of S[15:0].
S[15:0] is the content of MII register 22[15:0].
Local IP113M uses the frame to indicate its
status to the remote IP113M. The remote
IP113M receives the frame and stores the
information to the MII register 23.
1
20.11
3.3
mg_sd_off_way
R/W
Informing way for optical receiving SD off
1: far end fault pattern
0: maintenance frame
1
20.12
3.4
mg_em_bist_en
R/W
SSRAM BIST enable (R/W by EEPROM only)
1
20.13
3.5
mg_nway_limit_en
R/W
This pin overwrites the setting on pin 26
TP_FORCE.
20.14
3.6
mg_receive_en
R/W
TP receive enable
1
20.15
3.7
p02_link_on
RO
Fiber port link status (descramble_locked)
0
40/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
0
Pin (0)
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Switch configuration register 2 (MII register 21D, EEPROM register 04~05D)
21[7:0]
4[7:0]
p01_mg_port
_page_no
R/W
TP port allocated memory pages
The default is 120 pages with 64 bytes per page.
120d
21[15:8]
5[7:0]
p02_mg_port
_page_no
R/W
FX port allocated memory pages
The default is 120 pages with 64 bytes per page.
120d
IP113M-DS-R02
May. 19, 2003
41/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Local MC extended register (MII register 22D, EEPROM register 06~07D)
22.0
6.0
mg_loopback_en
R/W
Loop-back for remote test enable (same as MII
register 0.14)
0
22.1
6.1
mg_status_rpt
_en
RO
TP port status available
0
22.2
6.2
p01_mg_auto
_neg_en
R/W
TP port auto-negotiation enable (same as MII
register 0.12)
1
22.3
6.3
p01_mg_speed
_mode
R/W
TP port speed selection (same as MII register
0.13)
1: 100M, 0:10M
Pin (1)
22.4
6.4
p01_mg_duplex
_mode
R/W
TP port duplex mode selection (same as MII
register 0.8)
1: full duplex, 0:half duplex
Pin (1)
22.5
6.5
p01_mg_flow
_ctrl_en
R/W
TP port flow control selection (same as MII
register 4.10)
1: on, 0:off
Pin (1)
22.6
6.6
p01_mg_link
_status
RO
TP port link status off
1: link off, 0: link ok
22.7
6.7
p02_mg_flow
_ctrl_en
R/W
Fiber port flow control/backpressure enable
22.8
7.0
p02_mg_duplex
_mode
R/W
Fiber port duplex mode (FX_FULL)
1
22.9
7.1
p02_mg_link
_status
RO
Fiber port signal detect (power)
0
22.10
7.2
p02_mg_fef
_detect
RO
Fiber port Far-End-Fault detect
0
22[12:
11]
7[4:3]
p01_mg_throttle
_confg
R/W
TP port input Rate Control
2'b00: full speed
2'b01: 1/4 speed
2'b10: 2/4 speed
2'b11: 3/4 speed
00
22[14:
13]
7[6:5]
p01_mg_throttle
_confg
R/W
TP port output Rate Control
2'b00: full speed
2'b01: 1/4 speed
2'b10: 2/4 speed
2'b11: 3/4 speed
00
22.15
7.7
mg_link_pass_en
R/W
Link Fault Pass through enable (LFP)
42/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
0
Pin (1)
Pin (0)
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Link partner MC extended status register (MII register 23D)
23.0
--
lp_loopback_en
RO
Loop-back for remote test enable
23.1
--
lp_status_rpt_en
RO
Option B support
23.2
--
lp_tp_autoneg_en
RO
TP port auto-negotiation enable
23.3
--
lp_tp_speed_mode
RO
TP port speed selection
23.4
--
lp_tp_duplex_mode
RO
TP port duplex mode selection
23.5
--
lp_tp_flow_ctrl_en
RO
TP port flow control selection
23.6
--
lp_tp_link_off
RO
TP port link off
1: link off,
0:link on
23.7
--
lp_fb_flow_ctrl_en
RO
Fiber port flow control/backpressure enable
23.8
--
lp_fb_duplex_mode
RO
Fiber port duplex mode
23.9
--
lp_fb_link_status
RO
Fiber port signal detect (power) off
1: off,
0: on
23.10
--
lp_fb_fef_detect
RO
Fiber port Far-End-Fault detect
0
23.11
--
lp_power_abnormal
RO
MC power abnormal
0
23.12
--
lp_mc_failed
RO
MC failed
0
23.13
--
lp_sd_off_way
RO
Link Partner informing way of SD off
1: far end fault pattern
0: maintenance frame
0
23.14
--
lp_multi_tp_port
RO
MC support multi-port UTP
0
23.15
--
mg_link_pass_en
RO
Link Fault Pass through enable
0
Note
Note: Only available when MII 20.10 = 0.
IP113M-DS-R02
May. 19, 2003
43/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Remote control Transmit register 1 (MII register 24D)
24.0
--
mg_rem_tx_code
R/W
Remote control frame send trigger
0
24.1
--
mg_rem_tx_code
R/W
Transmitted maintenance direction discriminator
C1
Frame direction
0: upstream
1: downstream
0
24[3:2]
--
mg_rem_tx_code
R/W
Transmitted maintenance frame command
discriminator C3~C2
01: request
11: acknowledge
10: Indication
00: reserved
00
24[11:4]
--
mg_rem_tx_code
R/W
Transmitted maintenance frame control signals
C15~C8
bit11 (C15)
0 0 0 0
0 0 0 0
0 0 0 0
A4 A3 A2 A1
0
0
0
A0
8’b0
bit4 (C8)
0 01: Loop test start
0 00: Loop test finished
0 10: Status indication
RW 11: IP113M R/W registers
RW: 0: read, 1: write
A[4:0]: register address
24[15:12]
--
Reserved
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Remote control Transmit register 2 (MII register 25D)
25[15:0]
--
mg_rem_wt_data
R/W
Remote control write data
If a remote write command is issued, that is, MII
register 24[11:4] is programmed as xxxxx111.
The content in this register will be embedded into
S[15:0] and is sent to the remote site. The
partner IP113M receives the frame (register
write) and update the addressed MII register with
the value defined in this register
44/48
Copyright © 2003, IC Plus Corp.
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Preliminary, Specification subject to change without notice.
16’b0
IP113M-DS-R02
May. 19, 2003
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Remote control Receive register 1 (MII register 26D)
26.0
--
mg_rem_rx_code
RO
RC
Receive a acknowledge or not defined
maintenance frame C0
1: IP113M receives a maintenance frame.
0: no maintenance frame received.
User can poll this bit to make sure a there is a
maintenance frame is received. It is a read and
auto-clear bit.
0
26.1
--
mg_rem_rx_code
RO
Received maintenance direction discriminator C1
0
26[3:2]
--
mg_rem_rx_code
RO
Received maintenance frame command
discriminator C3~C2
00
26[11:4]
--
mg_rem_rx_code
RO
Received maintenance frame control signals
C15~C8
26[12]
--
mg_rem_rx_code
RO
RC
Received maintenance frame CRC error
1: received maintenance frame CRC error.
0: received maintenance frame CRC ok.
It is a read and auto-clear bit.
26[15:13]
--
Reserved
MII
ROM
NAME
R/W
DESCRIPTION
8’b0
DEFAULT
Remote control Receive register 2 (MII register 27D)
27[15:0]
--
mg_rem_rd_data
RO
MII
ROM
NAME
R/W
Remote control read data S0~S15.
DESCRIPTION
16’b0
DEFAULT
Remote control Receive register 3 (MII register 28D)
28[15:0]
--
mg_rem_rd_data
RO
MII
ROM
NAME
R/W
Vender message M0~M15
DESCRIPTION
16’b0
DEFAULT
Remote control Receive register 4 (MII register 29D)
29[15:0]
--
mg_rem_rd_data
RO
MII
ROM
NAME
R/W
Vender message M16~M29
DESCRIPTION
16’b0
DEFAULT
Remote control Receive register 5 (MII register 30D)
30[15:0]
--
IP113M-DS-R02
May. 19, 2003
mg_rem_rd_data
RO
Vender message M30~M55
45/48
16’b0
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Switch configuration register 3 (MII register 31D)
31.0
--
software_reset
R/W
SC
Switch software reset
It is a self-clear bit.
0
31.1
--
mg_power_indicate
_disable
R/W
IP113M power abnormal indication disable
0
31[3:2]
--
link_list_fail
RO
Link list failure indication
bit[2] : TP port link list abnormal
bit[3] : Fiber port link list abnormal
00
31[5:4]
--
BIST_status
RO
BIST Status of embedded SSRAM
bit[4] : memory is under testing
bit[5] : memory test result is good when testing
over
01
31[6]
--
mg_auto_loopback
_test
R/W
Auto loopback test enable
1: enable, 0:disable
0
31[7]
--
mg_t2_timer
_disable
R/W
Loopback test T2 timer disable (TS-1000)
1: The MC will not send loopback end indication
MF when T2 timer expired
0: The MC will send loopback end MF when T2
timer expired
0
31[8]
--
mg_auto_loopback
_complete
RO
Auto loopback test complete
1: completed, 0: still testing
0
31[9]
--
mg_auto_loopback
_ok
Auto loopback test OK
1: good, 0: not good
0
31[15:10]
--
Reserved
46/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003
IP113M
9. Signal Requirements
9.1.
Absolute Maximum Rating
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Functional performance and device reliability are not guaranteed under these conditions. All voltages are
specified with respect to GND.
Supply Voltage
–0.3V to 2.645V
Input Voltage
–0.3V to 5.0V
Output Voltage
–0.3V to 5.0V
Storage Temperature
-55°C to 150°C
Ambient Operating Temperature (Ta)
0°C to 70°C
9.2.
DC Characteristic
Operating Conditions
Parameter
Supply Voltage
Operation Junction Temperature
Sym.
VCC
Tj
Min.
2.375
Power Consumption
Typ.
2.5
TBD
Max.
2.645
Unit
V
°C
W
0.475
Conditions
VCC=2.5v
Input Clock
Parameter
Sym.
Min.
Frequency
Frequency Tolerance
I/O Electrical Characteristics
Parameter
Input Low Voltage
Typ.
25
-50
Sym.
VIL
Min.
Input High Voltage
VIH
2.0
Output Low Voltage
VOL
Output High Voltage
VOH
Typ.
Max.
Unit
MHz
+50
PPM
Max.
0.8
Unit
V
Conditions
Conditions
V
0.4
2.4
V
IOH=4mA
V
IOL=4mA
10. Order Information
Part No.
PIN
Notice
IP113M
48 PIN LQFP
-
IP113M-DS-R02
May. 19, 2003
47/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M
11. Package Detail
48
37
1
36
D
PH
12
25
13
HE
24
"E"
b 12"
e
A
A2
GAUGE PLANE
θ
A1
F y
c
F
SEATING
PLANE
D
0.254
12"
L
E
L1
DETAIL "E"
13
24
unit
mm
inch
1.600MAX.
0.050~0.150
1.400 + 0.05
0.0630MAX.
0.0020~0.0059
0.0551 + 0.0020
0.200TYP
0.0078TYP
c
D
E
0.127TYP
7.000 + 0.100
7.000 + 0.100
-
0.0050TYP
0.2756 + 0.0039
0.2756 + 0.0039
e
Hd
0.500TYP
9.000 + 0.250
9.000 + 0.250
0.0196TYP
0.3543 + 0.0098
0.3543 + 0.0098
1.000REF
0.100MAX.
0"~7"
0.0393REF
0.0039MAX.
0"~7"
Symbol
12
A
A1
25
2
A2
b
2
1
He
L
36
48
L1
y
e
37
-
0.600 +
- 0.150
-
-
0.0236 +
- 0.006
Notes:
1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSION.
2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION / INTRUSION.
3. MAX. END FLASH IS 0.15MM.
4. MAX. DAMBAR PROTRUSION IS 0.13MM.
GENERAL APPEARANCE SPEC SHOULD BE BASED ON FINAL VISUAL INSPECTION SPEC.
IC Plus Corp.
Headquarter
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL : 886-3-575-0275
FAX : 886-3-575-0475
Website : www.icplus.com.tw
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL : 886-2-2696-1669
FAX : 886-2-2696-2220
48/48
Copyright © 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP113M-DS-R02
May. 19, 2003