NTHS2101P 8.0 V, P−Channel Power MOSFET ChipFET Single Package Features • Offers an Ultra Low RDS(on) Solution in the ChipFET Package • Miniature ChipFET Package 40% Smaller Footprint than TSOP−6 • • • • making it an Ideal Device for Applications where Board Space is at a Premium Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the Operating Voltage used in many Logic ICs in Portable Electronics Simplifies Circuit Design since Additional Boost Circuits for Gate Voltages are not Required Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology http://onsemi.com V(BR)DSS Ultra Low RDS(on) TYP ID MAX 19 m @ −4.5 VGS 8.0 V 5.4 A 25 m @ −2.5 VGS 34 m @ −1.8 VGS S G Applications • Optimized for Battery and Load Management Applications in • • Portable Equipment such as MP3 Players, Cell Phones, Digital Cameras, Personal Digital Assistant and other Portable Applications Charge Control in Battery Chargers Buck and Boost Converters D P−Channel MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS −8.0 Vdc Gate−to−Source Voltage − Continuous VGS 8.0 Vdc Drain Current − Continuous − 5 seconds ID ID −5.4 −7.5 A PIN CONNECTIONS Total Power Dissipation Continuous @ TA = 25°C (5 sec) @ TA = 25°C Continuous @ 85°C (5 sec) @ 85°C PD W D 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 Continuous Source Current Is −1.1 S 5 4 G 4 RJA RJA 50 95 TL 260 Rating Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds A °C/W °C C4 d MARKING DIAGRAM C4 d Thermal Resistance (Note 1) Junction−to−Ambient, 5 sec Junction−to−Ambient, Continuous 1.3 2.5 0.7 1.3 ChipFET CASE 1206A STYLE 1 6 5 = Specific Device Code = Date Code ORDERING INFORMATION Device Package Shipping† NTHS2101PT1 ChipFET 3000/Tape & Reel 1. When surface mounted to a 1″ x 1″ FR4 board. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2003 December, 2003 − Rev. 0 1 Publication Order Number: NTHS2101P/D NTHS2101P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit V(Br)DSS VGS = 0 Vdc, ID = −250 Adc −8.0 − − Vdc Gate−Body Leakage Current Zero IGSS VDS = 0 Vdc, VGS = 8.0 Vdc − − 100 nAdc Zero Gate Voltage Drain Current IDSS VDS = −6.4 Vdc, VGS = 0 Vdc VDS = −6.4 Vdc, VGS = 0 Vdc, TJ = 85°C − − − − −1.0 −5.0 Adc Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 Adc −0.45 − −1.5 Vdc Static Drain−to−Source On−Resistance RDS(on) VGS = −4.5 Vdc, ID = −5.4 Adc VGS = −2.5 Vdc, ID = −4.5 Adc VGS = −1.8 Vdc, ID = −2.0 Adc − − − 19 25 34 25 36 48 m Forward Transconductance gFS VDS = −5.0 Vdc, ID = −5.2 Adc − 20 − S Diode Forward Voltage VSD IS = −1.1 Adc, VGS = 0 Vdc − −0.62 −1.2 V Input Capacitance Ciss 2400 − pF Coss VDS = −6.4 Vdc VGS = 0 V f = 1.0 1 0 MHz − Output Capacitance − 550 − Transfer Capacitance Crss − 420 − − 7.0 − − 28 − − 73 − − 60 − − 15 30 − 4.0 − − 8.0 − − 90 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 2) Temperature Coefficient (Positive) ON CHARACTERISTICS (Note 2) DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge VDD = −6.4 Vdc VGS = −4.5 Vdc ID = −5 −5.4 4 Adc RG = 2.0 (Note 2) td(on) tr td(off) tf Qg Qgd VGS = −2.5 Vdc ID = −5.4 Adc VDS = −6.4 Vdc Trr IF = −1.1 A, di/dt = 100 A/s Qgs Source−Drain Reverse Recovery Time 2. Pulse Test: Pulse Width = 250 s, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns nC ns NTHS2101P VGS = −8 thru −2.4 V 16 −2 V −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) TYPICAL ELECTRICAL CHARACTERISTICS TJ = 25°C 12 −1.8 V 8 −1.6 V 4 −1.4 V 16 12 8 TJ = 100°C 4 TJ = −55°C 0 0 0 1 2 3 4 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 6 0.5 1.0 1.5 2.0 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.10 VGS = −1.8 V 0.08 0.06 0.04 VGS = −2.5 V 0.02 VGS = −4.5 V 0 4 6 8 10 12 14 16 −ID, DRAIN CURRENT (A) 18 20 1.6 VGS = −4.5 V 1.4 1.2 1.0 0.8 0.6 −50 Figure 3. On−Resistance versus Drain Current and Gate Voltage −25 0 25 50 125 75 100 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 4. On−Resistance Variation with Temperature 10,000 5000 TJ = 125°C 4500 TJ = 100°C 1000 C, CAPACITANCE (pF) −IDSS, LEAKAGE (nA) 3.0 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE () Figure 1. On−Region Characteristics 2 TJ = 25°C 100 VGS = 0 V 10 Ciss TJ = 25°C Crss Ciss 4000 3500 3000 2500 2000 1500 1000 1 Coss Crss 500 0 0 2 4 6 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 8 8 6 4 2 0 2 4 6 8 −VGS −VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. Drain−to−Source Leakage Current versus Voltage Figure 6. Capacitance Variation http://onsemi.com 3 NTHS2101P 8 QT 7 4 6 −VGS 3 5 4 Q1 2 Q2 3 2 1 ID = 5.4 A TJ = 25°C 1 0 0 0 3 12 6 9 Qg, TOTAL GATE CHARGE (nC) 15 1000 VDD = −6.4 V ID = −5.4 A VGS = −4.5 V t, TIME (ns) 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS td(off) tf tr 100 td(on) 10 1 1 Figure 7. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE () 100 Figure 8. Resistive Switching Time Variation versus Gate Resistance −IS, SOURCE CURRENT (AMPS) 5 VGS = 0 V TJ = 25°C 4 3 2 1 0 0.4 0.5 0.6 0.7 −VSD, SOURCE−TO−DRAIN VOLTAGE (V) 0.8 NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 9. Diode Forward Voltage versus Current 2 1 Duty Cycle = 0.5 Notes: 0.2 PDM t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80°C/W 3. TJM − TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 0.01 10−4 Single Pulse 10−3 10−2 10 −1 1 SQUARE WAVE PULSE DURATION (sec) 10 Figure 10. Normalized Thermal Transient Impedance, Junction−to−Ambient http://onsemi.com 4 100 600 NTHS2101P PACKAGE DIMENSIONS ChipFET CASE 1206A−03 ISSUE E A 8 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A−01 AND 1206A−02 OBSOLETE. NEW STANDARD IS 1206A−03. M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 4 L D J G DIM A B C D G J K L M S C 0.05 (0.002) STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 2.00 1.80 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 0.178 0.007 0.711 0.028 mm inches 0.66 0.026 Figure 11. Basic Figure 12. Style 1 http://onsemi.com 5 mm inches NTHS2101P ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 6 For additional information, please contact your local Sales Representative. NTHS2101P/D