DM54S195/DM74S195 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of operation: Parallel (broadside) load Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T-type flip-flop as shown in the truth table. The high-performance S195, with a 105 MHz typical shift frequency, is particularly attractive for very high-speed data processing systems. In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register. Features Y Y Y Y Y Y Y Y Y Synchronous parallel load Positive-edge-triggered clocking Parallel inputs and outputs from each flip-flop Direct overriding clear J and K inputs to first stage Complementary outputs from last stage For use in high-performance: accumulators/processors serial-to-parallel, parallel-to-serial converters Typical clock frequency 105 MHz Typical power dissipation 350 mW Connection Diagram Dual-In-Line Package TL/F/6476 – 1 Order Number DM54S195J or DM74S195N See NS Package Number J16A or N16E C1995 National Semiconductor Corporation TL/F/6476 RRD-B30M105/Printed in U. S. A. DM54S195/DM74S195 4-Bit Parallel Access Shift Registers June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54S DM74S 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54S195 Parameter DM74S195 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.8 0.8 V IOH High Level Output Current b1 b1 mA IOL Low Level Output Current fCLK Clock Frequency (Note 1) fCLK Clock Frequency (Note 2) tW Pulse Width (Note 3) tSU 2 2 105 70 0 90 60 20 mA 0 105 70 MHz 0 90 60 MHz 7 7 Clear 12 12 Shift/Load 11 11 Data 5 5 Setup Time (Note 3) Clock tH Data Hold Time (Note 3) 3 3 tREL Shift/Load Release Time (Note 3) 6 6 Clear Release Time (Note 3) 9 9 TA V 20 0 Free Air Operating Temperature b 55 125 V ns ns ns ns 0 70 §C Note 1: CL e 15 pF, RL e 280X, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 280X, TA e 25§ C and VCC e 5V. Note 3: TA e 25§ C and VCC e 5V. Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Min Typ (Note 4) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.2 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.7V 50 mA IIL Low Level Input Current b2 mA IOS Short Circuit Output Current VCC e Max, VI e 0.5V VCC e Max (Note 5) Supply Current VCC e Max (Note 6) ICC V 0.5 V 1 mA DM54 b 40 b 100 DM74 b 40 b 100 70 109 mA mA Note 4: All typicals are at VCC e 5V, TA e 25§ C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: With all inputs open, SHIFT/LOAD grounded, and 4.5V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, then 4.5V to the CLEAR and then applying a momentary ground then 4.5V to the CLOCK. 2 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 280X Symbol From (Input) To (Output) Parameter CL e 15 pF Min Max CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Any Q 12 15 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q 16.5 20 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q 18.5 23 ns 70 60 MHz Function Table Inputs Clear L H H H H H H Shift/ Load Clock X L H H H H H X u L u u u u Outputs Serial Parallel J K A B C D X X X L L H H X X X H L H L X a X X X X X X b X X X X X X c X X X X X X d X X X X X QA QB QC QD QD L a QA0 QA0 L H QAn L b QB0 QA0 QAn QAn QAn L c QC0 QBn QBn QBn QBn L d QD0 QCn QCn QCn QCn H d QD0 QCn QCn QCn QCn H e High Level (steady state), L e Low Level (steady state), X e Don’t Care (any input, including transitions) u e Transition from low to high level a, b, c, d e The level of steady state input at A, B, C, or D, respectively. QA0, QB0, QC0, QD0 e The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn e The level of QA, QB, QC, respectively, before the most recent transition of the clock. Logic Diagram TL/F/6476 – 2 3 Timing Diagram Typical Clear, Shift, and Load Sequences TL/F/6476 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54S195J NS Package Number J16A 5 DM54S195/DM74S195 4-Bit Parallel Access Shift Registers Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74S195N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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