Revised April 1999 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear General Description The VHCT74A is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Features ■ High speed: fMAX = 160 MHz (typ) at TA = 25°C ■ High noise immunity: VIH = 2.0V, VIL = 0.8V ■ Power down protection is provided on all inputs and outputs ■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C ■ Pin and function compatible with 74HCT74 Ordering Code: Order Number Package Number 74VHCT74AM 74VHCT74ASJ 74VHCT74AMTC 74VHCT74AN M14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol IEEE/IEC Pin Descriptions Pin Names Truth Table Description D1, D2 Data Inputs CK1, CK2 Inputs Outputs Function CLR PR Clock Pulse Inputs L H X CLR1, CLR2 Direct Clear Inputs H L X PR1, PR2 Direct Preset Inputs H H L H Q1, Q1, Q2, Q2 Outputs © 1999 Fairchild Semiconductor Corporation DS500026.prf D L L X H H L H H H H H X CK Q Q X L H Clear X H L Preset X H L Qn Qn No Change www.fairchildsemi.com 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear July 1997 74VHCT74A Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 5) DC Output Voltage (VOUT ) Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VIN) 0V to +5.5V (Note 2) −0.5V to VCC + 0.5V (Note 3) −0.5V to 7.0V (Note 2) 0V to VCC −20 mA (Note 3) 0V to 5.5V Input Diode Current (IIK) Output Voltage (VOUT) Output Diode Current (IOK) −40°C to +85°C Operating Temperature (TOPR) ±20 mA (Note 4) DC Output Current (IOUT) ±25 mA DC VCC/GND Current (ICC ) ±50 mA Input Rise and Fall Time (tr, tf) VCC = 5.0V ± 0.5V −65°C to +150°C Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 0 ns/V ∼ 20 ns/V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 3: VCC = 0V. Note 4: VOUT < GND, VOUT > VCC.(Outputs Active) Note 5: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL TA = 25°C TA = −40°C to +85°C VCC (V) Min HIGH Level 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Parameter Typ Max Min Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level 4.5 4.40 4.5 3.94 4.50 4.40 V V 3.80 VIN = VIH IOH = −50 µA or VIL IOH = −8 mA VIN = VIH IOL = 50 µA LOW Level 4.5 0.1 0.1 Output Voltage 4.5 0.36 0.44 0–5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 2.0 20.0 µA VIN = VCC or GND 5.5 1.35 1.50 mA 0.0 +0.5 +5.0 µA IIN Input Leakage Current ICC Quiescent Supply Current ICCT Maximum ICC/Input IOFF Output Leakage Current 0.0 Conditions V LOW Level Output Voltage Units (Power Down State) www.fairchildsemi.com 2 V or VIL IOL = 8 mA VIN = 3.4V Other Inputs = VCC or GND VOUT = 5.5V Symbol Parameter VCC (V) (Note 6) TA = 25°C Min Typ TA = −40°C to +85°C Max Min Max Maximum Clock 5.0 100 160 80 Frequency 5.0 80 140 65 tPLH Propagation Delay Time 5.0 5.8 7.8 1.0 9.0 tPHL (CK-Q, Q) 5.0 6.3 8.8 1.0 10.0 tPLH Propagation Delay time 5.0 7.6 10.4 1.0 12.0 tPHL (CLR, PR -Q, Q) 5.0 8.1 11.4 1.0 13.0 CIN Input Capacitance 4 10 CPD Power Dissipation Capacitance 24 fMAX Units MHz 10 Conditions CL = 15 pF CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF pF VCC = Open pF (Note 7) Note 6: VCC is 5.0 ± 0.5V Note 7: CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD × VCC × fIN + ICC/2 (per flip-flop). AC Operating Requirements Symbol tW(L) Parameter Minimum Pulse Width (CK) tW(H) tW(L) Minimum Pulse Width (CLR, PR) VCC (V) TA = 25°C Typ TA = −40°C to +85°C Units Guaranteed Minimum 5.0 ± 0.5 5.0 5.0 ns 5.0 ± 0.5 5.0 5.0 ns tS Minimum Setup Time 5.0 ± 0.5 5.0 5.0 ns tH Minimum Hold Time 5.0 ± 0.5 0 0 ns tREM Minimum Removal Time 5.0 ± 0.5 3.5 3.5 ns (CLR, PR) 3 www.fairchildsemi.com 74VHCT74A AC Electrical Characteristics 74VHCT74A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 4 74VHCT74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 5 www.fairchildsemi.com 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.