ETC UPD464536ALS1-A55

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD464518AL, 464536AL
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
LVTTL INTERFACE/REGISTER-LATCH/LATE WRITE
Description
The µPD464518AL is a 262,144 words by 18 bits, and the µPD464536AL is a 131,072 words by 36 bits
synchronous static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the µPD464518AL and µPD464536AL a high-speed device.
The µPD464518AL and µPD464536AL are suitable for applications which require high-speed, low voltage, highdensity memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
• Register to latch synchronous operation
• LVTTL 3.3 V Input / Output levels
• Fast clock access time : 5.5 ns / 182 MHz, 6.0 ns / 166 MHz, 7.0 ns / 143 MHz
• Asynchronous output enable control : /G
• Single differential clock inputs
• Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
• Common I/O using three-state outputs
• Internally self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• Boundary scan (JTAG) IEEE 1149.1 compatible
• Single +3.3 V power supply
• Sleep mode : ZZ(Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
µPD464518ALS1-A55
5.5 ns
182 MHz
119-pin plastic BGA
µPD464518ALS1-A6
6.0 ns
166 MHz
µPD464518ALS1-A7
7.0 ns
143 MHz
µPD464536ALS1-A55
5.5 ns
182 MHz
µPD464536ALS1-A6
6.0 ns
166 MHz
µPD464536ALS1-A7
7.0 ns
143 MHz
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13609EJ4V0DS00 (4th edition)
Date Published January 2001 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1999
µPD464518AL, 464536AL
Pin Configurations
/xxx indicates active low signal.
119-pin Plastic BGA (256K Words by 18 Bits Pin Assignment)
[µPD464518ALS1]
Bottom View
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
7 6 5 4 3 2 1
2
7
6
5
4
3
2
1
1
2
3
4
5
6
7
VDDQ
SA2
SA6
NC
SA9
SA12
VDDQ
A
VDDQ
SA12
SA9
NC
SA6
SA2
VDDQ
NC
NC
SA16
NC
SA17
NC
NC
B
NC
NC
SA17
NC
SA16
NC
NC
NC
SA3
SA7
VDD
SA10
SA13
NC
C
NC
SA13
SA10
VDD
SA7
SA3
NC
NC
DQa9
VSS
NC
VSS
NC
DQb1
D
DQb1
NC
VSS
NC
VSS
DQa9
NC
DQa8
NC
VSS
/SS
VSS
DQb2
NC
E
NC
DQb2
VSS
/SS
VSS
NC
DQa8
VDDQ
DQa7
VSS
/G
VSS
NC
VDDQ
F
VDDQ
NC
VSS
/G
VSS
DQa7
VDDQ
DQa6
NC
VSS
NC
/SBb
DQb3
NC
G
NC
DQb3
/SBb
NC
VSS
NC
DQa6
NC
DQa5
VSS
NC
VSS
NC
DQb4
H
DQb4
NC
VSS
NC
VSS
DQa5
NC
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
DQa4
NC
VSS
K
VSS
DQb5
NC
K
NC
DQb5
VSS
K
VSS
NC
DQa4
NC
DQa3
/SBa
/K
VSS
NC
DQb6
L
DQb6
NC
VSS
/K
/SBa
DQa3
NC
VDDQ
NC
VSS
/SW
VSS
DQb7
VDDQ
M
VDDQ
DQb7
VSS
/SW
VSS
NC
VDDQ
NC
DQa2
VSS
SA1
VSS
NC
DQb8
N
DQb8
NC
VSS
SA1
VSS
DQa2
NC
DQa1
NC
VSS
SA0
VSS
DQb9
NC
P
NC
DQb9
VSS
SA0
VSS
NC
DQa1
NC
SA4
VSS
VDD
VDD
SA14
NC
R
NC
SA14
VDD
VDD
VSS
SA4
NC
ZZ
SA5
SA8
NC
SA11
SA15
NC
T
NC
SA15
SA11
NC
SA8
SA5
ZZ
VDDQ
NC
TDO
TCK
TDI
TMS
VDDQ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
Pin Name and Functions [µPD464518ALS1]
Pin name
Description
Function
VDD
Core Power Supply
Supplies power for RAM core
VSS
Ground
VDDQ
Output Power Supply
K, /K
Main Clock Input
SA0 to SA17
Synchronous Address Input
DQa1 to DQb9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Sleep Mode Enable
Enables sleep mode, active high
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Supplies power for output buffers
Data Sheet M13609EJ4V0DS
3
µPD464518AL, 464536AL
119-pin plastic BGA (128K Words by 36 Bits Pin Assignment)
[ µPD464536ALS1 ]
Bottom View
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
7 6 5 4 3 2 1
4
7
6
5
4
3
2
1
1
2
3
4
5
6
7
VDDQ
SA2
SA5
NC
SA9
SA12
VDDQ
A
VDDQ
SA12
SA9
NC
SA5
SA2
VDDQ
NC
NC
SA15
NC
SA16
NC
NC
B
NC
NC
SA16
NC
SA15
NC
NC
NC
SA3
SA6
VDD
SA10
SA13
NC
C
NC
SA13
SA10
VDD
SA6
SA3
NC
DQb8
DQb9
VSS
NC
VSS
DQc9
DQc8
D
DQc8
DQc9
VSS
NC
VSS
DQb9
DQb8
DQb6
DQb7
VSS
/SS
VSS
DQc7
DQc6
E
DQc6
DQc7
VSS
/SS
VSS
DQb7
DQb6
VDDQ
DQb5
VSS
/G
VSS
DQc5
VDDQ
F
VDDQ
DQc5
VSS
/G
VSS
DQb5
VDDQ
DQb3
DQb4
/SBb
NC
/SBc
DQc4
DQc3
G
DQc3
DQc4
/SBc
NC
/SBb
DQb4
DQb3
DQb1
DQb2
VSS
NC
VSS
DQc2
DQc1
H
DQc1
DQc2
VSS
NC
VSS
DQb2
DQb1
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
DQa1
DQa2
VSS
K
VSS
DQd2
DQd1
K
DQd1
DQd2
VSS
K
VSS
DQa2
DQa1
DQa3
DQa4
/SBa
/K
/SBd
DQd4
DQd3
L
DQd3
DQd4
/SBd
/K
/SBa
DQa4
DQa3
VDDQ
DQa5
VSS
/SW
VSS
DQd5
VDDQ
M
VDDQ
DQd5
VSS
/SW
VSS
DQa5
VDDQ
DQa6
DQa7
VSS
SA1
VSS
DQd7
DQd6
N
DQd6
DQd7
VSS
SA1
VSS
DQa7
DQa6
DQa8
DQa9
VSS
SA0
VSS
DQd9
DQd8
P
DQd8
DQd9
VSS
SA0
VSS
DQa9
DQa8
NC
SA4
VSS
VDD
VDD
SA14
NC
R
NC
SA14
VDD
VDD
VSS
SA4
NC
ZZ
NC
SA7
SA8
SA11
NC
NC
T
NC
NC
SA11
SA8
SA7
NC
ZZ
VDDQ
NC
TDO
TCK
TDI
TMS
VDDQ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
Pin Name and Functions [µPD464536ALS1]
Pin name
Description
Function
VDD
Core Power Supply
Supplies power for RAM core
VSS
Ground
VDDQ
Output Power Supply
K, /K
Main Clock
SA0 to SA16
Synchronous Address Input
DQa1 to DQd9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/SBc
Synchronous Byte "c" Write Enable
Write DQc1 to DQc9
/SBd
Synchronous Byte "d" Write Enable
Write DQd1 to DQd9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Sleep Mode Enable
Enables sleep mode, active high
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Supplies power for output buffers
Data Sheet M13609EJ4V0DS
5
µPD464518AL, 464536AL
Late Write Block Diagram
SA0 to SA17
K
Address
register
K
/K
Mux
Write address
register
/K
/SS
/SS
Write
clock
genelator
/SW
/SW
/SBa
/SBa
Write
control
logic
/SBb
/SBb
/SBc
/SBc
/SBd
/SBd
DQ
6
/G
ZZ
ZZ
Read
comp.
Data Data
in
out
Mux
Data
in
register
/G
Memory
array
Output
latch
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
Synchronous Truth Table
DQa1–9 DQb1–9 DQc1–9 DQd1–9
Power
ZZ
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Mode
L
H
×
×
×
×
×
Not selected
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
L
L
H
×
×
×
×
Read
Dout
Dout
Dout
Dout
Active
L
L
L
L
L
L
L
Write
Din
Din
Din
Din
Active
L
L
L
L
H
H
H
Write
Din
Hi-Z
Hi-Z
Hi-Z
Active
L
L
L
H
L
L
L
Write
Hi-Z
Din
Din
Din
Active
H
×
×
×
×
×
×
Sleep Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Standby
Remark × : Don’t care
Output Enable Truth Table
Mode
/G
DQ
Read
L
Dout
Read
H
Hi-Z
Sleep (ZZ=H)
×
Hi-Z
Write (/SW=L)
×
Hi-Z
Deselect (/SS=H)
×
Hi-Z
Remark × : Don’t care
Data Sheet M13609EJ4V0DS
7
µPD464518AL, 464536AL
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Condition
MIN.
TYP.
MAX.
Unit
Note
VDD
–0.5
+4
V
1
VDDQ
–0.5
+4
V
1
Input voltage
VIN
–0.5
VDD+0.5
V
1
Input / Output voltage
VI/O
–0.5
VDD+0.5
V
1
Operating temperature
Tj
5
110
°C
2
Tstg
–55
+125
°C
Output supply voltage
Storage temperature
Notes 1. –1.0 V MIN. (Pulse width 10% Tcyc)
2. Tj = Junction temperature
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (Tj = 5 to 110 °C)
Parameter
Symbol
Core supply voltage
Output buffer supply voltage
Conditions
MIN.
TYP.
MAX.
Unit
VDD
3.15
3.3
3.45
V
VDDQ
3.15
3.3
3.45
V
+0.8
V
–0.3
Note
Low level input voltage
VIL
High level input voltage
VIH
2.0
VDD+0.3
V
Clock input differential voltage
VDIF (DC)
0.2
VDD+0.6
V
Clock input common mode voltage range
VCM (DC)
1.3
2.1
V
Note –1.0 V MIN. (Pulse width 10% Tcyc)
Remark VDIF(DC) and VCM(DC) are as follows:
VDDQ
VDIF(DC)
VCM(DC)
VSS
Capacitance (TA = 25°°C, f = 1 MHz)
Parameter
Note
Symbol
Test conditions
MAX.
Unit
Input capacitance
CIN
VIN = 0 V
6
pF
Input / Output capacitance
CI/O
VI/O = 0 V
7
pF
Note These parameters are sampled and not 100% tested.
8
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit Note
Input leakage current
ILI
VIN = 0 to VDD
–5
+5
µA
DQ leakage current
ILO
VI/O = 0 to VDDQ, /SS = VIH or /G = VIH
–5
+5
µA
Operating supply current
ICC
/SS = VIL
µPD464518AL
450
mA
cycle = 182 MHz, IDQ = 0 mA
µPD464536AL
650
Sleep mode power supply
ISBZZ
ZZ = VIH, All other inputs = VIH or VIL
45
mA
mA
cycle = DC, IDQ = 0 mA
current
Power supply standby current
ISBSS
VIN = VIH or VIL, /SS = VIH, ZZ = VIL
µPD464518AL
430
cycle = 182 MHz, IDQ = 0 mA
µPD464536AL
630
Low level output voltage
VOL
IOL = 8 mA
0.4
High level output voltage
VOH
IOH = –5 mA
2.4
V
1
V
1
Note 1. See figure.
50 Ω
VDDQ / 2
DQ (Output)
5 pF
Data Sheet M13609EJ4V0DS
9
µPD464518AL, 464536AL
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
Input waveform (rise / fall time = 0.5 ns (20 to 80%))
K, /K signals
2.3 V
cross
point
Test Points
cross
point
1.6 V
Other signals
3.0 V
Test Points
1.5 V
1.5 V
0V
Output waveform
Test Points
1.5 V
1.5 V
Output load
ZO = 50 Ω
DQ (Output)
50 Ω
50 Ω
VDDQ / 2
VDDQ / 2
DQ (Output)
5 pF
10
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
Single Differential Clock, Registered Input / Latched Output Mode
Parameter
Symbol
-A55 (182 MHz)
-A6 (166 MHz)
-A7 (143 MHz)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Clock cycle time
tKHKH
5.5
–
6.0
–
7.0
–
ns
Clock phase time
tKHKL /tKLKH
1.8
–
2.0
–
2.5
–
ns
Address
tAVKH
0.5
–
0.5
–
0.5
–
ns
Write data
tDVKH
Write enable
tWVKH
Chip select
tSVKH
Address
tKHAX
1.0
–
1.0
–
1.0
–
ns
Write data
tKHDX
Write enable
tKHWX
Chip select
tKHSX
Setup times
Hold times
Notes
Clock access time
tKHQV
–
5.5
–
6.0
–
7.0
ns
1
K low to Q valid
tKLQV
–
3.0
–
3.0
–
3.5
ns
1
K low to Q change
tKLQX
0.7
–
0.7
–
0.7
–
ns
1
/G low to Q valid
tGLQV
–
3.0
–
3.0
–
3.5
ns
1
/G low to Q change
tGLQX
0.7
–
0.7
–
0.7
–
ns
1
/G high to Q Hi-Z
tGHQZ
0.7
3.0
0.7
3.0
0.7
3.5
ns
2
K high to Q Hi-Z
tKHQZ
0.7
3.0
0.7
3.0
0.7
3.5
ns
2
K low to Q Lo-Z
tKLQX2
0.7
–
0.7
–
0.7
–
ns
2
Sleep Mode Recovery
tZZR
5.5
–
6.0
–
7.0
–
ns
Sleep Mode Enable
tZZE
–
5.5
–
6.0
–
7.0
ns
Notes 1. See figure.
ZO = 50 Ω
50 Ω
VDDQ / 2
DQ (Output)
2. See figure.
50 Ω
VDDQ / 2
DQ (Output)
5 pF
Data Sheet M13609EJ4V0DS
11
12
Read Operation
/K
K
tKHAX
tKHKH
tKHKL
tKLKH
tAVKH
Address
a
b
c
d
e
f
g
h
i
j
k
tKHSX
Data Sheet M13609EJ4V0DS
tSVKH
/SS
tKHWX
tWVKH
/SW
/G
DQ
Qb
Qa
tKLQX
tKHQV
tKLQV
Qc
tKHQZ
tGLQV
Qe
Qf
Qg
tKLQX2
Qi
µPD464518AL, 464536AL
tGLQX
tGHQZ
Write Operation
/K
K
tKHAX
tKHKH
tKHKL
tKLKH
tAVKH
Address
l
m
n
o
p
q
r
s
t
u
v
tKHSX
Data Sheet M13609EJ4V0DS
tSVKH
/SS
tKHWX
tWVKH
/SW
/G
tGLQX
DQ
Ql
tGLQV
Qm
tKHQZ
Qp
Dn
tDVKH
tKHDX
Qq
Qr
tKLQX2
Ds
Qt
13
µPD464518AL, 464536AL
tGHQZ
14
Sleep Mode
/K
K
Data Sheet M13609EJ4V0DS
Address
a
b
c
d
e
f
g
h
i
j
l
k
/SS
/ZZ
DQ
Qa
Qb
Qc
tZZR
Qj
µPD464518AL, 464536AL
tZZE
µPD464518AL, 464536AL
JTAG Specification
The µPD464518AL and µPD464536AL support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin Name
Pin Assignments
Description
TCK
4U
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
2U
Test Mode Select. This is the command input for the TAP controller state machine.
TDI
3U
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-mined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
5U
Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (Tj = 5 to 110 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
JTAG input high voltage
VIH
2.2
VDD+0.3
V
JTAG input low voltage
VIL
–0.3
+0.8
V
JTAG output high voltage
VOH
IOH = –8 mA
2.4
–
V
JTAG output low voltage
VOL
IOL = 8 mA
–
0.4
V
Data Sheet M13609EJ4V0DS
Note
15
µPD464518AL, 464536AL
JTAG AC Test Conditions (Tj = 5 to 110 °C)
Input waveform (rise / fall time = 1 ns (20 to 80 %))
3.0 V
1.5 V
Test Points
1.5 V
0V
Output waveform
1.5 V
Test Points
1.5 V
Output load (VTT=1.5 V)
VTT
50 Ω
ZO = 50 Ω
TDO
16
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
JTAG AC Characteristics (Tj = 5 to 110 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock cycle time (TCK)
tTHTH
100
–
ns
Clock phase time (TCK)
tTHTL / tTLTH
40
–
ns
Setup time (TMS / TDI)
tMVTH / tDVTH
10
–
ns
Hold time (TMS / TDI)
tTHMX / tTHDX
10
–
ns
tTLQV
–
20
ns
TCK low to TDO valid (TDO)
Note
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTHDX
tTLQV
TDO
Data Sheet M13609EJ4V0DS
17
µPD464518AL, 464536AL
Scan Register Definition (1)
Register name
Instruction register
Description
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction
register. The register is then placed between the TDI and TDO pins when the controller is moved
into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the
input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
µPD464518AL
µPD464536AL
Unit
Instruction register
3
3
bit
Bypass register
1
1
bit
ID register
32
32
bit
Boundary register
51
70
bit
Register name
ID Register Definition
Part number
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no.
ID [0] fix bit
µPD464518AL
256K x 18
XXXX
0110001011 101000
00010010000
1
µPD464536AL
128K x 36
XXXX
0110101100 101000
00010010000
1
18
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
SCAN Exit Order
[ µPD464518AL (256K words by 18 bits) ]
[ µPD464536AL (128K words by 36 bits) ]
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
1
M2
5R
26
SA17
3B
1
M2
5R
36
SA16
3B
2
SA5
6T
27
NC
2B
37
NC
2B
3
SA0
4P
28
SA9
3A
2
SA0
4P
38
SA9
3A
29
SA10
3C
3
SA8
4T
39
SA10
3C
4
SA4
6R
30
SA13
2C
4
SA4
6R
40
SA13
2C
5
SA8
5T
31
SA12
2A
5
SA7
5T
41
SA12
2A
6
ZZ
7T
6
ZZ
7T
42
DQc9
2D
7
DQa1
7P
8
DQa2
6N
32
DQb1
1D
7
DQa9
6P
43
DQc8
1D
33
DQb2
2E
8
DQa8
7P
44
DQc7
2E
9
DQa7
6N
45
DQc6
1E
10
DQa6
7N
46
DQc5
2F
11
DQa5
6M
47
DQc4
2G
12
DQa4
6L
48
DQc3
1G
13
DQa3
7L
49
DQc2
2H
34
9
DQa3
DQb3
2G
6L
35
DQb4
1H
14
DQa2
6K
50
DQc1
1H
10
DQa4
7K
36
/SBb
3G
15
DQa1
7K
51
/SBc
3G
11
/SBa
5L
37
NC
4D
16
/SBa
5L
52
NC
4D
12
/K
4L
38
/SS
4E
17
/K
4L
53
/SS
4E
13
K
4K
39
NC
4G
18
K
4K
54
NC
4G
14
/G
4F
40
NC
4H
19
/G
4F
55
NC
4H
41
/SW
4M
20
/SBb
5G
56
/SW
4M
21
DQb1
7H
57
/SBd
3L
22
DQb2
6H
58
DQd1
1K
15
DQa5
6H
16
DQa6
7G
17
DQa7
6F
18
DQa8
7E
42
DQb5
2K
23
DQb3
7G
59
DQd2
2K
43
DQb6
1L
24
DQb4
6G
60
DQd3
1L
25
DQb5
6F
61
DQd4
2L
44
DQb7
2M
26
DQb6
7E
62
DQd5
2M
45
DQb8
1N
27
DQb7
6E
63
DQd6
1N
28
DQb8
7D
64
DQd7
2N
29
DQb9
6D
65
DQd8
1P
19
DQa9
6D
20
SA2
6A
46
DQb9
2P
30
SA2
6A
66
DQd9
2P
21
SA3
6C
47
SA11
3T
31
SA3
6C
67
SA11
3T
22
SA7
5C
48
SA14
2R
32
SA6
5C
68
SA14
2R
23
SA6
5A
49
SA1
4N
33
SA5
5A
69
SA1
4N
24
NC
6B
50
SA15
2T
34
NC
6B
25
SA16
5B
51
M1
3R
35
SA15
5B
70
M1
3R
Data Sheet M13609EJ4V0DS
19
µPD464518AL, 464536AL
JTAG Instructions
Instructions
Description
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to Hi-Z any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs
input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from
the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an
inactive drive state (Hi-Z) and the boundary register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
JTAG Instruction Cording
IR2
IR1
IR0
Instruction
Note
0
0
0
EXTEST
1
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0
1
1
BYPASS
1
0
0
SAMPLE
1
0
1
BYPASS
1
1
0
BYPASS
1
1
1
BYPASS
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
20
Data Sheet M13609EJ4V0DS
1
µPD464518AL, 464536AL
TAP Controller State Diagram
1
Test-Logic-Reset
0
1
0
1
Run-Test / Idle
1
Select-DR-Scan
Select-IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
0
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1k resistor.
TDO should be left unconnected.
Data Sheet M13609EJ4V0DS
21
22
Test Logic Operation (Instruction Scan)
TCK
TMS
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
select-IR-Scan
select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
Data Sheet M13609EJ4V0DS
Controller
state
TDI
IDCODE
Output from Instruction Register
Output Inactive
TDO
New Instruction
Output from Instruction Register
µPD464518AL, 464536AL
Instruction
Register state
Test Logic Operation (Data Scan)
TCK
TMS
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
23
µPD464518AL, 464536AL
Output from Instruction Register
Output from Instruction Register
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Output Inactive
IDCODE
Instruction
Instruction
Register state
Capture-DR
select-DR-Scan
TDO
Run-Test/Idle
Data Sheet M13609EJ4V0DS
Controller
state
TDI
µPD464518AL, 464536AL
•
Package Drawing
119-PIN PLASTIC BGA
A
S
B
T
C
Index mark
7
6
5
4
3
2
1
D
U T RP NM L K J HGF E DCB A
P
J
I
R
H
K
S
F
S
E
G
L
ITEM
A
MILLIMETERS
22.0±0.2
B
19.5
C
12.0
D
E
F
14.0±0.2
0.84
1.27 (T.P.)
G
0.6±0.1
H
0.56
I
1.46±0.1
J
K
2.30 MAX.
0.15
L
P
φ 0.78±0.1
R
S
T
25°
1.25
C0.7
1.0
P119S1-127-R4-1
24
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD464518AL and µPD464536AL.
Types of Surface Mount Device
µPD464518ALS1: 119-pin plastic BGA
µPD464536ALS1: 119-pin plastic BGA
Data Sheet M13609EJ4V0DS
25
µPD464518AL, 464536AL
[MEMO]
26
Data Sheet M13609EJ4V0DS
µPD464518AL, 464536AL
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M13609EJ4V0DS
27
µPD464518AL, 464536AL
• The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
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Customers must check the quality grade of each semiconductor product before using it in a particular
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4