Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. SCCS059B - August 1994 - Revised September 2001 Features • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of −40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16543T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C CY74FCT162543T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25˚C CY74FCT162H543T Features: • Bus hold retains last active state • Eliminates the need for external pull-up or pull-down resistors CY74FCT16543T CY74FCT162543T CY74FCT162H543T 16-Bit Latched Transceivers Functional Description The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB) must be LOW in order to enter data from A or to take data from B as indicated in the truth table. With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the three-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs flow-through pinout and small shrink packaging and in simplifying board design. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines. The CY74FCT162H543T is a 24-mA balanced output part that has “bus hold” on the data inputs. The device retains the input’s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. Copyright © 2001, Texas Instruments Incorporated CY74FCT16543T CY74FCT162543T CY74FCT162H543T Logic Block Diagrams Pin Configuration 1OEBA Top View SSOP/TSSOP 1CEBA 1LEBA 1OEAB 1OEAB 1LEAB 1CEAB 1CEAB 1LEAB GND 1A 1 C D 1A 1 1B 1 1A 2 V CC 1A 3 1A 4 C D 1A 5 GND 1A 6 TO 7 OTHER CHANNELS 1A 7 FCT16543T-1 1A 8 2OEBA 2A 1 2CEBA 2A 2 2LEBA 2CEAB 2A 3 GND 2A 4 2A 5 2LEAB 2A 6 2OEAB C D 2A 1 V CC 2A 7 2A 8 2B 1 GND 2CEAB 2LEAB 2OEAB C D TO 7 OTHER CHANNELS 56 55 3 4 5 6 7 8 9 54 53 52 51 50 49 48 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OEBA 1LEBA 1CEBA GND 1B 1 1B 2 VCC 1B 3 1B 4 1B 5 GND 1B 6 1B 7 1B 8 2B 1 2B 2 2B 3 GND 2B 4 2B 5 2B 6 VCC 2B 7 2B 8 GND 2CEBA 2LEBA 2OEBA FCT16543T-3 FCT16543T-2 Function Table[1] Pin Description Name 1 2 Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A A-to-B Data Inputs or B-to-A Three-State Outputs[9] B B-to-A Data Inputs or A-to-B Three-State Outputs[9] Inputs CEAB Latch Status Output Buffers LEAB OEAB A to B B H X X Storing High Z X H X Storing X X X H X High Z L L L Transparent Current A Inputs L H L Storing Previous A Inputs[2] Maximum Ratings[3, 4] (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation .......................................................... 1.0W Storage Temperature .....................Com’l −55°C to +125°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .................................Com’l −55°C to +125°C Operating Range DC Input Voltage .................................................−0.5V to +7.0V Range DC Output Voltage ..............................................−0.5V to +7.0V Industrial DC Output Current (Maximum Sink Current/Pin) ........................... −60 to +120 mA 2 Ambient Temperature VCC −40°C to +85°C 5V ± 10% CY74FCT16543T CY74FCT162543T CY74FCT162H543T Electrical Characteristics Over the Operating Range Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions Min. Typ.[5] Max. 2.0 V 0.8 [6] VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA IIH Input HIGH Current IIL Input LOW Current IOZH Unit 100 mV −1.2 V VCC=Max., VI=VCC ±1 µA VCC=Max., VI=GND ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=2.7V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V ±1 µA IOS Short Circuit Current[7] VCC=Max., VOUT=GND −80 −200 mA IO Output Drive Current[7] VCC=Max., VOUT=2.5V −50 −180 mA ±1 µA IOFF Power-Off Disable VCC=0V, VOUT ≤4.5V[8] −0.7 V −140 Notes: 1. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. 2. Data prior to LEAB LOW-to-HIGH Transition H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. 3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 5. Typical values are at VCC= 5.0V, TA= +25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 8. Tested at +25˚C. 9. On the 74FCT162H543T, these pins have bus hold. 3 CY74FCT16543T CY74FCT162543T CY74FCT162H543T Output Drive Characteristics for CY74FCT16543T Parameter VOH VOL Min. Typ.[5] VCC=Min., IOH=−3 mA 2.5 3.5 VCC=Min., IOH=−15 mA 2.4 3.5 VCC=Min., IOH=−32 mA 2.0 3.0 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC=Min., IOL=64 mA Max. Unit V 0.2 0.55 V Min. Typ.[5] Max. Unit VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA 2.4 3.3 Output Drive Characteristics for CY74FCT162543T, CY74FCT162H543T Parameter IODL Description Output LOW Current [7] [7] Test Conditions IODH Output HIGH Current VOH Output HIGH Voltage VCC=Min., IOH=−24 mA VOL Output LOW Voltage VCC=Min., IOL=24 mA V 0.3 0.55 V Typ.[5] Max. Unit Capacitance[6] (TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Typ.[5] Max. Unit 5 500 µA Power Supply Characteristics Parameter Description Test Conditions ICC Quiescent Power Supply Current VCC=Max. VIN≤0.2V, VIN≥VCC−0.2V ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max. VIN=3.4V[10] 0.5 1.5 mA ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE=GND VIN=VCC or VIN=GND 60 100 µA/MHz IC Total Power Supply Current[12] VCC=Max., f1=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling, OE=GND VIN=VCC or VIN=GND 0.6 1.5 mA VIN=3.4V or VIN=GND 0.9 2.3 mA VIN=VCC or VIN=GND 2.4 4.5[13] mA VIN=3.4V or VIN=GND 6.4 16.5[13] mA VCC=Max., f1=2.5 MHz, 50% Duty Cycle, Outputs Open, Sixteen Bits Toggling, OE=GND Notes: 10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY74FCT16543T CY74FCT162543T CY74FCT162H543T Switching Characteristics Over the Operating Range[14] CY74FCT16543T CY74FCT162543T Parameter Description CY74FCT16543AT CY74FCT162543AT Min. Max. Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Transparent Mode A to B or B to A 1.5 8.5 1.5 6.5 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 1.5 12.5 1.5 8.0 ns 1, 5 tPZH tPZL Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 1.5 12.0 1.5 9.0 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 1.5 9.0 1.5 7.5 ns 1, 7, 8 tSU Set-up Time HIGH or LOW A or B to LEAB or LEBA 2.0 — 2.0 — ns 4 tH Hold Time HIGH or LOW A or B to LEAB or LEBA 2.0 — 2.0 — ns 4 tW LEBA or LEAB Pulse Width LOW 4.0 — 4.0 — ns 5 tSK(O) Output Skew[16] — 0.5 — 0.5 ns — CY74FCT16543CT CY74FCT162543CT CY74FCT162H543CT Parameter Description Min. Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Transparent Mode A to B or B to A 1.5 5.1 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 1.5 5.6 ns 1, 5 tPZH tPZL Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 1.5 6.5 ns 1, 7, 8 tSU Set-up Time HIGH or LOW A or B to LEAB or LEBA 2.0 — ns 4 tH Hold Time HIGH or LOW A or B to LEAB or LEBA 2.0 — ns 4 tW LEBA or LEAB Pulse Width LOW 4.0 — ns 5 tSK(O) Output Skew[16] — 0.5 ns — Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. See “Parameter Measurement Information” in the General Information section. 16. Skew between any two outputs of the same package switching in the same directional. This parameter is ensured by design. 5 CY74FCT16543T CY74FCT162543T CY74FCT162H543T Ordering Information CY74FCT16543 Speed (ns) Ordering Code 5.1 CY74FCT16543CTPVC/PVCT 6.5 8.5 Package Name Package Type Operating Range O56 56-Lead (300-Mil) SSOP Industrial CY74FCT16543ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial CY74FCT16543TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial Ordering Information CY74FCT162543 Speed (ns) 5.1 Ordering Code Package Name Package Type 74FCT162543CTPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT162543CTPVC O56 56-Lead (300-Mil) SSOP Operating Range Industrial 74FCT162543CTPVCT O56 56-Lead (300-Mil) SSOP 6.5 74FCT162543ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial 8.5 CY74FCT162543TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial Ordering Information CY74FCT162H543T Speed (ns) 5.1 Ordering Code 74FCT162H543CTPACT Package Name Z56 Package Type 56-Lead (240-Mil) TSSOP 6 Operating Range Industrial CY74FCT16543T CY74FCT162543T CY74FCT162H543T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated