44B CY7C344B 32-Macrocell MAX® EPLD Features densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344B LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. • High-performance, high-density replacement for TTL, 74HC, and custom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins • Advanced 0.65-micron CMOS EPROM technology to increase performance • 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package The speed and density of the CY7C344B makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial “glue” logic, without using multiple chips. This architectural flexibility allows the CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three. Functional Description Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344B represents the Logic Block Diagram [1] Pin Configurations HLCC Top View INPUT 15(23) INPUT INPUT/CLK 2(9) 27(6) INPUT INPUT 13(20) 28(7) INPUT INPUT 14(21) MACROCELL 8 MACROCELL 10 MACROCELL 12 MACROCELL 14 I/O 3(10) I/O 4(11) MACROCELL 5 I/O 5(12) L O I MACROCELL 7 O I/O 6(13) B A MACROCELL 11 MACROCELL 3 G L MACROCELL 16 I/O 9(16) C O I/O 10(17) I/O 11(18) N T I/O 12(19) I/O 17(24) R I/O 18(25) O L I/O 19(26) I/O 20(27) MACROCELL 9 MACROCELL 13 MACROCELL 15 MACROCELL 18 B MACROCELL 17 MACROCELL 20 U S MACROCELL 19 MACROCELL 22 I/O I/O I/O VCC GND I/O I/O MACROCELL 1 MACROCELL 4 MACROCELL 6 4 3 2 1 28 27 26 MACROCELL 21 MACROCELL 24 MACROCELL 23 MACROCELL 26 MACROCELL 25 I/O 23(2) MACROCELL 28 MACROCELL 27 I/O 24(3) MACROCELL 30 MACROCELL 29 I/O 25(4) MACROCELL 32 MACROCELL 31 I/O 26(5) 32 64 EXPANDER PRODUCT TERM ARRAY I/O INPUT INPUT INPUT INPUT/CLK I/O I/O 5 6 7 8 9 10 11 12 13 14 1516 1718 I/O I/O MACROCELL 2 1(8) 25 24 23 22 21 20 19 I/O I/O INPUT INPUT INPUT INPUT I/O I/O INPUT VCC GND I/O I/O 15(22) C344B–2 CerDIP Top View INPUT INPUT/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT C344B–1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT INPUT I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT C344B–3 Selection Guide 7C344B-15 7C344B-20 7C344B-25 15 20 25 Maximum Access Time (ns) Note: 1. Number in () refers to J-leaded packages. MAX is a registered trademark of Altera Corporation. Cypress Semiconductor Corporation Document #: 38-03036 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 8, 1999 CY7C344B DC Output Current, per Pin[2] ...................–25 mA to +25 mA Maximum Ratings DC Input Voltage[2] .........................................–2.0V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................. –65°C to +135°C Ambient Temperature VCC Commercial –0°C to +70°C 5V ±5% Industrial –40°C to +85°C 5V ±10% Ambient Temperature with Power Applied..............................................-65°C to +135°C Range Maximum Junction Temperature (Under Bias)............. 150°C Supply Voltage to Ground Potential[2] ............ –2.0V to +7.0V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VCC Supply Voltage Maximum VCC rise time is 10 ms VOH Output HIGH Voltage IOH = –4.0 mA DC[3] Min. Max. Unit 4.75(4.5) 5.25(5.5) V 2.4 V [3] VOL Output LOW Voltage IOL = 8 mA DC VIH Input HIGH Level VIL Input LOW Level –0.3 0.8 V IIX Input Current GND ≤ VIN ≤ VCC –10 +10 µA IOZ Output Leakage Current VO = VCC or GND –40 +40 µA tR Recommended Input Rise Time 100 ns tF Recommended Input Fall Time 100 ns 2.0 0.45 V VCC+0.3 V Capacitance Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 0V, f = 1.0 MHz 10 pF COUT Output Capacitance VOUT = 0V, f = 1.0 MHz 12 pF AC Test Loads and Waveforms R1 464Ω 5V R1 464Ω 5V OUTPUT ALL INPUT PULSES OUTPUT R2 250Ω 50 pF INCLUDING JIGAND SCOPE Equivalent to: 3.0V R2 250Ω 5 pF GND 10% ≤ 6 ns tR (a) (b) THÉVENIN EQUIVALENT (commercial) 163Ω OUTPUT 1.75V C344B–5 90% 10% 90% tf ≤ 6 ns tF C344B–6 C344B–7 Notes: 2. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. Document #: 38-03036 Rev. ** Page 2 of 12 CY7C344B For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled. Timing Considerations Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. When calculating synchronous frequencies, use tSU if all inputs are on the input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tSU) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the asynchronous configuration. 240 ICC ACTIVE (mA) Typ. Operation of the devices described herein with conditions above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344B contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. Typical ICC vs. fMAX 180 VCC =5.0V Room Temp. 120 60 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz MAXIMUM FREQUENCY 50 MHz C344B–8 Output Drive Current IO OUTPUT CURRENT (mA) TYPICAL Design Recommendations 250 IOL 200 VCC =5.0V Room Temp. 150 100 IOH 50 0 1 2 3 4 VO OUTPUT VOLTAGE (V) 5 C344B–9 The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. Document #: 38-03036 Rev. ** Page 3 of 12 CY7C344B EXPANDER DELAY t EXP REGISTER LOGIC ARRAY CONTROLDELAY tCLR tLAC tPRE INPUT INPUT DELAY tIN LOGIC ARRAY tRSU DELAY tRH tLAD OUTPUT DELAY OUTPUT tOD tXZ tZX tRD tCOMB tLATCH SYSTEM CLOCK DELAYtICS I/O CLOCK DELAY tIC I/O I/O DELAY tIO FEEDBACK DELAY tFD C344B–10 Figure 1. CY7C344B Timing Model External Synchronous Switching Characteristics Over Operating Range 7C344B-15 Parameter tPD1 Description Min. Dedicated Input to Combinatorial Output Delay[4] Com’l/Ind [4] tPD2 I/O Input to Combinatorial Output Delay tSU Global Clock Set-up Time Com’l/Ind Com’l/Ind [4] Max. Min. Max. 7C344B-25 Max. Unit 15 20 25 ns 15 20 25 ns 9 12 15 Synchronous Clock Input to Output Delay Input Hold Time from Synchronous Clock Input Com’l/Ind 0 0 0 ns tWH Synchronous Clock Input HIGH Time Com’l/Ind 6 7 8 ns tWL Synchronous Clock Input LOW Time Com’l/Ind 6 7 8 ns 83.3 Maximum Register Toggle Frequency Com’l/Ind tCNT Minimum Global Clock Period Com’l/Ind tODH Output Data Hold Time After Clock fCNT [6] Maximum Internal Global Clock Frequency 12 ns tH fMAX 10 Min. tCO1 [5] Com’l/Ind 7C344B-20 13 15 ns 71.4 62.5 MHz 16 20 ns Com’l/Ind 1 1 1 ns Com’l/Ind 76.9 62.5 50 MHz Notes: 4. C1 = 35 pF 5. The fMAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a 32-bit counter programmed into each LAB. Document #: 38-03036 Rev. ** Page 4 of 12 CY7C344B External Asynchronous Switching Characteristics Over Operating Range Parameter Description 7C344B-15 7C344B-20 7C344B-25 Min. Min. Min. Max. Max. Max. Unit 22 ns tACO1 Asynchronous Clock Input to Output Delay[4] Com’l/Ind tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Com’l/Ind 5 6 8 ns tAH Input Hold Time from Asynchronous Clock Input tAWH 15 18 Com’l/Ind 5 6 8 ns [7] Com’l/Ind 6 7 9 ns [7] Com’l/Ind 7 9 11 ns Asynchronous Clock Input HIGH Time tAWL Asynchronous Clock Input LOW Time tACNT Minimum Internal Array Clock Frequency Com’l/Ind fACNT Maximum Internal Array Clock Frequency[6] Com’l/Ind 13 76.9 16 62.5 20 50 ns MHz Typical Internal Switching Characteristics Over Operating Range 7C344B-15 Parameter Description Min. Max. 7C344B-20 Min. Max. 7C344B-25 Min. Unit 7 ns tIN Dedicated Input Pad and Buffer Delay Com’l/Ind 3 tIO I/O Input Pad and Buffer Delay Com’l/Ind 3 5 7 ns tEXP Expander Array Delay Com’l/Ind 8 10 15 ns tLAD Logic Array Data Delay Com’l/Ind 7 10 13 ns tLAC Logic Array Control Delay Com’l/Ind 4 4 4 ns Com’l/Ind 4 4 4 ns Com’l /Ind 7 7 7 ns 7 7 7 ns [4] 5 Max. tOD Output Buffer and Pad Delay tZX Output Buffer Enable Delay[4] tXZ [4] Output Buffer Disable Delay Com’l/Ind tRSU Register Set-Up Time Relative to Clock Signal at Register Com’l/Ind 4 4 5 ns tRH Register Hold Time Relative to Clock Signal at Register Com’l/Ind 5 8 10 ns tLATCH Flow-Through Latch Delay Com’l/Ind 1 1 1 ns tRD Register Delay Com’l/Ind 1 1 1 ns tCOMB Transparent Mode Delay Com’l/Ind 1 1 1 ns tIC Asynchronous Clock Logic Delay Com’l/Ind 7 8 10 ns tICS Synchronous Clock Delay Com’l/Ind 2 2 3 ns tFD Feedback Delay Com’l/Ind 1 1 1 ns tPRE Asynchronous Register Preset Time Com’l/Ind 5 6 9 ns tCLR Asynchronous Register Clear Time Com’l/Ind 5 6 9 ns Notes: 7. This parameter is measured with a positive-edge-triggered clock at the register. For the negative-edge clocking, the tACH and tACL parameter must be swapped. Document #: 38-03036 Rev. ** Page 5 of 12 CY7C344B Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT C344B-11 External Synchronous tWH tWL SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER tH tSU DATA FROM LOGIC ARRAY tCO1 REGISTERED OUTPUTS C344B-12 External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 tAH tAWH tAWL ASYNCHRONOUS CLOCK INPUT C344B–13 Internal Synchronous CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE C344B-14 Document #: 38-03036 Rev. ** Page 6 of 12 CY7C344B Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT tCOMB tOD OUTPUT PIN C344B-15 Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY tIC tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB C344B-16 Document #: 38-03036 Rev. ** Page 7 of 12 CY7C344B Switching Waveforms (continued) Internal Synchronous SYSTEM CLOCK PIN SYSTEM CLOCK AT REGISTER tIN tICS tRSU tRH DATA FROM LOGIC ARRAY C344B-17 Ordering Information Speed (ns) 15 20 25 Ordering Code CY7C344B-15HC/HI Package Name Package Type H64 28-Lead Windowed Leaded Chip Carrier CY7C344B-15JC/JI J64 28-Lead Plastic Leaded Chip Carrier CY7C344B-15PC/PI P21 28-Lead (300-Mil) Molded DIP CY7C344B-15WC/WI W22 28-Lead Windowed CerDIP CY7C344B-20HC/HI H64 28-Lead Windowed Leaded Chip Carrier CY7C344B-20JC/JI J64 28-Lead Plastic Leaded Chip Carrier CY7C344B-20PC/PI P21 28-Lead (300-Mil) Molded DIP CY7C344B-20WC/WI W22 28-Lead Windowed CerDIP CY7C344B-25HC/HI H64 28-Lead Windowed Leaded Chip Carrier CY7C344B-25JC/JI J64 28-Lead Plastic Leaded Chip Carrier CY7C344B-25PC/PI P21 28-Lead (300-Mil) Molded DIP Document #: 38-03036 Rev. ** Operating Range Commercial/Industrial Commercial/Industrial Commercial/Industrial Page 8 of 12 CY7C344B Package Diagrams 28-Pin Windowed Leaded Chip Carrier H64 51-80077 Document #: 38-03036 Rev. ** Page 9 of 12 CY7C344B Package Diagrams (continued) 28-Lead Plastic Leaded Chip Carrier J64 51-85001-A 28-Lead (300-Mil) Molded DIP P21 51-85014-B Document #: 38-03036 Rev. ** Page 10 of 12 CY7C344B Package Diagrams (continued) 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A 51-80087 Document #: 38-03036 Rev. ** Page 11 of 12 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C344B Document Title: CY7C344B 32-Macrocell MAX® EPLD Document Number: 38-03036 REV. ECN NO. Issue Date Orig. of Change ** 106381 06/15/01 SZV Document #: 38-03036 Rev. ** Description of Change Change from Spec #: 38-00860 to 38-03036 Page 12 of 12