fax id: 6104 1CY 7C34 6B CY7C346 CY7C346B 128-Macrocell MAX® EPLDs Features ture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology (CY7C346) • Advanced 0.65-micron CMOS technology to increase performance (CY7C346B) • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346/CY7C346B are divided into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip. Functional Description The CY7C346/CY7C346B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architec- The speed and density of the CY7C346/CY7C346B allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346/CY7C346B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C346/CY7C346B reduces board space, part count, and increases system reliability. Logic Block Diagram .. 1 . 78 . 79 80 . 83 . 84 .. 2 .. 5 .. 6 .. 7 (C7) [16] (A10) [9] (B9) [10] (A9) [11] (A8) [14] (B7) [15] (A7) [17] (C6) [20] (A5) [21] (B5) [22] INPUT [59] INPUT [60] INPUT [61] INPUT [64] INPUT [65] INPUT [66] INPUT [67] INPUT [70] INPUT [71] INPUT [72] . INPUT/CLK ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT (N4) (M5) (N5) (N6) (M7) (L7) (N7) (L8) (N9) (M9) . . . . . . . . . . 36 37 38 41 42 43 44 47 48 49 SYSTEM CLOCK 8 (B13) [1] 9 (C12) [2] 10 (A13) [3] 11 (B12) [4] 12 (A12) [5] 13 (11) [6] NC (A11) [7] NC (B10) [8] LAB A MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 1 2 3 4 5 6 7 8 MACROCELL 121–128 MACROCELL 9–16 14 (A4) 15 (B4) 16 (A3) 17 (A2) 18 (B3) 21 (A1) NC (B2) NC (B1) [23] [24] [25] [26] [27] [28] [29] [30] LAB B MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB G MACROCELL 104 MACROCELL 103 MACROCELL 102 MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 17 18 19 20 21 22 23 24 MACROCELL 25–32 22 (C2) [31] 25 (C1) [32] 26 (D2) [33] 27 (D1) [34] 28 (E2) [35] 29 (E1) [36] NC (F1) [39] NC (G2) [40] LAB C MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB F MACROCELL 88 MACROCELL 87 MACROCELL 86 MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 86–96 33 34 35 36 37 38 39 40 LAB D (G12) NC (H13) NC (J13) 71 (J12) 70 (K13) 69 (K12) 68 (L13) 67 (L12) 64 [80] [79] [78] [77] [76] [75] [74] [73] (M13) (M12) (N13) (M11) (N12) (N11) (M10) (N10) [58] [57] [56] [55] [54] [53] [52] [51] (M4) NC (N3) NC (M3) 55 (N2) 54 (M2) 53 (N1) 52 (L2) 51 (M1) 50 NC NC 63 60 59 58 57 56 LAB E MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 49 50 51 52 53 54 55 56 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL [18, 19, 43, 44, 68, 69, 93, 94] VCC 16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88] GND • 72 71 70 69 68 67 66 65 MACROCELL 73– 80 MACROCELL 57– 64 3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) Cypress Semiconductor Corporation [90] [89] [86] [85] [84] [83] [82] [81] MACROCELL 105–112 P I A MACROCELL 41–48 30 (G3) [41] 31 (G1) [42] 32 (H3) [45] 33 (J1) [46] 34 (J2) [47] 35 (K1) [48] NC (K2) [49] NC (L1) [50] [100] (C13) NC [99] (D12) NC [98] (D13) 77 [97] (E12) 76 [96] (E13) 75 [95] (F11) 74 [92] (G13) 73 [91] (G11) 72 3901 North First Street () – PERTAIN TO 100–PIN PGA PACKAGE [ ] – PERTAIN TO 100–PIN PQFP PACKAGE • C346–1 San Jose • CA 95134 • 408-943-2600 October 1989 – Revised March 31, 1997 CY7C346 CY7C346B Selection Guide 7C346B–15 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial 7C346–25 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 15 20 25 30 35 250 250 250 250 250 Military Maximum Standby Current (mA) 7C346B–20 320 325 320 320 Industrial 320 320 320 320 320 Commercial 225 225 225 225 225 275 275 275 275 275 275 275 275 Military Industrial 275 Shaded area contains preliminary information. Pin Configurations PLCC/CLCC Top View 11 10 9 8 7 6 I/O PGA BottomView 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 I/O I/O 12 13 73 I/O I/O I/O 14 15 72 I/O I/O I/O 16 I/O I/O GND 17 18 19 69 GND 20 21 66 65 I/O I/O 71 70 68 67 I/O I/O I/O I/O VCC N I/O I/O I/O INP INP INP INP VCC INP I/O I/O I/O I/O M I/O I/O I/O I/O INP GND INP VCC INP I/O I/O I/O I/O L I/O I/O I/O I/O K I/O I/O I/O I/O J I/O I/O I/O I/O H VCC VCC GND INP I/O 22 64 VCC I/O VCC 23 F 24 25 26 I/O GND I/O GND GND VCC I/O 63 62 61 GND I/O E I/O I/O D I/O I/O I/O I/O 7C346 7C346B 60 59 I/O I/O 27 I/O 29 58 57 I/O I/O 30 56 31 55 I/O 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 28 I/O I/O G I/O I/O INP GND GND 7C346 7C346B I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O I/O C I/O I/O I/O I/O B I/O I/O I/O I/O INP VCC INP GND INP A I/O I/O I/O I/O INP VCC INP 1 2 3 4 INP 5 6 INP GND /CLK 7 I/O I/O I/O I/O INP INP INP I/O I/O I/O 9 11 12 13 8 10 C346–3 C346–2 2 CY7C346 CY7C346B Pin Configurations (continued) PQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/O I/O 1 I/O 2 80 79 I/O I/O 3 78 I/O I/O 4 I/O I/O 5 77 76 I/O 6 75 I/O I/O 7 74 I/O I/O 8 73 I/O INPUT 9 72 INPUT 10 71 INPUT INPUT 11 70 GND 12 INPUT VCC GND 13 69 68 INPUT 7C346 7C346B I/O VCC 14 67 INPUT INPUT 15 66 INPUT INPUT/CLK 16 65 INPUT INPUT 17 64 INPUT VCC 18 63 GND VCC 19 62 INPUT 20 GND INPUT INPUT INPUT 21 61 60 INPUT 22 59 INPUT I/O 23 58 I/O I/O 24 57 I/O I/O 25 56 I/O I/O 26 55 I/O I/O 27 54 I/O I/O 28 I/O 29 I/O 30 53 INPUT I/O 52 I/O 51 I/O 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C346–4 3 CY7C346 CY7C346B DC Input Voltage[1] ........................................–3.0V to + 7.0V Maximum Ratings DC Program Voltage .................................................... 13.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ........................................... >1100V (per MIL-STD-883, Method 3015) Storage Temperature ..................................–65°C to+150°C Ambient Temperature with Power Applied..............................................–55°C to+125°C Operating Range Maximum Junction Temperature (under bias).................................................................. 150°C Ambient Temperature VCC 0°C to +70°C 5V ± 5% –40°C to +85°C 5V ± 10% –55°C to +125°C (Case) 5V ± 10% Range Commercial Supply Voltage to Ground Potential ................ –2.0V to+7.0V Industrial Maximum Power Dissipation................................... 2500 mW Military DC VCC or GND Current ............................................ 500 mA DC Output Current per Pin........................ –25 mA to+25 mA Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Current GND < VIN < VCC IOZ Output Leakage Current VO = VCC or GND Min. Max. Unit 2.4 0.5V[3, 4] V 0.45 V 2.2 VCC +0.3 V –0.3 0.8 V –10 +10 µA –40 +40 µA –30 IOS Output Short Circuit Current VCC = Max., VOUT = ICC1 Power Supply Current (Standby) VI = GND (No Load) –90 mA Com’l 225 mA ICC2 Power Supply Current[5] VI = VCC or GND (No Load) f = 1.0 MHz[4] Mil/Ind 275 Com’l 250 tR Recommended Input Rise Time Mil/Ind 320 100 ns tF Recommended Input Fall Time 100 ns mA Capacitance[6] Max. Unit CIN Parameter Input Capacitance Description VIN = 2V, f = 1.0 MHz Test Conditions 10 pF COUT Output Capacitance VOUT = 2V, f = 1.0 MHz 20 pF Notes: 1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns. 2. Typical values are for TA = 25°C and V CC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed by design but not 100% tested. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ , which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. 4 CY7C346 CY7C346B AC Test Loads and Waveforms[6] R1 464Ω R1 464Ω 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 250Ω 50 pF INCLUDING JIGAND SCOPE (a) 3.0V R2 250Ω 5 pF INCLUDING JIGAND SCOPE 10% 90% GND 90% 10% ≤ 6 ns ≤ 6 ns C346–5 C346–6 (b) Equivalent to: THÉVENIN EQUIVALENT(commercial/military) 163Ω OUTPUT 1.75V Externally, the CY7C346/CY7C346B provides 20 dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow. Logic Array Blocks There are 8 logic array blocks in the CY7C346/CY7C346B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Programmable Interconnect Array The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. EXPANDER DELAY tEXP REGISTER LOGIC ARRAY CONTROL DELAY tCLR tLAC tPRE INPUT INPUT DELAY tIN LOGIC ARRAY DELAY tLAD tRSU tRH OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX SYSTEMCLOCKDELAY tICS PIA DELAY tPIA CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO C346–7 Figure 1. CY7C346/CY7C346B Internal Timing Model 5 CY7C346 CY7C346B Timing Delays The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. Timing delays within the CY7C346/CY7C346B may be easily determined using Warp2 or Warp3 software or by the model shown in or Figure 1. The CY7C346 /CY7C346B has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information, Warp3 software provides a timing simulator. Typical ICC vs. fMAX 400 Design Recommendations Operation of the devices described herein with conditions above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C346/CY7C346B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. 300 VCC =5.0V RoomTemp. 200 100 For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have. 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz MAXIMUM FREQUENCY 50 MHz C346–8 Output Drive Current 100 IOL Design Security 80 The CY7C346/CY7C346B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. VCC =5.0V RoomTemp. 60 40 IOH 20 The CY7C346/CY7C346B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. 0 0.45 1 2 3 4 VO OUTPUT VOLTAGE (V) 6 5 C346–9 CY7C346 CY7C346B Timing Considerations lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay t EXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. When calculating synchronous frequencies, use tS1 if all inputs are on dedicated input pins. The parameter tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same asynchronous clock as the CY7C346/CY7C346B. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device’s clock signal path adding an additional delay (tEXP) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device’s register. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAWL) is less than 1/(tAS2 + tAH). When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the 7 CY7C346 CY7C346B Commercial and Industrial External Synchronous Switching Characteristics [6] Over Operating Range 7C346–25 7C346–30 7C346–35 7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35 Max. Unit tPD1 Parameter Dedicated Input to Combinatorial Output Delay[7] Description Min. Max. 15 Min. 20 25 30 35 ns tPD2 I/O Input to Combinatorial Output Delay[8] 25 32 40 45 55 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] 23 30 37 44 55 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4,10] 33 42 52 59 75 ns tEA Input to Output Enable Delay[4, 7] 15 20 25 30 35 ns tER Input to Output Disable Delay[4, 7] 15 20 25 30 35 ns tCO1 Synchronous Clock Input to Output Delay 7 8 14 16 20 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4,11] 17 20 30 35 42 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 12] 10 13 15 20 25 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 20 24 30 36 45 ns tH Input Hold Time from Synchronous Clock Input[7] 0 0 0 0 0 ns tWH Synchronous Clock Input HIGH Time 5 7 8 10 12.5 ns tWL Synchronous Clock Input LOW Time 5 7 8 10 12.5 ns tRW Asynchronous Clear Width[4, 7] 16 22 25 30 35 ns tRR Asynchronous Clear Recovery Time[4,7] 16 22 25 30 35 ns tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset Width[4, 7] 15 20 25 30 35 ns tPR Asynchronous Preset Recovery Time[4,7] 15 20 25 30 35 ns tPO Asynchronous Preset to Registered Output Delay[7] 15 20 25 30 35 ns tCF Synchronous Clock to Local Feedback Input[4, 13] 3 3 3 3 6 ns tP External Synchronous Clock Period (1/(fMAX3))[4] fMAX1 fMAX2 15 Max. Min. 20 Max. Min. 25 Max. Min. 30 35 ns 12 15 16 20 25 ns External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 14] 58.8 47.6 34.5 27.7 22.2 MHz Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] 76.9 62.5 55.5 43.4 32.2 MHz Shaded area contains preliminary information. 8 CY7C346 CY7C346B Commercial and Industrial External Synchronous Switching Characteristics [6] Over Operating Range 7C346–25 7C346–30 7C346–35 7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 16] 100 71.4 62.5 50 40 MHz fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH))[4, 17] 100 71.4 62.5 50 40 MHz tOH Output Data Stable Time from Synchronous Clock Input[4, 18] 3 3 3 3 3 ns Shaded area contains preliminary information. Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs. 15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local originating within the same LAB. 16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate t S for calculation. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to the dedicated clock input pin. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. 9 CY7C346 CY7C346B Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range 7C346–25 7C346–30 7C346–35 7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tACO1 Asynchronous Clock Input to Output Delay[7] 15 20 25 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] 25 32 39 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] tAS2 5 5 5 6 8 ns I/O Input Set-Up Time to Asynchronous Clock Input[7] 14.5 17 19 22 28 ns tAH Input Hold Time from Asynchronous Clock Input[7] 5 6 6 8 10 ns tAWH Asynchronous Clock Input HIGH Time[7] 9 10 11 14 16 ns tAWL Asynchronous Clock Input LOW Time[7, 20] 7 8 9 11 14 ns tACF Asynchronous Clock to Local Feedback Input[4, 21] tAP External Asynchronous Clock Period (1/(fMAXA4))[4] 16 18 20 25 30 ns fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4, 22] 50 40 33.3 27.7 23.2 MHz fMAXA2 Maximum Internal Asynchronous Frequency[4,23] 62.5 55.5 50 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous Mode [4, 24] 66.6 50 40 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] 62.5 55.5 50 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] 12 12 15 15 15 ns 11 13 15 18 22 ns Shaded area contains preliminary information. Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and t AWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, t AWH should be used for both tAWH and tAWL . 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/(tACF + t AS1)) or (1/(t AWH + t AWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single LAB. This parameter is tested periodically by sampling production material. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the lesser of 1/(tAWH + tAWL ), 1/(t AS1 + t AH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin. 10 CY7C346 CY7C346B Commercial and Industrial Internal Switching Characteristics Over Operating Range Parameter Description 7C346B–15 7C346B–20 7C346–25 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 Min. Min. Min. Min. Min. Max. Unit tIN Dedicated Input Pad and Buffer Delay Max. 3 4 5 7 9 ns tIO I/O Input Pad and Buffer Delay 3 4 6 6 9 ns tEXP Expander Array Delay 8 10 12 14 20 ns tLAD Logic Array Data Delay 8 10 12 14 16 ns tLAC Logic Array Control Delay 5 7 10 12 13 ns tOD Output Buffer and Pad Delay 3 3 5 5 6 ns tZX Output Buffer Enable Delay[27] 5 5 10 11 13 ns tXZ Output Buffer Disable Delay 5 5 10 11 13 ns tRSU Register Set-Up Time Relative to Clock Signal at Register 4 5 6 8 10 ns tRH Register Hold Time Relative to Clock Signal at Register 4 5 6 8 10 ns tLATCH Flow Through Latch Delay 1 2 3 4 4 ns tRD Register Delay 1 1 1 2 2 ns tCOMB Transparent Mode Delay[28] 1 2 3 4 4 ns tCH Clock HIGH Time 4 6 8 10 12.5 ns tCL Clock LOW Time 4 6 8 10 12.5 ns tIC Asynchronous Clock Logic Delay 6 8 14 16 18 ns tICS Synchronous Clock Delay 0.5 0.5 1 1 1 ns tFD Feedback Delay 1 1 1 1 2 ns tPRE Asynchronous Register Preset Time 3 3 5 6 7 ns tCLR Asynchronous Register Clear Time 3 3 5 6 7 ns tPCW Asynchronous Preset and Clear Pulse Width 3 4 5 6 7 ns tPCR Asynchronous Preset and Clear Recovery Time 3 4 5 6 7 ns tPIA Programmable Interconnect Array Delay Time 10 Max. 12 Max. 14 Max. 16 20 ns Shaded area contains preliminary information. Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. 11 CY7C346 CY7C346B Military External Synchronous Switching Characteristics[6] Over Operating Range Parameter Description 7C346B–20 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 Min. Min. Min. Min. Max. Unit tPD1 Dedicated Input to Combinatorial Output Delay[7] Max. 20 25 30 35 ns tPD2 I/O Input to Combinatorial Output Delay[8] 32 39 45 55 ns tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[9] 30 37 44 55 ns tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4,10] 42 51 59 75 ns tEA Input to Output Enable Delay[4, 7] 20 25 30 35 ns tER Input to Output Disable Delay[4, 7] 20 25 30 35 ns tCO1 Synchronous Clock Input to Output Delay 8 14 16 20 ns tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4,11] 20 30 35 42 ns tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7,12] 13 15 20 25 ns tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 24 29 36 45 ns tH Input Hold Time from Synchronous Clock Input[7] 0 0 0 0 ns tWH Synchronous Clock Input HIGH Time 7 8 10 12.5 ns tWL Synchronous Clock Input LOW Time 7 8 10 12.5 ns tRW Asynchronous Clear Width[4,7] 20 25 30 35 ns tRR Asynchronous Clear Recovery Time[4,7] 20 25 30 35 ns tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset Width[4,7] 20 25 30 35 ns tPR Asynchronous Preset Recovery Time[4,7 ] 20 25 30 35 ns tPO Asynchronous Preset to Registered Output Delay[7] 20 25 30 35 ns tCF Synchronous Clock to Local Feedback Input[4,13] 3 3 3 6 ns tP External Synchronous Clock Period (1/(fMAX3))[4] fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4,14] 20 Max. 25 Max. 30 35 ns 14 16 20 25 ns 47.6 34.5 27.7 22.2 MHz Shaded area contains preliminary information. 12 CY7C346 CY7C346B Military External Synchronous Switching Characteristics[6] Over Operating Range (continued) Parameter Description 7C346B–20 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 Min. Min. Min. Min. Max. Max. Max. Max. Unit fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] 62.5 55.5 43.4 32.2 MHz fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 16] 71.4 62.5 50 40 MHz fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH))[4, 17] 71.4 62.5 50 40 MHz tOH Output Data Stable Time from Synchronous Clock Input[4,18] 3 3 3 3 ns Shaded area contains preliminary information. Military External Asynchronous Switching Characteristics[6] Over Operating Range Parameter Description 7C346B–20 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 Min. Min. Min. Min. Max. Max. Max. Max. Unit tACO1 Asynchronous Clock Input to Output Delay[7] 20 25 30 35 ns tACO2 Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] 32 39 46 55 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] 6 5 6 8 ns tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[7] 17 19 22 28 ns tAH Input Hold Time from Asynchronous Clock Input[7] 6 6 8 10 ns tAWH Asynchronous Clock Input HIGH Time[7] 10 11 14 16 ns tAWL Asynchronous Clock Input LOW Time[7, 20] 8 9 11 14 ns tACF Asynchronous Clock to Local Feedback Input[4, 21] tAP External Asynchronous Clock Period (1/(fMAXA4))[4] 18 20 25 30 ns fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4,22] 40 33.3 27.7 23.2 MHz fMAXA2 Maximum Internal Asynchronous Frequency[4, 23] 55.5 50 40 33.3 MHz fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4,24] 50 40 33.3 28.5 MHz fMAXA4 Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4,25] 55.5 50 40 33.3 MHz tAOH Output Data Stable Time from Asynchronous Clock Input[4, 26] 12 15 15 15 ns 13 Shaded area contains preliminary information. 13 15 18 22 ns CY7C346 CY7C346B Military Typical Internal Switching Characteristics Over Operating Range Parameter Description 7C346B–20 7C346B–25 7C346–30 7C346B–30 7C346–35 7C346B–35 Min. Min. Min. Min. Max. Unit tIN Dedicated Input Pad and Buffer Delay 4 5 7 9 ns tIO I/O Input Pad and Buffer Delay 4 6 6 9 ns tEXP Expander Array Delay 10 12 14 20 ns tLAD Logic Array Data Delay 10 12 14 16 ns tLAC Logic Array Control Delay 7 10 12 13 ns tOD Output Buffer and Pad Delay 3 5 5 6 ns [27] Max. Max. Max. tZX Output Buffer Enable Delay 5 10 11 13 ns tXZ Output Buffer Disable Delay 5 10 11 13 ns tRSU Register Set-Up Time Relative to Clock Signal at Register 5 6 8 10 ns tRH Register Hold Time Relative to Clock Signal at Register 5 6 8 10 ns tLATCH Flow Through Latch Delay 2 3 4 4 ns tRD Register Delay 1 1 2 2 ns 4 ns Delay[28] tCOMB Transparent Mode tCH Clock HIGH Time 6 2 3 tCL Clock LOW Time 6 tIC Asynchronous Clock Logic Delay tICS Synchronous Clock Delay tFD Feedback Delay tPRE tCLR tPCW Asynchronous Preset and Clear Pulse Width 4 5 6 7 ns tPCR Asynchronous Preset and Clear Recovery Time 4 5 6 7 ns tPIA Programmable Interconnect Array Delay Time 8 4 10 8 12.5 10 ns 12.5 ns 8 14 16 18 ns 0.5 2 2 3 ns 1 1 1 2 ns Asynchronous Register Preset Time 3 5 6 7 ns Asynchronous Register Clear Time 3 5 6 7 ns 12 Shaded area contains preliminary information. 14 14 16 20 ns CY7C346 CY7C346B Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1[7] /t PD2 [8] COMBINATORIAL OUTPUT tER[7] HIGH-IMPEDANCE THREE-STATE COMBINATORIAL OR REGISTERED OUTPUT tEA [7] HIGH-IMPEDANCE THREE-STATE VALID OUTPUT C346–10 External Synchronous DEDICATED INPUTS OR REGISTERED FEEDBACK [7] tS1 tH tWH tWL SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] tRW/t PW tRR/t PR tOH tRO/t PO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [7] C346–11 External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT ASYNCHRONOUS CLEAR/PRESET tAH tAWH tACO1 tRW/t PW tAWL tRR/t PR tAOH tRO/t PO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK C346–12 15 CY7C346 CY7C346B Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN tPIA tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT C346–13 Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB C346–14 Internal Synchronous tCH tCL SYSTEM CLOCK PIN tIN tICS tRSU tRH SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY C346–15 16 CY7C346 CY7C346B Switching Waveforms (continued) Internal Synchronous CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE C346–16 Ordering Information Speed (ns) Ordering Code Package Name 15 CY7C346B–15HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–15JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346B–15NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346B–15RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–20HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–20JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346B–20NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346B–20RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–20HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–20RMB R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346–25HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346–25JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346–25NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346–25RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–25HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–25JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346B–25NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346B–25RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–25HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–25RMB R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346–30HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346–30JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346–30NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346B–30HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–30JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346B–30NC/NI N100 CY7C346B–30RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346–30HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346–30RMB R100 100-Pin Windowed Ceramic Pin Grid Array 20 25 30 Package Type Operating Range Commercial/Industrial Commercial/Industrial Military Commercial/Industrial Military Commercial/Industrial 100-Lead Plastic Quad Flatpack CY7C346B–30HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–30RMB R100 100-Pin Windowed Ceramic Pin Grid Array Shaded area contains preliminary information. 17 Military CY7C346 CY7C346B Ordering Information (continued) Speed (ns) 35 Ordering Code Package Name Operating Range Package Type CY7C346–35JC/JI J83 CY7C346–35NC/NI N100 84-Lead Plastic Leaded Chip Carrier 100-Lead Plastic Quad Flatpack Commercial/Industrial CY7C346–35RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–35HC/HI H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–35JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C346B–35NC/NI N100 100-Lead Plastic Quad Flatpack CY7C346B–35RC/RI R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346–35HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346–35RMB R100 100-Pin Windowed Ceramic Pin Grid Array CY7C346B–35HMB H84 84-Pin Windowed Leaded Chip Carrier CY7C346B–35RMB R100 100-Pin Windowed Ceramic Pin Grid Array Military Shaded area contains preliminary information. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups Parameter Subgroups VOH 1, 2, 3 tPD1 7, 8, 9, 10, 11 VOL 1, 2, 3 tPD2 7, 8, 9, 10, 11 VIH 1, 2, 3 tPD3 7, 8, 9, 10, 11 VIL 1, 2, 3 tCO1 7, 8, 9, 10, 11 IIX 1, 2, 3 tS1 7, 8, 9, 10, 11 IOZ 1, 2, 3 tS2 7, 8, 9, 10, 11 ICC1 1, 2, 3 tH 7, 8, 9, 10, 11 tWH 7, 8, 9, 10, 11 tWL 7, 8, 9, 10, 11 tRO 7, 8, 9, 10, 11 tPO 7, 8, 9, 10, 11 tACO1 7, 8, 9, 10, 11 tACO2 7, 8, 9, 10, 11 tAS1 7, 8, 9, 10, 11 tAH 7, 8, 9, 10, 11 tAWH 7, 8, 9, 10, 11 tAWL 7, 8, 9, 10, 11 Document #: 38–00244–D MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. 18 CY7C346 CY7C346B Package Diagrams 84-Lead Windowed Leaded Chip Carrier H84 19 CY7C346 CY7C346B Package Diagrams (continued) 84-Lead Plastic Leaded Chip Carrier J83 20 CY7C346 CY7C346B Package Diagrams (continued) 100-Lead Plastic Quad Flatpack N100 21 CY7C346 CY7C346B Package Diagrams (continued) 100-Pin Windowed Ceramic Pin Grid Array R100 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.