TMP93CF76/CF77/CW76/CU76/CT76 CMOS 16-Bit Microcontroller TMP93CF76/CF77/CW76/CU76/CT76 1. Outline and Feature TMP93CF76/CF77/CW76/CU76/CT76 are a high-speed advanced 16-bit microcontroller developed for application with VCR system control, software servo motor control, VFT driver and timer control. In addition to basics such as I/O ports, the TMP93CF76/CF77/CW76/CU76/CT76 have highspeed/high-precision signal measuring circuit, PWM (Pulse-Width-Modulator) and high-precision real timing pulse generator. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) • TLCS-90 instruction mnemonic upward compatible • 16 Mbyte linear address space • General-purpose registers and register bank system • 16-bit multiplication/division and bit transfer/arithmetic instructions • High-speed micro DMA: 4 channels (2 µs/2 byte at 16 MHz) (2) Minimum instruction execution time: 250 ns at 16 MHz (3) Internal ROM: (4) Internal RAM: TMP93CF76 192 KB TMP93CF77 160 KB TMP93CW76 128 KB TMP93CU76 96 KB TMP93CT76 72 KB TMP93CF76 4.0 KB TMP93CF77 4.0 KB TMP93CW76 2.5 KB TMP93CU76 2.5 KB TMP93CT76 2.0 KB 000707EBP1 • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93CF76-1 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 (5) 20-bit time-base-counter (TBC) • Free running counter • Accuracy: 125 ns (at fc = 16 MHz) • Overflow: 131 ms (at fc = 16 MHz) (6) 8-bit timer (TC0): 1 channel • For CTL linear time counter (7) 16-bit timer (TC1 to 5): 5 channels • C.sync count, capstan FG count, general: 3 channels (8) Timing pulse generator (TPG): 2 channels • (16-bit timing data + 6-bit output data) with 8-stages FIFO : 1 channel • (16-bit timing data + 4-bit output data) : 1 channel • Accuracy: 500 ns (at 16 MHz) (9) Pulse width modulation outputs (PWM) • 14-bit PWM: 3 channels (for controlling capstan, drum and tuner) • 8-bit PWM: 1 channel (for controlling volume ) • Carrier frequency: 31.25 kHz (at 16 MHz) (10) 24-bit time base counter capture circuit (Capture 0) • (18-bit timing data + 6 bit trigger data) with 8-stages FIFO: 1 channel • Capture input sources: Remote-control-input (RMTIN), V.sync, CTL, Drum-PG, general (1 channel) • Accuracy: 500 ns (at 16 MHz) (11) 17-bit time base counter capture circuit (Capture 1/2) • (16-bit timing data + 1-bit trigger data): 2 channels • Capture input sources: Drum-FG, Capstan-FG • Accuracy: 125 ns (at 16 MHz) (12) VISS/VASS detection circuit (VISS/VASS) • CTL duty detection • VASS data 16-bit latch (13) Composite-sync-signal (C.sync) input • Vertical-sync-signal (V.sync) separation • Horizontal-sync-signal (H.sync) separation (14) Head Amp switch/Color Rotary control (HA/CR) (15) Pseudo-V/H generator (PV/PH) (16) 8-bit AD converter (ADC): 10 channels • Conversion speed: 95 states (11.8 µs at 16 MHz) (17) Serial Channel (SIO): 1channel (18) Serial bus I/F • I2C bus with 8-stages FIFO: 1 channel/2 ports (19) Watch dog timer (WDT) 93CF76-2 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 (20) Interrupt controller (INTC) • CPU: 8 sources → SWI instruction and illegal instruction • Internal: 17 sources • External: 5 sources 7-level priority can be set. (21) I/O ports • 67 I/O ports (multiplexed functional pins.) High Break Down Voltage PortE, F are Included: 14 I/O ports • 8 input ports (P40/AIN2 to P47/AIN9) • 10 output ports PC0/G0 to PC7/G7, PD0/G8 to PD1/G9: High Break Down Voltage (22) Standby function: 4 halt modes (RUN, IDLE2, IDLE1, STOP) (23) System clock function • Dual clock operation 16 MHz (High-speed: normal)/32 kHz (Low-speed:slow) … 17-bit Real Time Counter built in (24) Operating Voltage • Vcc = 2.7 to 5.5 V (at 32 kHz) • Vcc = 4.5 to 5.5 V (at 16 MHz) (25) Package • 100 pin QFP 14 mm × 20 mm (Pin pitch: 0.65 mm) • Product name: P-QFP100-1420-0.65A 93CF76-3 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 DVCC DGND P73/SDA0 P74/SCL0 P75/AIN0/SDA1 P76/AIN1/SCL1 I2 C bus I/F 900/L CPU (IIC) XWA to AD P51/SO P52/SCK SIO for P50 (SI) PWM0 14-BIT PWM PWM1 W XBC B XDE D XHL H X1 Low frequency OSC (32 kHz) PB0/XT1 Real Time Counter (RTC) L IX XIY IY XIZ IZ XSP SP PB1/XT2 TEST CPU INT CLK RESET 32 bit SR P54/INT0 Interrupt Controller F P53/INT1 PC TEST1 TEST2 TEST3 (NC) INT2, 3, 4 8-BIT PWM (1CH) Others INT to PWM3 X2 A XIX (3CH) PA3/PWM2 High frequency OSC (16 MHz) RAM (2.0/2.5/4.0 KB) (VFT Driver) Port 2 P20 to 27 PD0 to 1/G8 to 9 Port D Port 1 P10 to17 PC0 to 7/G0 to 7 Port C Port 0 P00 to 07 PC0 to 5/S8 to 13 Port F PE0 to 7/S0 to 7 Port E Vkk 8-Bit Timer (TC0) P96/TO1/TPG10 P52/INT2/TI1(TI0) 16-Bit Timer (TC1) P51/INT3/TI2 (TI4) 16-Bit Timer (TC2) P50/INT4/TI3 (TI5)/SI 16-Bit Timer (TC3) ROM (72/96/128/ 166/192 KB) Watchdog Timer (WDT) Time Base Timer (TBC) for P75 (AIN0) P76 (AIN1) 8 BIT AD Converter (10 CH) ADREF P40 to 47/AIN2 to 9 ADGND Capture (Capture0, 1, 2) VS V-Separation C-sync P86/CSYNCIN 16-Bit Timer (TC4) 16-Bit Timer (TC5) RMTU, RMTD to SIO P93/TPG03 P97/TPG11 RMT-Input EXT External-Input P82/RMTIN P83/EXT/TO1 Timing Pulse Generater CTL, CFG, DFG, DPG P84/DPGIN CFGTM (TPG) P91/TPG01/ VASWP Capture Input (CAPIN) VISS/VASS CTL Duty Detector P90/TP0/TPG00 P92/TP1 P85/CFGIN P81/DFGIN P80/CTLIN PCTL HS P94/CR P94/HA P87/COMPIN PV/PH Head Amp SW Color Rotary PA0/PWM3/ PVPH for 8-BIT PWM Figure 1.1 TMP93CF76/CF77/CW76/CU76/CT76 block diagram 93CF76-4 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 2. Pin Assignment and Functions The assignment of input and output pins for the TMP93CF76/CF77/CW76/CU76/CT76, their names and functions are described below. Pin Assignment P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 TEST3 Figure 2.1.1 shows pin assignment of the TMP93CF76/CF77/CW76/CU76/CT76. P23 P24 P25 P26 P27 PE0/S0 PE1/S1 PE2/S2 PE3/S3 PE4/S4 PE5/S5 PE6/S6 PE7/S7 PF0/S8 PF1/S9 PF2/S10 PF3/S11 PF4/S12 PF5/S13 PC0/G0 PC1/G1 PC2/G2 PC3/G3 PC4/G4 PC5/G5 PC6/G6 PC7/G7 PD0/G8 PD1/G9 VKK 100 1 95 90 85 80 5 75 10 70 15 65 20 60 25 55 30 35 40 45 50 TEST2 TEST1 PB1/XT2 PB0/TX1 RESET TEST X2 X1 DGND CLK P54/INT0 P53/INT1 P52/INT2/TI1/TI0/SCK P51/INT3/TI2/TI4/SO P50/INT4/TI3/TI5/SI ADREF ADGND P47/AIN9 P46/AIN8 P45/AIN7 P44/AIN6 P43/AIN5 P42/AIN4 P41/AIN3 P40/AIN2 P76/AIN1/SCL1 P75/AIN0/SDA1 P74/SCL0 P73/SDA0 P87/COMPIN DVCC PA0/PWM3/PVPH PA3/PWM2 PWM0 PWM1 P90/TP0/TPG00 P91/TPG01/VASWP P92/TP1 P93/TPG03 P94/CR P95/HA P96/TO1/TPG10 P97/TPG11 P80/CTLIN P81/DFGIN P82/RMTIN P83/EXT/TO1 P84/DPGIN P85/CFGIN P86/CSYNCIN 2.1 Figure 2.1.1 Pin assignment (100-pin QFP) 93CF76-5 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 Pin names and function (1/3) Number of pins I/O P00 to P07 8 I/O port0: I/O ports P10 to P17 8 I/O port1: I/O ports P20 to P27 8 I/O P40 to P47 AIN2 to AIN9 8 Input Input port4: Input ports Analog input: Input to AD converter P50 INT4 TI3 TI5 SI 1 I/O Input Input Input Input Port50: I/O port (schmitt input) External Interrupt request input 4: Rising edge/Falling edge programable 16-bit timer3 (TC3) Input 3 16-bit timer5 (TC5) input 5 SIO received data P51 INT3 TI2 TI4 SO 1 I/O Input Input Input Output Port51: I/O port (schmitt input) External Interrupt request input 3: Rising edge/Falling edge programable 16-bit timer2 (TC2): Input 2 16-bit timer4 (TC4): input 4 SIO sending data P52 INT2 TI1 TI0 SCK 1 I/O Input Input Input I/O Port52: I/O port (schmitt input) External Interrupt request input 2: Rising edge/Falling edge programable 16-bit timer1 (TC1) Input 1 8-bit Timer0 (TC0) Input 0 SIO clock line P53 INT1 1 I/O Input Port53: I/O port (schmitt input) External Interrupt request pin1: Rising edge/Level programable P54 INT0 1 I/O Input Port54: I/O port (schmitt input) External Interrupt request pin0: Rising edge/Falling edge programable P73 SDA0 1 I/O I/O Port73: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SDA0 line P74 SCL0 1 I/O I/O Port74: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL0 line P75 SDA1 AIN0 1 I/O I/O Input Port75: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SDA1 line Analog input 0: Analog input signal for AD converter P76 SCL1 AIN1 1 I/O I/O Input Port76: Input port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL1 line Analog input 1: Analog input signal for AD converter P80 CTLIN 1 I/O Input Port80: I/O port (schmitt input) CTL Capture input (Capture 0) P81 DFGIN 1 I/O Input Port81: I/O port (schmitt input) DFG Capture input (Capture 1) Pin name Functions port2: I/O ports 93CF76-6 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 Table 2.2.1 Pin names and function (2/3) Pin name Number of pins I/O Functions P82 RMTIN 1 I/O Input Port82: I/O port (schmitt input) Remote Control Signal Capture input P83 EXT TO1 1 I/O Input Output P84 DPGIN 1 I/O Input Port84: I/O port (schmitt input) DPG Capture input (Capture 0) P85 CFGIN 1 I/O Input Port85: I/O port (schmitt input) CFG Capture input (Capture 2) P86 CSYNCIN 1 I/O Input Port86: I/O port (schmitt input) C.sync Capture input P87 COMPIN 1 I/O Input Port87: I/O port (schmitt input) Envelope Comparate Input (to HA/CR) P90 TP0 TPG00 1 I/O Output Output Port90: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 0 TPG00: TPG0 output P91 VASWP TPG01 1 I/O Output Output Port91: I/O port (Push-pull or open-drain output selectable) Video/Audio head switching control signal output TPG01: TPG0 output P92 TP1 1 I/O Output Port92: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 1 P93 TPG03 1 I/O Output Port93: I/O port (Push-pull or open-drain output selectable) TPG03: TPG0 output P94 CR 1 I/O Output Port94: I/O port (Push-pull or open-drain output selectable) Color Rotary Output P95 HA 1 I/O Output Port95: I/O port (Push-pull or open-drain output selectable) Head Amp Switching Control Output P96 TO1 TPG10 1 I/O Output Output Port96: I/O port (Push-pull or open-drain output selectable) Timer Out 1 TPG10: TPG1 output P97 TPG11 1 I/O Output Port97: I/O port (Push-pull or open-drain output selectable) TPG11: TPG1 output PA0 PVPH PWM3 1 I/O Output Output PortA0: I/O port PVPH 3-state Output PWM(8 bits) output 3 PA3 PWM2 1 I/O Output PortA3: I/O port (Push-pull or open-drain output selectable) PWM(14 bits) output 2 Port83: I/O port (schmitt input) External Capture input (Capture 0) Timer Out 1 93CF76-7 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 Table 2.2.1 Pin names and function (3/3) Pin name Number of pins I/O Functions PWM0 1 Output PWM(14 bits) output 0 (Push-pull or open-drain output selectable) PWM1 1 Output PWM(14 bits) output 1 (Push-pull or open-drain output selectable) PB0 XT1 1 I/O Input PortB0: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PB1 XT2 1 I/O Output PortB1: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PC0 to PC7 G0 to G7 8 Output Output PortC: Output (High break down voltage outputs with pull-down resistor) Grid Drivers PD0,1 G8, 9 2 Output Output PortD: Output (High break down voltage outputs with pull-down resistor) Grid Drivers PE0 to PE7 S0 to S7 8 I/O Output PortE: I/O ports (High break down voltage outputs with pull-down resistor) Segment Drivers PF0 to PF5 S8 to S13 6 I/O Output PortF: I/O ports (High break down voltage outputs with pull-down resistor) Segment Drivers TEST1 1 Output TEST2 1 Input TEST1 should be connected with TEST2 pin. TEST3(NC) 1 Output TEST3 should be open connection. CLK 1 Output Clock output: Output (System Clock ÷ 2) clock. Pulled-up during reset. Can be set to output disable for reducing noise. (Initial Disable) TEST 1 Input Test pin: Always set to “Vcc” level RESET 1 Input Reset: Initializes LSI. (with pull-up resistor) X1 1 Input High Frequency Oscillator connecting pins (16 MHz) X2 1 Output VKK 1 High Frequency Oscillator connecting pins (16 MHz) VFT Driver power supply pin DVCC 1 Power supply pin DGND 1 GND pin (0 V) ADREF 1 Reference voltage input for AD converter ADGND 1 GND pin for AD converter 93CF76-8 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 3. Operation This section describes the functions TMP93CF76/CF77/CW76/CU76/CT76 devices. and basic operational blocks of See the “7. Points of Concern and Restrictions” for the using notice and restrictions for each block. 3.1 CPU TMP93CF76/CF77/CW76/CU76/CT76 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section). This section describes CPU functions unique to the TMP93CF76/CF77/CW76/CU76/CT76 that are not described in the previous section. 3.1.1 Reset To reset the TMP93CF76/CF77/CW76/CU76/CT76, the RESET input must be kept at 0 for at least 10 system clocks. (1.25 µs at 16 MHz) within the operating voltage range and with a stable oscillation. When reset is accepted, the CPU sets as follows: • Program Counter (PC) according to Reset Vector that is stored FFFF00H to FFFF02H. PC (7:0) PC (15:8) PC (23:16) ← stored data in location FFFF00H ← stored data in location FFFF01H ← stored data in location FFFF02H • Stack pointer (XSP) for system mode to 100H. • IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.) • MAX bit of status register to 1. (Sets to maximum mode) • Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from PC (reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows • Initializes built-in I/O registers as per specifications. • Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode. Note: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. 93CF76-9 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CF76/CF77/CW76/CU76/CT76. 000000H 000000H 000090H 000000H Internal I/O (144 byte) Internal I/O (144 byte) Internal I/O (144 byte) 000090H 000090H Internal RAM (4.0 Kbyte) 000100H 000100H Internal RAM (2.5 Kbyte) Direct Area (n) 000100H Internal RAM (4.0 Kbyte) 000A90H 001090H 001090H 64K-byte Area (nn) FD0000H FD8000H FE0000H Internal ROM (192 Kbyte) FFFF00H FFFF00H FFFF00H Interrupt Vector Table Area (256 byte) Interrupt Vector Table Area (256 byte) FFFFFFH FFFFFFH TMP93CF76 Internal ROM (128 Kbyte) Internal ROM (160 Kbyte) 16-Mbyte Area (R) (−R) (R+) (R+R8/16) (R+d8/16) (nnn) Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CF77 TMP93CW76 Internal Area Figure 3.2.1 Memory map (1/2) 93CF76-10 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 000000H 000000H Internal I/O (144 byte) 000090H Internal I/O (144 byte) 000090H Internal RAM (2.5 Kbyte) 000100H Internal RAM (2.0 Kbyte) Direct Area (n) 000100H 000890H 000A90H 64K-byte Area (nn) FE8000H FEE000H Internal ROM (96 Kbyte) Internal ROM (72 Kbyte) FFFF00H FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH 16-Mbyte Area (R) (−R) (R+) (R+R8/16) (R+d8/16) (nnn) Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CU76 TMP93CT76 Internal Area Figure 3.2.1 Memory map (2/2) 93CF76-11 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 4. Electrical Characteristics 4.1 Absolute Maximum Rating Parameter Rating Unit Power Supply Voltage Vcc −0.5 to 6.5 Input Voltage VIN −0.5 to Vcc+0.5 Output Voltage (except PC, PD, PE, PF) VOUT1 −0.5 to Vcc+0.5 Output Voltage (PC, PD, PE, PF) VOUT2 Vcc−40 Output Current (except PC, PD, PE, PF) (per 1 pin) IOH1 −3.2 Output Current (PC, PD) (per 1 pin) IOH2 −25 Output Current (PE, PF) (per 1 pin) IOH3 −15 Output Current (per 1 pin) IOL 3.2 Output Current (total except PC, PD, PE, PF) ΣIOH1 −40 Output Current (total of PC, PD, PE, PF) ΣIOH2 −120 Output Current (total) ΣIOL 120 Power Dissipation (Ta = 70°C) PD 600 Soldering Temperature Tsolder 260 Storage Temperature Tstg −65 to 150 Operating Temperrature Topr −20 to 70 Note: 4.2 Symbol V mA mW °C The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. DC Characteristics (1/2) Ta = −20 to 70°C Parameter Power Supply Voltage Input Low Voltage Input High Voltage P0, P1, P2, P4, P9, PA, PB, PE, PF RESET , Symbol Vcc Condition fc = 4 to 16 MHz 4.5 fs = 30 to 34 kHz 2.7 VIL2 (Schmitt) −0.3 VIL4 (Xtal) P0, P1, P2, P4, P9, PA, PB, PE, PF RESET , VIH1 (CMOS) Max Unit 5.5 V 0.25 Vcc 0.3 VIL3 (Fixed) X1 Typ. 0.3 Vcc VIL1 (CMOS) P5, P7, P8 TEST Min Vcc = 2.7 to 5.5 V 0.2 Vcc V 0.7 Vcc VIH2 (Schmitt) 0.75 Vcc TEST VIH3 (Fixed) Vcc − 0.3 X1 VIH4 (Xtal) P5, P7, P8 Vcc + 0.3 0.8 Vcc 93CF76-184 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 4.2 DC Characteristics (2/2) Ta = −20 to 70°C Parameter Symbol Condition Min Typ. Max Unit 0.45 V VOL IOL = 1.6 mA (Vcc = 2.7 to 5.5 V) VOH IOH = −400 µA (Vcc = 2.7 to 5.5 V) 2.4 VOH1 IOH = −700 µA (Vcc = 4.5 to 5.5 V) 4.1 PC, PD IOH Vcc = 4.5 V VOH = 2.4 V Input Leakage Current ILI 0.0 ≤ Vin ≤ VCC 0.02 ±5 Output Leakage Current ILO 0.2 ≤ Vin ≤ VCC -0.2 0.05 ±10 Power Down Voltage VSTOP VIH2 = 0.8 VCC Output Low Voltage Output High Voltage PE, PF RESET RRST Pull Up Resistor Pin Capacitance CIO Schmitt Width RESET , V −5 mA −15 µA VIL2 = 0.2 VCC, 2.0 6.0 Vcc = 5 V ± 10% 50 150 Vcc = 3 V ± 10% 80 200 osc = 1 MHz/100 mVp-p V kΩ 10 pF 1.0 VTH V P5,P7,P8 NORMAL Vcc = 5 V ± 10% fc = 16 MHz RUN IDLE2 IDLE1 Icc SLOW RUN IDLE2 IDLE1 Vcc = 3 V ± 10% fs = 32.768 kHz (typ: VCC = 3.0 V) Vcc = 2.7 to 5.5 V STOP 30 50 18 28 15 25 5 8 50 80 30 45 25 40 12 25 0.2 10 mA µA Note 1: Typical value are for Ta = 25°C and Vcc = 5 V unless otherwise noted. Note 2: Icc measurement conditions (NORMAL,SLOW). Only CPU is operational;output pins are open and input pins are fixed. 4.3 AD Conversion Characteristics Ta = −20 to 70°C, VCC = 4.5 to 5.5 V Parameter Symbol Min Typ. Max Unit ADREF Vcc − 1.5 Vcc Vcc V ADGND Vss Vss Vss V Analog Input Voltage Range VAIN ADGND ADREF V Analog Current for ADREF IREF 1.0 1.5 mA ET ±3 LSB Analog Reference Voltage Supply Total tolerance (excludes quantization error) (Ta = 25°C, Vcc = ADREF = 5 V) 93CF76-185 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 4.4 Serial Bus Interface Timing (1) I2C bus Logic Timing Start Command Stop Command tGSTA1 tODAT1 tGSTP1 tGSTP3 SDA tFSDA tRSDA tRSCL tFSCL SCL tGSDA2 tSUODAT tHDODAT tHIGH tLOW tGSTP2 tCYCSCL Parameter Symbol Min Typ. Max Unit s SCL cycle tCYCSCL 2 /fc SCL low pulse width tLOW 2N-1/fc s SCL High pulse width tHIGH 2N-1/fc s N SDA Rising Time (Note 1) tRSDA s SDA Falling Time (Note 1) tFSDA s SCL Rising Time (Note 1) tRSCL SCL Falling Time (Note 1) tFSCL The time from start command write to start sheecense tGSTA1 Start condition hold time, start generation of the first clock after this tGSTA2 2N-1/fc Delay time from SCL falling to data output (Note 2) tODAT1 5/fc s Set up time of data output for SCL rising (Note 2) tSUODAT 0 s The time of holding data for SCL rising (Note 3) s s 2N/fc s s tHODAT 4/fc s The time from stop command write to starting stop sheecense tGSTP1 2N-1/fc s The time from SDA falling to SCL rising (during stop sheecense) tGSTP2 2N-2/fc s Stop condition set up time tGSTP3 2N-1/fc s Note 1: The time of rising/falling depend on the feature of bus interface. Note 2: The worst case is at the first bit of slave address. Note 3: The worst case is at the acknowledge bit. Note 4: N: dividing value set by I2CCR1 <SCK 2:0>. SCK N 000 001 010 011 100 101 110 111 6 7 8 9 10 11 12 reserved 93CF76-186 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 (2) Master SCL output timing The I2CCR1 <SCK 2:0> are used to select a maximum transfer frequency directed from the SCL pin in the master mode.When rising time of the output clock (tRC) is at least 8/fc [s], a high-level time of the output clock (tHC) is tSCL. While the SCL line is fixed to low-level by a slave device,the output clock stops. The first clock (tHC [s] ) after restart is (tSCL/2) ≤ tHC ≤ tSCL. (a) In case of tRC < (8/fc) [s] 1/FSCL [s] tHC SCL pin (Output) tHC = tLC = tSCL/2 [s] (tSCL = 1/fSCL [s] ) tLC 0.5VCC FSCL=fSCL tRC (b) In case of tRC ≥ (8/fc) [s] tHC = tSCL [s] , tLC = tSCL/2 [s] tHC 1/FSCL [s] SCL pin (Output) tLC 0.5 VCC FSCL=fSCL/1.5 tRC 93CF76-187 2001-09-07 TMP93CF76/CF77/CW76/CU76/CT76 (3) Clock Syncro 8 bit SIO mode 1. SCK Input mode Parameter Symbol Expression Min SCK cycle tSCY2 25X SCK falling Latch output data tOHS2 6X Enable output data SCK raising tOSS2 Unit Max s s tSCY2 − 16X s SCK raising Latch input data tHSR2 6X ns Enable input data SCK raising tISS2 0 ns Note: X=1/fc 2. SCK Output mode Parameter Symbol Expression Unit Min Max 211X s tSCY2 − 2X s SCK cycle tSCY2 25X SCK falling Latch output data tOHS2 2X Enable output data SCK raising tOSS2 s SCK raising Latch input data tHSR2 2X s Enable input data SCK raising tISS2 0 ns Note: X=1/fc tOSS2 tSCY2 tISS2 SCK (Input/Output mode) tOHS2 SO (Output data) tHSR2 SI (Input data) 93CF76-188 2001-09-07