CXD4000R Fingerprint Verification System LSI Description The CXD4000R is an IC that inputs the signal from a Sony fingerprint sensor and performs fingerprint verification. This chip integrates a CPU, A/D converter, DRAM, USB controller and other circuits. Features • Combination with a Sony fingerprint sensor and a flash memory realizes a fingerprint verification system with a 3-chip configuration • 16-bit microcomputer SPC970 • USB controller (conforms to Rev 1.1) 120 pin LQFP (Plastic) Applications • Fingerprint verification units (stand-alone) • Cellular phones • Personal computers Fingerprint Verification Block • Adoption of Sony's original verification algorithm also provides excellent results for blurred and deformed fingerprints • False rejection ratio: 1% or less, false acceptance ratio: 0.1% or less (with 2 trials) • Verification time per finger: approximately 40ms (Clock frequency: 48MHz, excluding fingerprint image loading time) Structure Silicon gate CMOS IC Absolute Maximum Ratings VSS – 0.5 to +4.6 V • Supply voltage VDD • Input voltage VI VSS – 0.5 to VDD + 0.5 V VSS – 0.5 to VDD + 0.5 V • Output voltage VO • Storage temperature Tstg –55 to +150 °C Microcomputer Block • CPU: SPC970 series 16-bit CPU core • Internal RAM: 4K bytes • External flash memory: 16-bit, 2M bytes • External expansion SRAM: 8-bit/16-bit, 2M bytes each • General purpose register: 16 bits × 8 lines × 32 banks • Processing rate: 41.6ns (fSYS: 24MHz) • Peripheral hardware • Serial interface × 1 channel (Clock synchronous serial interface or asynchronous serial interface) • 16-bit timer × 4 channels • External memory interface • 8-bit A/D converter (also used as sensor input) • 8-bit D/A converter × 1 channel • General-purpose I/O: 12 (also used as interrupt inputs, etc.) Recommended Operating Conditions • Supply voltage VDD 3.0 to 3.6 • Input voltage VI VSS to VDD • Output voltage VO VSS to VDD • Operating temperature Topr 0 to +70 V V V °C I/O Pin Capacitance • Input pin capacitance CI 9 (max.) • Output pin capacitance CO 11 (max.) • I/O pin capacitance CI/O 11 (max.) Note) Measurement conditions: VDD = VI = 0V, f = 1MHz pF pF pF USB Controller • Conforms to Rev 1.1 • USB transceiver circuit • Supports full-speed (12Mbps) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01664-PS CXD4000R USB_AVD DM DP USB_AVS SI SO SCK SIOCS PB0 PB1 VSS VDD PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDD VSS SENS_CLK SENS_GAIN0 SENS_GAIN1 SENS_GAIN2 SENS_XSP NC Block Diagram and Pin Configuration 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 ADC_AVS 1 90 D15 AIN1 2 AIN2 3 ADC_AVD 4 VSS 5 86 D11 RST 6 85 VSS VDD 7 VSS 8 VSS 9 VSS 10 81 D8 VSS 11 80 D7 89 D14 Port A Port B USART 87 D12 84 D10 82 VDD 79 D6 USB Controller VSS 13 14 78 D5 77 VSS Binarization Verification register VSS 15 VSS 16 76 D4 75 D3 VSS 17 VSS 83 D9 USB Driver Timer VSS 12 VDD 88 D13 ADC 74 D2 CPU Block Correlation 18 73 D1 VSS 19 72 D0 DAC_AVS 20 71 A20 DAC_BIR 21 70 VSS Main RAM Positional Correlation DAC AOUT 22 69 A19 DAC_AVD 23 68 A18 VSS 24 67 VDD NC 25 66 A17 NC 26 Verification SRAM VSS 27 Clock Generator DRAM 65 A16 Interrupt Controller 64 A15 XTAL 28 63 VSS EXTAL 29 62 A14 30 61 A13 –2– A12 VSS VDD A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 VSS A2 A1 VDD A0 WR RD CS0 CS1 CS2 VSS NC NC NC VSS VSS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS VDD CXD4000R Pin Description Pin No. Symbol 1 ADC_AVS 2 AIN1 I A/D converter analog input. 3 AIN2 I A/D converter analog input. 4 ADC_AVD A/D converter power supply. 5 VSS GND. 6 RST 7 VDD I/O Remarks A/D converter GND. I Sensor input Low level active system reset. Power supply. 8 to 13 VSS 14 Description GND. VDD Power supply. 15 to 19 VSS GND. 20 DAC_AVS 21 DAC_BIR I Bias resistor connection for D/A converter output buffer (operational amplifier). 22 AOUT O D/A converter analog output. 23 DAC_AVD D/A converter power supply. 24 VSS GND. D/A converter GND. 25, 26 NC No connected. 27 VSS 28 XTAL O Oscillator connection for clock oscillation. 29 EXTAL I Oscillator connection for clock oscillation. 30 VDD GND. Power supply. 31 to 33 VSS GND. 34 to 36 NC No connected. 37 VSS 38 CS2 O External expansion 16-bit SRAM chip select. 39 CS1 O External expansion 8-bit SRAM chip select. 40 CS0 O Flash memory chip select. 41 RD O External memory read strobe. 42 WR O External memory write strobe. 43 A0 I/O External memory address bus. 44 VDD 45 A1 I/O External memory address bus. 46 A2 I/O External memory address bus. 47 VSS 48 A3 I/O External memory address bus. 49 A4 I/O External memory address bus. 50 A5 I/O External memory address bus. GND. Power supply. GND. –3– Pull-up with an external 33kΩ resistor CXD4000R Pin No. Symbol I/O Description Remarks 51 A6 I/O External memory address bus. 52 A7 I/O External memory address bus. 53 A8 I/O External memory address bus. 54 VSS 55 A9 I/O External memory address bus. 56 A10 I/O External memory address bus. 57 A11 I/O External memory address bus. 58 VDD Power supply. 59 VSS GND. 60 A12 I/O External memory address bus. 61 A13 I/O External memory address bus. 62 A14 I/O External memory address bus. 63 VSS 64 A15 I/O External memory address bus. 65 A16 I/O External memory address bus. 66 A17 I/O External memory address bus. 67 VDD 68 A18 I/O External memory address bus. 69 A19 I/O External memory address bus. 70 VSS 71 A20 I/O External memory address bus. 72 D0 I/O External memory data bus. Pulled-up internally 73 D1 I/O External memory data bus. Pulled-up internally 74 D2 I/O External memory data bus. Pulled-up internally 75 D3 I/O External memory data bus. Pulled-up internally 76 D4 I/O External memory data bus. Pulled-up internally 77 VSS 78 D5 I/O External memory data bus. Pulled-up internally 79 D6 I/O External memory data bus. Pulled-up internally 80 D7 I/O External memory data bus. Pulled-up internally 81 D8 I/O External memory data bus. Pulled-up internally 82 VDD 83 D9 I/O External memory data bus. Pulled-up internally 84 D10 I/O External memory data bus. Pulled-up internally 85 VSS 86 D11 I/O External memory data bus. Pulled-up internally 87 D12 I/O External memory data bus. Pulled-up internally GND. GND. Power supply. GND. GND. Power supply. GND. –4– CXD4000R Pin No. Symbol I/O Description Remarks 88 D13 I/O External memory data bus. Pulled-up internally 89 D14 I/O External memory data bus. Pulled-up internally 90 D15 I/O External memory data bus. Pulled-up internally 91 USB_AVD 92 DM I/O USB D– 93 DP I/O USB D+ 94 USB_AVS 95 SI I Serial data input. Pulled-up internally 96 SO O Serial data output. Tri-state, pulled-up internally 97 SCK I/O Serial clock I/O. Pulled-up internally 98 SIOCS I Serial chip select input. Pulled-up internally 99 PB0 I (Port B) Input port/external interrupt request input. Pulled-up internally 100 PB1 I (Port B) Input port/external interrupt request input. Pulled-up internally 101 VSS GND. 102 VDD Power supply. 103 PB2 I (Port B) Input port/external interrupt request input. Pulled-up internally 104 PB3 I (Port B) Input port/external interrupt request input. Pulled-up internally 105 PA0 I/O (Port A) I/O port. Pulled-down internally 106 PA1 I/O (Port A) I/O port. Pulled-down internally 107 PA2 I/O (Port A) I/O port. Pulled-down internally 108 PA3 I/O (Port A) I/O port. Pulled-down internally 109 PA4 I/O (Port A) I/O port. Pulled-up internally 110 PA5 I/O (Port A) I/O port. Pulled-up internally 111 PA6 I/O (Port A) I/O port. Pulled-up internally 112 PA7 I/O (Port A) I/O port/external 16-bit SRAM upper byte control. Pulled-up internally 113 VDD Power supply. 114 VSS GND. 115 SENS_CLK O Sensor clock output. 116 SENS_GAIN0 O Sensor gain output. 117 SENS_GAIN1 O Sensor gain output. 118 SENS_GAIN2 O Sensor gain output. 119 SENS_XSP O Sensor start pulse output. 120 NC USB power supply. USB GND. No connected. –5– CXD4000R Electrical Characteristics DC Characteristics Item Input voltage (1) (digital) Input voltage (2) (USB interface) Input voltage (3) (A/D input) (Within the recommended operating range) Symbol High level input voltage VIH Low level input voltage VIL Differential input sensitivity Vdi Differential common mode range Conditions Min. Max. 0.7VDD Unit V Applicable pins Inputs other than ∗3 and ∗4 0.2VDD V 0.2 — V Vcm 0.8 2.5 V Single-ended receiver high level input voltage VIH 2.0 VDD V Single-ended receiver low level input voltage VIL 0 0.8 V Analog input level VIN 0.1VDD 0.9VDD V ∗4 VDD – 0.4 VDD V ∗1 0 0.4 V VDD – 0.4 VDD V Output voltage (1) High level output voltage (digital) Low level output voltage VOH1 IOH = –4mA VOL1 IOL = 4mA Output voltage (2) High level output voltage (digital) Low level output voltage VOH2 IOH = –2mA VOL2 IOL = 2mA 0 0.4 V Output voltage (3) Low level output voltage (USB interface) High level output voltage VOL RL = 1.5kΩ to 3.6V — 0.3 V VOH RL = 15kΩ to GND 2.8 3.6 V 0 VDD V Output voltage (4) Analog output level (D/A output) VON ∗1 A0 to A20, PA0 to PA7, SCK, SO D0 to D15, SENS_CLK, SENS_GAIN0 to SENS_GAIN2, SENS_XSP, CS0 to CS2, RD, WR DP, DM AIN1, AIN2 AOUT ∗2 ∗3 ∗4 ∗5 –6– ∗3 ∗2 ∗3 ∗5 CXD4000R AC Characteristics (1) Oscillation Inverter I/O Characteristics Item Logical Vth Input voltage Output voltage Symbol LVth Pins (Within the recommended operating range) Conditions Min. Typ. VDD/2 EXTAL VIH VOH XTAL VOL Feedback resistor RFB EXTAL XTAL Oscillation frequency fEX EXTAL XTAL V 0.3VDD Feed current where IOH = –3.0mA VDD/2 V V Pull-in current where IOL = 3.0mA VIN = VDD or Vss Unit V 0.7VDD EXTAL VIL Max. 250k VDD/2 V 2.5M Ω 48.12 MHz 1M 20 Note) When using USB, the oscillation frequency should be 48MHz ± 0.25%. (2) Frequency Division Clock Timing Item Microcomputer system clock period Verification engine clock period Symbol tSYS tENG (Within the recommended operating range) Conditions Min. Max. Unit Frequency division value 1/2 (clock frequency φ = fEX/2) 41.57 100 ns Frequency division value 1/4 (clock frequency φ = fEX/4) 83.13 200 ns Frequency division value 1/8 (clock frequency φ = fEX/8) 166.26 400 ns Frequency division value 1/16 (clock frequency φ = fEX/16) 332.51 800 ns Frequency division value 1/1 (clock frequency = fEX) 20.79 50 ns Frequency division value 1/2 (clock frequency = fEX/2) 41.57 100 ns Frequency division value 1/4 (clock frequency = fEX/4) 83.13 200 ns Frequency division value 1/8 (clock frequency = fEX/8) 166.26 400 ns Frequency division value 1/16 (clock frequency = fEX/16) 332.51 800 ns (3) Reset Input Item Reset input low level width (Within the recommended operating range) Symbol tRST Pins RST Conditions Min. Max. Unit Clock oscillation stabilized 4/fEX + 20 — ns tRST RST Fig. 1. Reset Input Timing –7– CXD4000R (4) Interrupt Input Item (Within the recommended operating range) Symbol Pins Min. Max. Unit 20 — ns tsys + 20 — ns PS5 32/fEX + 20 — ns PS7 128/fEX + 20 — ns Conditions Noise filer not selected External interrupt high and low level width tIH tIL CPU clock PB0 to PB3 Noise filter selected tIH tIL PB0 to PB3 Fig. 2. Interrupt Input Timing (5) A/D Converter Characteristics Item (Within the recommended operating range) Symbol Conditions Min. Typ. Resolution Max. 8 Conversion rate FCMAX VIN = 0.1AVD to 0.9AVD, FIN = 1kHz, ramp wave 0.5 Supply current Iop FIN = 100kHz, sine wave — Standby current Istb ADC standby Reference current Iref Integral non-linearity error ElAD Differential non-linearity error EdAD Endpoint method (6) D/A Converter Characteristics Item Symbol Unit bits 12 MHz 2.9 — mA — — 1 µA — 628 — µA — 0.7 — LSB — 0.65 — LSB (Within the recommended operating range) Measurement conditions Resolution Endpoint method Min. Typ. Max. Unit — 8 — bits — 0.34 — LSB Linearity error ElDA Differential linearity error EdDA — 0.17 — LSB Output full-scale voltage VFS — DAC_AVD – 1LSB — V –8– CXD4000R (7) Serial Transfer SCK = Output mode (Within the recommended operating range) Item Symbol tCSH tSCKE tSCKD tSOE tSOD tSCKL1 tSCKHW1 tSCKLW1 tSCKC1 SIOCS high level width SIOCS ↓ → SCK enable SIOCS ↑ → SCK disable SIOCS ↓ → SO enable SIOCS ↑ → SO disable SIOCS ↓ → SCK low SCK high pulse width SCK low pulse width SCK cycle time Conditions Min. Max. 2tsys + 20 Unit ns CS automatic transfer mode 2tsys + 50 ns 2tsys + 50 ns 2tsys + 50 ns 2tsys + 50 ns 4tsys ns 8/fEX – 20 ns 8/fEX – 20 ns 16/fEX ns SI input data setup time (activated by SCK ↓) tSIS1 2tsys + 50 ns SI input data hold time (activated by SCK ↓) tSIH1 0 ns SCK ↓ → SO delay time tSOEE ns 30 tCSH SIOCS tSCKC1 tSCKL1 tSCKE tSCKLW1 tSCKHW1 tSCKD SCK (output) ∗1 ∗1 tSIS1 SI tSIH1 Input tSOE tSOEE tSOD SO ∗1 Output disabled state (Set to high level by an internal pull-up resistor.) Fig. 7-1. Serial Transfer Timing (SCK: Output mode) –9– CXD4000R SCK = Input mode (Within the recommended operating range) Item Symbol SIOCS high level width SIOCS ↓ → SCK low∗2 SIOCS ↓ → SO enable SIOCS ↑ → SO disable SCK high pulse width SCK low pulse width SCK cycle time tCSH tSCKL2 tSOE tSOD tSCKH2 tSCKL2 tSCKC2 Conditions CS automatic transfer mode Min. Max. Unit 2tsys + 20 ns 4tsys + 20 ns 2tsys + 50 ns 2tsys + 50 ns tsys + 20 tsys + 20 2tsys + 40 ns ns ns SI input data setup time (activated by SCK ↑) tSIS2 20 ns SI input data hold time (activated by SCK ↑) tSIH2 20 ns SCK ↓ → SO delay time tSOEE2 3tsys + 50 ∗2 Even if SCK goes to low level before SIOCS falls, this is ignored. tCSH SIOCS tSCKC2 tSCKL2 tSCKLW2 tSCKH2 tSCKHW2 SCK (input) tSIS2 SI tSIH2 Input tSOE tSOEE2 tSOD SO Fig. 7-2. Serial Transfer Timing (SCK: Input mode) – 10 – ns CXD4000R (8) External Memory Interface Read Timing (Within the recommended operating range) Item Chip select pulse width∗1 Read strobe pulse width∗1 Address CSn ↓ → RD ↓ Read data setup time Read data hold time∗2 Symbol tRCS tRD tCSRD tDS tDH Min. Max. Unit (2 + BWTn) × tsys – 20 (2 + BWTn) × tsys + 20 ns (1 + BWTn) × tsys – 20 (1 + BWTn) × tsys + 20 ns tsys – 20 tsys + 20 ns 50 — ns 0 — ns ∗1 BWTn: Number of waits setting ∗2 Prescribed from the timing at which any of A0 to A20, CSn or RD first becomes invalid. t2 t1 A0 to A20 tRCS CSn tCSRD tRD RD tDS tDH D0 to D15 Fig. 8-1. External Memory Interface Timing (Read) – 11 – CXD4000R Write Timing (Within the recommended operating range) Item Symbol tWCS tWR tCSWR tWRCS tDWR tWRD Chip select pulse width Read strobe pulse width Address CSn ↓ → WR ↓ WR ↑ → address CSn ↑ Write data enable → WR ↑ WR ↑ → write data disable t1 Min. Max. (3 + BWTn) × tsys – 20 (3 + BWTn) × tsys + 20 ns (1 + BWTn) × tsys – 20 (1 + BWTn) × tsys + 20 ns tsys/2 – 20 tsys/2 + 20 tsys/2 – 20 tsys/2 + 20 (1.5 + BWTn) × tsys – 20 (1.5 + BWTn) × tsys + 20 10 tsys/2 + 20 ns t2 t3 A0 to A20 tWCS CSn tCSWR Unit tWR tWRCS WR tDWR D0 to D15 Fig. 8-2. External Memory Interface Timing (Write) – 12 – tWRD ns ns ns CXD4000R (9) USB Interface (Within the recommended operating range) Item Symbol Conditions Min. Max. Unit 28 43 Ω Output impedance Zdrv Rise time Tr CL = 50pF 4 20 ns Fall time Tf CL = 50pF 4 20 ns Rise/fall ratio Tr/Tf CL = 50pF 0.9 1.1 — Output signal crossover voltage Vcrs CL = 50pF 1.3 2.0 V VDD 1.5kΩ 27Ω∗1 DP CXD4000R 27Ω∗1 DM ∗1 Connect the DP and DM pins to the USB cable through 27Ω resistors. Fig. 9. USB Interface Connection Circuit – 13 – CXD4000R Package Outline Unit: mm 120PIN LQFP (PLASTIC) 18.0 ± 0.2 1.7 MAX 1.4 ± 0.1 16.0 ± 0.1 90 S 61 0.1 91 S 60 B A 31 120 1 30 0.5 0.22 ± 0.05 0.1 M S 0˚ to 10˚ DETAIL A 0.145 ± 0.03 (0.2) (0.125) 0.6 ± 0.15 0.22 ± 0.05 (0.5) 0.25 (17.0) 0.1 ± 0.05 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-120P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP120-P-1616 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.8g JEDEC CODE LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SPEC. COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm – 14 – Sony Corporation