24-Bit Audio Digital Signal Processor Overview The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. While the DSP56374 is designed with flexibility and thus is versatile in the types of applications it can support, it does include a powerful set of audio features, including various built-in audio peripherals and embedded software designed to meet the needs of both consumer and automotive audio applications. The DSP56374 provides a wealth of audio processing functions including an operating system, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, and many more. The DSP56374 also supports various matrix decoders and sound field processing algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Motorola Symphony™ DSP family. This design provides a two-fold performance increase over Motorola’s popular DSP56000 core family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, patch module, and direct memory access (DMA). The DSP56374 is available in either a 52-pin or 80pin TQFP at 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.25 V. DSP56374 Features On-chip Memory Configuration DSP Modular Chassis > 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM. > 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM. > 6Kx24 Bit Program RAM. > Various memory switches are available. See memory table below. > 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism > 1.25 V core with a 3.3 V peripheral I/O. > 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V (0°C to 70°C for consumer-grade devices; -40°C to 85°C for automotive-grade devices). > Object Code Compatible with the 56K core. > Data ALU with a 24 x 24 bit multiplieraccumulator and a 56-bit barrel shifter. 16-bit arithmetic support. > Program Control with position independent code support and instruction cache support. > Six-channel DMA controller. > Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 1024), predivider factors (1 to 32) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. > Internal address tracing support and OnCE for Hardware/Software debugging. > JTAG port. > Very low-power CMOS design, fully static design with operating frequencies down to DC. > STOP and WAIT low-power standby modes. > STOP and WAIT low-power standby modes. 15* 5 12* 12 3 Peripheral Modules Memory Expansion Area Triple Timer Program RAM 6k × 24 X Data RAM 6k × 24 Y Data RAM 6k × 24 ROM 20k × 24 ROM 4k × 24 ROM 4k × 24 Peripheral Expansion Area Address Generation Unit YAB YM_EB ESAI_1 Interface XM_EB ESAI Interface PM_EB GPIO PIO_EB SHI Interface Watch dog Timer XAB PAB Six Channel DMA Unit DAB 24-Bit Bootstrap ROM DSP56300 Core DDB Internal Data Bus Switch Clock Gen. YDB XDB PDB GDB Power Mgmt. PLL Program Interrupt Controller Program Decode Controller Program Address Generator 4 Data ALU 24 × 24+56→56-bit MAC Two 56-bit Accumulators JTAG OnCE 56-bit Barrel Shifter XTAL EXTAL RESET PINIT/NMI MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO MODD/IRQD/GPIO * ESAI_1 and dedicated GPIO pins are not available in the 52-pin package. Bit Settings Memory Sizes (24-bit words) MSW1 MSW0 MS Prog RAM X Data RAM Y Data RAM Prog ROM X Data ROM Y Data ROM X X 0 6K 6K 6K 20K 4K 4K 0 0 1 2K 10K 6K 20K 4K 4K 0 1 1 4K 8K 6K 20K 4K 4K 1 0 1 8K 4K 6K 20K 4K 4K 1 1 1 10K 4K 4K 20K 4K 4K Learn More: For more information about Freescale products, please visit www.freescale.com. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004 DSP56374FS REV 2 > Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. > Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note 80pin package only. > Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO, support for 8, 16 and 24-bit words. > Triple Timer module (TEC). > Hardware Watchdog Timer > Most pins of unused peripherals may be programmed as GPIO lines. Up to 47 pins can be configured as GPIO on the 80-pin package and 20 pins on the 52-pin package.