Revised December 2000 GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock General Description Features The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. ■ Bidirectional interface between GTLP and TTL logic levels Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. ■ Designed with edge rate control circuitry to reduce output noise on the GTLP port ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced CMOS technology ■ Bushold data inputs on the A port eliminates the need for external pull-up resistors on unused inputs. ■ Power up/down and power off high impedance for live insertion ■ 5 V tolerant inputs and outputs on the LVTTL ports ■ Open drain on GTLP to support wired-or connection ■ Flow through pinout optimizes PCB layout ■ D-type flip-flop, latch and transparent data paths ■ A Port source/sink −32 mA/+32 mA ■ GTLP Buffered CLKAB signal available (CLKOUT) Ordering Code: Order Number Package Number GTLP16616MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide Package Description GTLP16616MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS500017 www.fairchildsemi.com GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock June 1997 GTLP16616 Pin Descriptions Connection Diagram Pin Names Description OEAB A-to-B Output Enable (Active LOW) OEBA B-to-A Output Enable (Active LOW) CEAB A-to-B Clock Enable (Active LOW) CEBA B-to-A Clock Enable (Active LOW) LEAB A-to-B Latch Enable (Transparent HIGH) LEBA B-to-A Latch Enable (Transparent HIGH) VREF GTLP Reference Voltage CLKAB A-to-B Clock CLKBA B-to-A Clock A1-A17 A-to-B Data Inputs or B-to-A 3-STATE Outputs B1-B17 B-to-A Data Inputs or A-to-B Open Drain Outputs CLKIN B-to-A Buffered Clock Output CLKOUT GTLP Buffered Clock Output of CLKAB Functional Description The GTLP16616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control both the 17 bits of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used. Truth Table (Note 1) Inputs Output B Mode X Z Latched X B0 (Note 2) storage X B0 (Note 3) of A data L L Transparent H H CEAB OEAB LEAB X H L L L L X L H X X L H X L L L ↑ L L L L L ↑ H H of A data H L L X X B0 (Note 3) Clock inhibit CLKAB A X X L H L L Clocked storage Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH prior to LEAB going LOW. Note 3: Output level before the indicated steady-state input conditions were established. www.fairchildsemi.com 2 GTLP16616 Logic Diagram 3 www.fairchildsemi.com GTLP16616 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VI) −0.5V to +7.0V Recommended Operating Conditions (Note 6) Supply Voltage VCC DC Output Voltage (VO) VCC −0.5V to +7.0V Outputs 3-STATE −0.5V to VCC + 0.5V Outputs Active (Note 5) 4.75V to 5.25V Bus Termination Voltage (VTT) GTLP DC Output Sink Current into 1.35V to 1.65V Input Voltage (VI) A Port IOL 64 mA on A Port and Control Pins DC Output Source Current from 0.0V to 5.5V HIGH Level Output Current (IOH) −64 mA A Port IOH −32 mA A Port DC Output Sink Current LOW Level Output Current (IOL) 80 mA into B Port in the LOW State, IOL +32 mA A Port DC Input Diode Current (IIK) +34 mA B Port VI < 0V −50 mA VO < 0V −50 mA VO > VCC +50 mA Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. >2000V ESD Rating −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Storage Temperature (TSTG) 3.15V to 3.45V VCCQ −65°C to +150°C Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Test Conditions Min Typ B Port VREF +0.1 Others 2.0 B Port 0.0 VTT GTLP 1.0 GTL 0.8 VCC = 3.15V, VIK II = −18 mA Units V V Others VREF Max (Note 7) VREF −0.1 V 0.8 V V V −1.2 V VCCQ = 4.75V VOH VOL A Port A Port VCC, VCCQ = Min to Max (Note 8) IOH = −100 µA VCC = 3.15V IOH = −8 mA VCC −0.2 2.4 VCCQ = 4.75V IOH = −32 mA 2.0 V VCC, VCCQ = Min to Max (Note 8) IOL = 100 µA 0.2 VCC = 3.15V IOL = 32 mA 0.5 V VCCQ = 4.75V II B Port VCC = 3.15V VCCQ = 4.75V IOL = 34 mA 0.65 V Control Pins VCC, VCCQ = 0 or Max VI = 5.5V or 0V ±10 µA A Port VCC = 3.45V VI = 5.5V 20 VCCQ = 5.25V VI = VCC 1 VI = 0 B Port VCC = 3.45V VI = VCC 5 VCCQ = 5.25V VI = 0 −5 IOFF A Port and Control Pins VCC = VCCQ = 0 II(hold) A Port IOZH IOZL VI or VO = 0 to 4.5V 100 VCC = 3.15V, VI = 0.8V 75 VCCQ = 4.75V VI = 2.0V −20 A Port VCC = 3.45V, VO = 3.45V 1 B Port VCCQ = 5.25V VO = 1.5V 5 A Port VCC = 3.45V, VO = 0 −20 B Port VCCQ = 5.25V VO = 0.65V −10 www.fairchildsemi.com 4 µA −30 µA µA µA µA µA Symbol (Continued) Test Conditions Min Typ Max (Note 7) ICCQ A or B VCC = 3.45V, Outputs HIGH 30 40 (VCCQ) Ports VCCQ = 5.25V, Outputs LOW 30 40 VI = VCCQ or GND Outputs Disabled 30 40 VCC = 3.45V, VCCQ = 5.25V, IO = 0, Outputs HIGH 0 1 Outputs LOW 0 1 VI = VCC or GND Outputs Disabled 0 1 One Input at 2.7V 0 1 IO = 0, ICC A or B (VCC) Ports ∆ICC A Port and VCC = 3.45V, (Note 9) Control Pins VCC = 5.25V, Units mA mA mA A or Control Inputs at VCC or GND CIN Control Pins VI = VCCQ or 0 8 CI/O A Port VI = VCCQ or 0 9 CI/O B Port VI = VCCQ or 0 6 pF Note 7: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C. Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX Maximum Clock Frequency tW Pulse Duration tS tH Min 175 LEAB or LEBA HIGH 3.0 CLKAB or CLKBA HIGH or LOW 3.2 A before CLKAB↑ 0.5 B before CLKBA↑ 3.1 A before LEAB↓ 1.3 B before LEBA↓ 3.7 CEAB before CLKAB↑ 0.7 CEBA before CLKBA↑ 1.0 A after CLKAB↑ 1.5 B after CLKBA↑ 0.0 A after LEAB↓ 0.5 B after LEBA↓ 0.0 CEAB after CLKAB↑ 1.5 CEBA after CLKBA↑ 1.7 Max Unit MHz ns Setup Time Hold Time 5 ns ns www.fairchildsemi.com GTLP16616 DC Electrical Characteristics GTLP16616 AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH From To (Input) (Output) A B LEAB B CLKAB B CLKAB CLKOUT OEAB B or CLKOUT 4.3 6.5 5.0 8.2 1.8 4.5 6.7 1.5 5.3 8.7 1.8 4.6 6.7 1.5 5.4 8.7 3.0 6.2 10.0 3.0 5.7 10.0 1.6 4.4 6.3 1.3 6.1 9.8 ns tPHL tSKEW 1.0 1.0 ns tPHL tPLH B (Note 11) CLKOUT 0 2 tRISE Transition time, B outputs (20% to 80%) 2.6 tFALL Transition time, B outputs (20% to 80%) 2.6 tPLH B A LEBA A CLKBA A 8.2 7.2 2.1 4.2 6.3 1.9 3.3 5.0 2.3 4.4 6.8 2.1 3.5 5.2 ns CLKOUT CLKIN 3.0 6.0 10.0 3.0 6.4 10.0 1.5 5.0 6.4 1.4 3.9 8.0 ns tPHL tPZH, tPZL 5.6 5.0 ns tPHL tPLH 2.0 1.4 ns tPHL tPLH ns ns tPHL tPLH Unit ns tPHL tPLH Max ns tPHL tPLH Typ (Note 10) ns tPHL tPLH Min OEBA A or CLKIN ns tPHZ, tPLZ Note 10: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for the CLKOUT pin and any B output transition when measured with reference to CLKAB↑. This guarantees the relationship between B output data and CLKOUT such that data is coincident or ahead of CLKOUT. This specification is guaranteed but not tested. www.fairchildsemi.com 6 Test Circuit for A Outputs Test Circuit for B Outputs CL includes probes and jig capacitance. CL includes probes and jig capacitance. For B Port outputs, CL = 30 pF is used for worst case edge rate. Voltage Waveforms Pulse Duration (Vm = 1.5V for A Port and 1.0V for B Port) Voltage Waveforms Propagation Delay and Setup and Hold Times (Vm = 1.5V for A Port and 1.0V for B Port) Voltage Waveforms Enable and Disable Times (A Port) Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 7 www.fairchildsemi.com GTLP16616 Test Circuits and Timing Waveforms GTLP16616 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300” Wide Package Number MS56A www.fairchildsemi.com 8 GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com