HB56A472E Series 4,194,304-word × 72-bit High Density Dynamic RAM Module Description The HB56A472E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4- and 8-byte processor applications. The HB56A472E is a 4 M × 72 dynamic RAM module, mounted 18 pieces of 16-Mbit DRAM (HM5116400BTS) sealed in TSOP package and 2 pieces of 16-bit BiCMOS line driver (74ABT16244) sealed in TSSOP package. An outline of the HB56A472E is 168-pin socket type package (dual lead out). Therefore, the HB56A472E makes high density mounting possible without surface mount technology. The HB56A472E provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. Features • 168-pin socket type package (dual lead out) Lead pitch: 1.27 mm • Single 5 V (± 5%) supply • High speed Access time: t RAC = 60/70/80 ns (max) Access time: t CAC = 20/23/25 ns (max) • Low power dissipation Active mode: 7.90/6.95/6.48 W (max) Standby mode (TTL): 525 mW (max) Standby mode (CMOS): 431 mW (max) • Buffered inputs except RAS and DQ • 4 Byte interleave enabled, dual address inputs (A0/B0) • Fast page mode capability • 4,096 refresh cycle: 64 ms • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh • TTL compatible This Material Copyrighted by Its Respective Manufacturer Datasheet Title Ordering Information Type No. Access Time Package Contact Pad HB56A472E-6B 60 ns 168-pin dual lead out socket type Gold HB56A472E-7B 70 ns 168-pin dual lead out socket type Gold HB56A472E-8B 80 ns 168-pin dual lead out socket type Gold Pin Arrangement Front side Back side 1Pin 10Pin 11Pin 40Pin 85Pin 94Pin 95Pin 124Pin 41Pin 125Pin 84Pin 168Pin Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 16 DQ12 31 OE0 46 CE4 2 DQ0 17 DQ13 32 VSS 47 NC 3 DQ1 18 VCC 33 A0 48 WE2 4 DQ2 19 DQ14 34 A2 49 VCC 5 DQ3 20 DQ15 35 A4 50 NC 6 VCC 21 DQ16 36 A6 51 NC 7 DQ4 22 DQ17 37 A8 52 DQ18 8 DQ5 23 VSS 38 A10 53 DQ19 9 DQ6 24 NC 39 NC 54 VSS 10 DQ7 25 NC 40 VCC 55 DQ20 11 DQ8 26 VCC 41 NC 56 DQ21 12 VSS 27 WE0 42 NC 57 DQ22 13 DQ9 28 CE0 43 VSS 58 DQ23 14 DQ10 29 NC 44 OE2 59 VCC 15 DQ11 30 RE0 45 RE2 60 DQ24 2 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Pin Arrangement (cont) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 61 NC 88 DQ38 115 NC 142 DQ59 62 NC 89 DQ39 116 VSS 143 VCC 63 NC 90 VCC 117 A1 144 DQ60 64 NC 91 DQ40 118 A3 145 NC 65 DQ25 92 DQ41 119 A5 146 NC 66 DQ26 93 DQ42 120 A7 147 NC 67 DQ27 94 DQ43 121 A9 148 NC 68 VSS 95 DQ44 122 A11 149 DQ61 69 DQ28 96 VSS 123 NC 150 DQ62 70 DQ29 97 DQ45 124 VCC 151 DQ63 71 DQ30 98 DQ46 125 NC 152 VSS 72 DQ31 99 DQ47 126 B0 153 DQ64 73 VCC 100 DQ48 127 VSS 154 DQ65 74 DQ32 101 DQ49 128 NC 155 DQ66 75 DQ33 102 VCC 129 NC 156 DQ67 76 DQ34 103 DQ50 130 NC 157 VCC 77 DQ35 104 DQ51 131 NC 158 DQ68 78 VSS 105 DQ52 132 PDE 159 DQ69 79 PD1 106 DQ53 133 VCC 160D DQ70 80 PD3 107 VSS 134 NC 161 DQ71 81 PD5 108 NC 135 NC 162 VSS 82 PD7 109 NC 136 DQ54 163 PD2 83 ID0 (VSS) 110 VCC 137 DQ55 164 PD4 84 VCC 111 NC 138 VSS 165 PD6 85 VSS 112 NC 139 DQ56 166 PD8 86 DQ36 113 NC 140 DQ57 167 ID1 (VSS) 87 DQ37 114 NC 141 DQ58 168 VCC 3 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Pin Description Pin Name Function A0–A11, B0 Address input: Row address: Column address: Refresh address: DQ0–DQ71 Data-in/Data-out RE0, RE2 Row address strobe (RAS) CE0, CE4 Column address strobe (CAS) WE0, WE2 Read/write enable OE0, OE2 Output enable VCC Power supply VSS Ground PD1–PD8 Presence detect ID0, ID1 ID bit PDE Presence detect enable NC No connection A0–A11, B0 A0–A11, B0 A0–A9, B0 A0–A11, B0 Presence Detect Pin Assignment PDE = Low PDE = High Pin Name Pin No. 60 ns 70 ns 80 ns PD1 79 1 1 1 High-Z PD2 163 1 1 1 High-Z PD3 80 0 0 0 High-Z PD4 164 1 1 1 High-Z PD5 81 0 0 0 High-Z PD6 165 1 0 1 High-Z PD7 82 1 1 0 High-Z PD8 166 0 0 0 High-Z Note: 1: High level (driver output) 0: Low level (driver output) 4 This Material Copyrighted by Its Respective Manufacturer All Datasheet Title Block Diagram RE0 RE2 OE0 OE2 WE0 WE2 CE0 CE4 DQ0 DQ1 DQ2 DQ3 I/O CAS I/O I/O I/O RAS WE OE DQ4 DQ5 DQ6 DQ7 I/O CAS I/O I/O I/O RAS WE OE DQ8 DQ9 DQ10 DQ11 I/O CAS I/O I/O I/O RAS WE OE DQ12 DQ13 DQ14 DQ15 I/O CAS I/O I/O I/O RAS WE OE DQ16 DQ17 DQ18 DQ19 I/O CAS I/O I/O I/O RAS WE OE DQ20 DQ21 DQ22 DQ23 I/O CAS I/O I/O I/O RAS WE OE DQ24 DQ25 DQ26 DQ27 I/O CAS I/O I/O I/O RAS WE OE DQ28 DQ29 DQ30 DQ31 I/O CAS I/O I/O I/O RAS WE OE DQ32 DQ33 DQ34 DQ35 I/O CAS I/O I/O I/O RAS WE OE D0 D1 D2 D3 D4 D5 D6 D7 D8 DQ36 DQ37 DQ38 DQ39 I/O CAS I/O I/O I/O RAS WE OE DQ40 DQ41 DQ42 DQ43 I/O CAS I/O I/O I/O RAS WE OE DQ44 DQ45 DQ46 DQ47 I/O CAS I/O I/O I/O RAS WE OE DQ48 DQ49 DQ50 DQ51 I/O CAS I/O I/O I/O RAS WE OE DQ52 DQ53 DQ54 DQ55 I/O CAS I/O I/O I/O RAS WE OE DQ56 DQ57 DQ58 DQ59 I/O CAS I/O I/O I/O RAS WE OE DQ60 DQ61 DQ62 DQ63 I/O CAS I/O I/O I/O RAS WE OE DQ64 DQ65 DQ66 DQ67 I/O CAS I/O I/O I/O RAS WE OE DQ68 DQ69 DQ70 DQ71 I/O CAS I/O I/O I/O RAS WE OE D9 D10 D11 D12 D13 D14 D15 D16 D17 PD1 to PD8 A0 D0 to D8 VCC PD1 B0 D9 to D17 VCC PD2 A1 to A11 D0 to D17 VSS PD3 VCC D0 to D17, 74ABT16244 VCC PD4 VSS D0 to D17, 74ABT16244 VSS PD5 VCC VSS VCC VSS VSS PD6 0.1 µ F 20PCS 0.68 µ F 4PCS PD7 PD8 Note : D0 to D17 : HM5116400 : 74ABT16244 5 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to +7.0 V Supply voltage relative to VSS VCC –0.5 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 19 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 4.75 5.0 5.25 V 1 Input high voltage VIH 2.4 — 5.5 V 1 Input low voltage VIL –0.5 — 0.8 V 1 Note: 1. All voltage referred to VSS 6 This Material Copyrighted by Its Respective Manufacturer Note Datasheet Title DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 5%, VSS = 0 V) HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Test Conditions Notes Operating current I CC1 — 1504 — 1324 — 1234 mA t RC = min 1,2 Standby current I CC2 — 100 — 100 — 100 mA TTL interface RAS, CAS = VIH Dout = High-Z — 82 — 82 — 82 mA CMOS interface RAS, CAS ≥ V CC-0.2 V Dout = High-Z RAS-only refresh current I CC3 — 1504 — 1324 — 1234 mA t RC = min 2 Standby current I CC5 — 154 154 154 RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 1504 — 1324 — 1234 mA t RC = min Fast page mode current I CC7 — 1324 — 1144 — 964 mA t PC = min Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 5.5 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 5.5 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC VCC 2.4 V High Iout = –5.0 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA — — mA 1, 3 Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25°C, VCC = 5 V ± 5%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 20 pF 1 Input capacitance (CAS, WE, OE) CI2 — 20 pF 1 Input capacitance (RAS) CI3 — 78 pF 1 I/O capacitance (DQ) CI/O — 20 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 7 This Material Copyrighted by Its Respective Manufacturer Datasheet Title AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V)*1, *2, *18 Test Conditions • Input rise and fall time: 5 ns • Input timing reference levels: 0.8 V, 2.4 V • Output load: 2 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write, and Refresh Cycles (Common parameters) HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — 150 — ns RAS precharge time t RP 40 — 50 — 60 — ns CAS precharge t CP 10 — 10 — 10 — ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns CAS pulse width t CAS 15 10000 18 10000 20 10000 ns Row address setup time t ASR 5 — 5 — 5 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 10 — 15 — 15 — ns RAS to CAS delay time t RCD 20 40 20 47 20 55 ns 3 RAS to column address delay time t RAD 15 25 15 30 15 35 ns 4 RAS hold time t RSH 20 — 23 — 25 — ns CAS hold time t CSH 60 — 70 — 80 — ns CAS to RAS precharge time t CRP 10 — 10 — 10 — ns OE to Din delay time t OED 20 — 23 — 25 — ns 5 OE delay time from Din t DZO 0 — 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — 0 — ns 6 Transition time (rise and fall) tT 3 50 3 50 3 50 ns 7 Refresh period t REF — 64 — 64 — 64 ms 19 8 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Read Cycle HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 — 80 ns 8, 19 Access time from CAS t CAC — 20 — 23 — 25 ns 9, 10, 17 Access time from address t AA — 35 — 40 — 45 ns 9, 11, 17 Access time from OE t OEA — 20 — 23 — 25 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns 12 Read command hold time to RAS t RRH 0 — 0 — 0 — ns 12 Column address to RAS lead time t RAL 35 — 40 — 45 — ns Column address to CAS lead time t CAL 30 — 35 — 40 — ns CAS to output in low-Z t CLZ 2 — 2 — 2 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 20 — 20 — 20 ns 13 Output buffer turn-off to OE t OEZ — 20 — 20 — 20 ns 13 CAS to Din delay time t CDD 20 — 23 — 25 — ns 5 Write Cycle HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns Write command hold time t WCH 10 — 15 — 15 — ns Write command pulse width t WP 10 — 10 — 10 — ns Write command to RAS lead time t RWL 20 — 23 — 25 — ns Write command to CAS lead time t CWL 15 — 18 — 20 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 Data-in hold time t DH 15 — 20 — 20 — ns 15 14 9 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Read-Modify-Write Cycle HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 155 — 181 — 205 — ns RAS to WE delay time t RWD 90 — 103 — 115 — ns 14 CAS to WE delay time t CWD 40 — 46 — 50 — ns 14 Column address to WE delay time t AWD 55 — 63 — 70 — ns 14 OE hold time from WE t OEH 15 — 18 — 20 — ns Refresh Cycle HB56A472E 60 ns Parameter Symbol Min 70 ns 80 ns Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 10 — 10 — 10 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 5 — 5 — 5 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 0 — 0 — 0 — ns Fast Page Mode Cycle HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — 50 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 40 — 45 — 50 ns 9, 17 40 — 45 — 50 — ns RAS hold time from CAS precharge t CPRH 10 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Fast Page Mode Read-Modify-Write Cycle HB56A472E 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PRWC 85 — 96 — 105 — ns 60 — 68 — 75 — ns WE delay time from CAS precharge t CPW 14 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max) 11. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 12. Either t RCH or tRRH must be satisfied for a read cycle. 13. t OFF (max) and tOEZ (max) are defined the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, tAWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycle. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH ≥ tCWL, the DQ pins will remain open circuit (high impedance); if t OEH ≤ tCWL, invalid data will be out at each DQ. 19. t REF is determined by 4,096 refresh cycle. 11 This Material Copyrighted by Its Respective Manufacturer Datasheet Title Timing Waveforms Refer to the HM5116400B Series data sheet. Physical Outline Unit: mm/inch 133.35 5.250 127.35 5.014 4.00 Max 0.157 Max 4.00 Min 0.157 Min 3.00 0.118 84 1.270 0.050 36.83 1.450 8.89 11.43 C 0.350 0.450 2 – φ 3.00 2 – φ 0.118 1.27 ± 0.10 0.050 ± 0.004 A B 54.61 2.150 168 3.00 0.118 1 4.00 0.157 17.78 0.700 25.40 1.000 85 Detail B 1.27 0.050 12 This Material Copyrighted by Its Respective Manufacturer 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 3.125 ± 0.125 0.123 ± 0.005 1.00 ± 0.05 0.039 ± 0.002 Detail C 1.00 0.039 3.125 ± 0.125 0.123 ± 0.005 0.25 Max 0.010 Max 2.54 Min 0.100 Min Detail A 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004