a High Efficiency Step-Down Switching Regulator Controllers ADP1147-3.3/ADP1147-5 FEATURES Greater Than 95% Efficiency Current Mode Switching Architecture Provides Superior Load and Line Transient Response Wide Input Voltage Range 3.5 V* to 16 V User Defined Current Limit Short Circuit Protection Shutdown Pin Low Dropout Voltage Low Standby Current 160 mA typ Low Cost Available in 8-Lead PDIP or 8-Lead SOIC FUNCTIONAL BLOCK DIAGRAM VIN P-DRIVE GROUND ADP1147 R Q S Q R S S RSENSE** 0.05V CC RC 3300pF 1kV +C OUT CT 470pF ADP1147 CT REFERENCE SENSE(–) ITH SHUTDOWN VIN = 6 VOLTS 95 VIN P-DRIVE SHUTDOWN ITH SENSE(+) 100kV For designs requiring even greater efficiencies refer to the ADP1148 data sheet. VOUT 5V/2A 390mF 0V = NORMAL 1.5V = SHUTDOWN 1.25V A very low dropout voltage with excellent output regulation can be obtained by minimizing the dc resistance of the Inductor, the RSENSE resistor, and the RDS(ON) of the P-MOSFET. The power savings mode conserves power by reducing switching losses at lower output currents. When the output load current falls below the minimum required for the continuous mode the ADP1147 will automatically switch to the power savings mode. It will remain in this mode until the inductor requires additional current or the sleep mode is entered. In sleep mode with no load the standby power consumption of the device is reduced to 2.0 mW typical at VIN = 10 V. 1000pF 90 EFFICIENCY – % L* 50mH D1 30BQ040 IN VIN G 100 P-CHANNEL IRF7204 100mF 13kV CT 5pF VOS VTH1 VTH2 OFF-TIME CONTROL *3.5 volt operation is for the ADP1147-3.3. +C C 10mV to 150mV T The ADP1147 is part of a family of High Efficiency Step-Down Switching Regulators. These regulators offer superior load and line transient response, a user defined current limit and an automatic power savings mode. The automatic power savings mode is used to maintain efficiency at lower output currents. The ADP1147 incorporates a constant off-time, current mode switching architecture to drive an external P-channel MOSFET at frequencies up to 250 kHz. Constant off-time switching generates a constant ripple current in the external inductor. This results in a wider input voltage operating range of 3.5 V* to 16 V, and a less complex circuit design. 1mF B 1 SLEEP GENERAL DESCRIPTION + V 2 APPLICATIONS Portable Computers Modems Cellular Telephones Portable Equipment GPS Systems Handheld Instruments VIN (5.2V TO 12V) SENSE(+) SENSE(–) VIN = 10 VOLTS 85 80 75 70 SENSE(–) 65 GND *COILTRONICS CTX 50–2MP **KRL SL-1-C1-0R050J SHUTDOWN Figure 1. High Efficiency Step-Down Converter (Typical Application) 60 1 10 100 LOAD CURRENT – mA 1k 10k Figure 2. ADP1147-5 Typical Efficiency, Figure 1 Circuit REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADP1147-3.3/ADP1147-5–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (08C ≤ T ≤ +708C , V 1 A IN = 10 V, VSHUTDOWN = 0 V unless otherwise noted) ADP1147 Min Typ Max Units 3.23 4.90 3.33 5.05 3.43 5.20 V V –40 0 +40 mV ∆VOUT 40 60 50 65 100 mV mV mV p-p IQ 1.6 160 160 10 2.3 250 250 22 mA µA µA µA 120 10 150 170 mV mV 120 10 150 170 mV mV 0.6 0.8 2 V 1.2 5 µA 50 70 2 90 10 µA µA 4 5 6 µs 100 200 ns Parameter Conditions VS REGULATED OUTPUT VOLTAGE ADP1147-3-3 ADP1147-5 VIN = 9 V ILOAD = 700 mA ILOAD = 700 mA VOUT OUTPUT VOLTAGE LINE REGULATION TA = +25°C VIN = 7 V to 12 V, ILOAD = 50 mA ∆VOUT OUTPUT VOLTAGE LOAD REGULATION ADP1147-3.3 ADP1147-5 Sleep Mode Output Ripple 5 mA < ILOAD < 2 A 5 mA < ILOAD < 2 A TA = +25°C, ILOAD = 0 A INPUT DC SUPPLY CURRENT2 Normal Mode Sleep Mode (ADP1147-3.3) Sleep Mode (ADP1147-5) Shutdown TA = +25°C 4 V < VIN < 16 V 4 V < VIN < 16 V 4 V < VIN < 16 V VSHUTDOWN = 2.1 V, 4 V < VIN < 16 V CURRENT SENSE THRESHOLD VOLTAGE ADP1147-3.3 ADP1147-5 VSENSE(–) = VOUT+ 100 mV (Forced) TA = +25°C VSENSE(–) = VOUT– 100 mV (Forced) V5–V4 VSENSE(–) = VOUT+ 100 mV (Forced) TA = +25°C VSENSE(–) = VOUT– 100 mV (Forced) SHUTDOWN PIN THRESHOLD TA = +25°C V6 SHUTDOWN PIN INPUT CURRENT 0 V < VSHUTDOWN < 8 V, VIN = 16 V TA = +25°C I6 CT PIN DISCHARGE CURRENT TA = +25°C, VOUT in Regulation, VSENSE(–) = VOUT, VOUT = 0 V I2 OFF-TIME CT = 390 pF, ILOAD = 700 mA tOFF DRIVER OUTPUT TRANSITION TIMES TA = +25°C CL = 3000 pF (Pin 8) VIN = 6 V tr, tf NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Input Supply Voltage (Pin 1) . . . . . . . . . . . . . . 16 V to –0.3 V Continuous Output Current (Pin 8) . . . . . . . . . . . . . . 50 mA Sense Voltages (Pins 4, 5) . . . . . . . . . . . . . . . . 10 V to –0.3 V Operating Ambient Temperature Range . . . . . 0°C to +70°C Extended Commercial Temperature Range . . –40°C to +85°C Junction Temperature* . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Model Output Voltage Package Description Package Option ADP1147AN-3.3 ADP1147AR-3.3 ADP1147AN-5 ADP1147AR-5 3.3 V 3.3 V 5V 5V Plastic DIP SOIC Plastic DIP SOIC N-8 SO-8 N-8 SO-8 *TJ is calculated from the ambient temperature, T A, and power dissipation, P D, according to the following formulas: ADP1147AN-3.3, ADP1147AN-5: T J = TA + (PD × 110°C/W). ADP1147AR-3.3, ADP1147AR-5: T J = TA+(PD × 150°C/W). –2– REV. 0 ADP1147-3.3/ADP1147-5 ELECTRICAL CHARACTERISTICS (–408C ≤ T A≤ 1 +858C , VIN = 10 V, unless otherwise noted) Parameter Conditions VS REGULATED OUTPUT VOLTAGE ADP1147-3.3 ADP1147-5 VIN = 9 V ILOAD = 700 mA ILOAD = 700 mA VOUT INPUT DC SUPPLY CURRENT Normal Mode Sleep Mode (ADP1147-3.3) Sleep Mode (ADP1147-5) Shutdown 4 V < VIN < 16 V 4 V < VIN < 16 V 5 V < VIN < 16 V VSHUTDOWN = 2.1 V, 4 V < VIN < 16 V IQ VSENSE(–) = VOUT+ 100 mV (Forced) TA = +25°C VSENSE(–) = VOUT– 100 mV (Forced) VSENSE(–) = VOUT+ 100 mV (Forced) TA = +25°C VSENSE(–) = VOUT– 100 mV (Forced) V5–V4 CURRENT SENSE THRESHOLD VOLTAGE ADP1147-3.3 ADP1147-5 SHUTDOWN PIN THRESHOLD OFF-TIME CT = 390 pF, ILOAD = 700 mA ADP1147 Min Typ Max Units 3.17 4.85 3.33 5.05 3.4 5.2 V V 1.6 160 160 10 2.6 280 280 28 mA µA µA µA 120 25 150 175 mV mV 120 25 150 175 mV mV V6 0.55 0.8 2 V tOFF 3.8 5 6 µs NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Specifications subject to change without notice. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 VIN CT 3 4 ITH SENSE(–) 5 SENSE(+) 6 SHUTDOWN 7 GND 8 P-DRIVE Input Voltage. External Capacitor Connection. This capacitor sets the operating frequency of the device. The frequency is also dependent on the input voltage level. Error Amplifier Decoupling Pin. Pin 3 voltage level causes the comparator current threshold to increase. This connects to internal resistive divider, which senses the output voltage. Pin 4 is also the (–) input for the current comparator. This provides the + input to the current comparator. The offset between Pins 4 and 5 together with RSENSE establish the current trip threshold. When this pin is pulled high, it keeps the MOSFET turned off. When the pin is pulled to ground, the ADP1147 functions normally. This pin cannot be left floating. Independent ground lines must be connected separately to (a) the negative pin of COUT and (b) the cathode of the Schottky diode and the negative terminal of CIN. Provides high current drive for the MOSFET. Voltage swing is from VIN to ground at this pin. PIN CONFIGURATIONS 8-Lead Plastic DIP (N-8) VIN 1 CT 2 ADP1147 8-Lead SOIC (SO-8) 8 P-DRIVE VIN 1 7 GND CT 2 TOP VIEW ITH 3 (Not to Scale) 6 SHUTDOWN SENSE– 4 ITH 3 5 SENSE+ 8 P-DRIVE ADP1147 7 GND TOP VIEW (Not to Scale) SENSE– 4 TJMAX = 1258C, uJA = 1108C/W 5 SENSE+ TJMAX = 1258C, uJA = 1508C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP1147 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 6 SHUTDOWN –3– WARNING! ESD SENSITIVE DEVICE ADP1147-3.3/ADP1147-5–Performance Characteristics 1000 1000 200 L = 50mH RSENSE = 0.02V VSENSE = VOUT = +5V 800 800 CAPACITANCE – pF 100 L = 25mH RSENSE = 0.02V 600 VIN = +12V 400 50 200 0 0 0 VIN = +10V VIN = +7V 0 1 2 3 4 5 MAXIMUM OUTPUT CURRENT – Amps Figure 3. Selecting RSENSE vs. Maximum Output Current COUT – mF RSENSE – mV 150 100 200 FREQUENCY – kHz 0 FIGURE 1 CIRCUIT 5.10 EFFICIENCY – % EFFICIENCY – % SCHOTTKY DIODE OUTPUT VOLTAGE – V 1 AMP ADP1147 IQ 90 0.1 AMP 85 80 85 75 70 30m 0.1 0.3 IOUT – Amps 1 3 Figure 6. Typical Efficiency Losses 5.09 100mA 5.08 5.07 300mA 5.06 5.05 5.04 5 8 11 14 17 INPUT VOLTAGE – Volts 20 Figure 7. Efficiency vs. Input Voltage 5.11 5 5.11 FIGURE 1 CIRCUIT 95 80 10m 1 2 3 4 (VIN – VOUT) VOLTAGE – Volts Figure 5. Selecting Minimum Output Capacitor vs. (VIN – VOUT) and Inductor 95 90 L = 50mH RSENSE = 0.05V 0 300 Figure 4. Operating Frequency vs. Timing Capacitor I2R GATE CHARGE 400 200 100 100 600 5.03 1 AMP 4 8 12 INPUT VOLTAGE – V 16 Figure 8. ADP1147-5 Output Voltage vs. Input Voltage 1.6 40 FIGURE 1 CIRCUIT 1.4 5.08 VIN = 6 VOLTS 5.07 5.06 5.05 VIN = 12 VOLTS 5.04 0 400 800 1200 1600 LOAD CURRENT – mA Figure 9. Load Regulation 2000 VSHUTDOWN = +2V 1.0 0.8 0.6 0.4 SLEEP MODE 0.2 5.03 5.02 35 ACTIVE MODE 1.2 SUPPLY CURRENT – mA 5.09 SUPPLY CURRENT – mA OUTPUT VOLTAGE – V 5.10 0 4 6 8 10 12 14 16 INPUT VOLTAGE – Volts 25 20 15 10 5 18 Figure 10. DC Supply Current –4– 30 20 0 4 6 8 10 12 14 16 INPUT VOLTAGE – Volts 18 20 Figure 11. Supply Current in Shutdown REV. 0 ADP1147-3.3/ADP1147-5 1.8 80 30 0°C 1.4 +25°C 1.2 1.0 +70°C 0.8 0.6 0.4 70 25 60 20 OFF-TIME – ms GATE CHARGE CURRENT – mA NORMALIZED FREQUENCY 1.6 Q N + QP = 100nC 15 10 2 4 6 8 (VIN – VOUT) – Volts 10 0 12 20 155 +3.3V 10 0 0.3 0.5 1 1.5 2 2.5 3 3.3 3.5 4 4.5 5 OUTPUT VOLTAGE – Volts 50 80 110 140 170 200 230 260 OPERATING FREQUENCY – kHz Figure 13. Gate Charge Supply Current Figure 12. Operating Frequency vs. (VIN–VOUT) 30 20 Q N + QP = 50nC 1 +5V 40 5 0.2 0 50 Figure 14. Off-Time vs. VOUT 95 3.35 100mA MAXIMUM THRESHOLD 3.34 145 140 OUTPUT VOLTAGE – V 90 EFFICIENCY – % SENSE VOLTAGE – mV 150 1 AMP 85 0.1 AMP 80 75 135 3.33 300mA 3.32 3.31 1 AMP 3.30 3.29 3.28 130 0 25 70 85 TEMPERATURE – 8C 100 Figure 15. Current Sense Threshold Voltage 70 5 8 11 14 17 INPUT VOLTAGE – Volts Figure 16. Efficiency vs. Input Voltage at VO = 3.3 V; Figure 1 Circuit with ADP1147-3.3 3.36 OUTPUT VOLTAGE – V 3.34 3.32 3.30 VIN = 6 VOLTS 3.28 3.26 3.24 VIN = 12 VOLTS 3.22 3.20 3.18 0 400 800 1200 1600 LOAD CURRENT – mA 2000 Figure 18. Load Regulation (VO = 3.3 V); Figure 1 Circuit with ADP1147-3.3 REV. 0 –5– 20 3.27 4 8 12 INPUT VOLTAGE – Volts 16 Figure 17. Output Voltage vs. Input Voltage (VO = 3.3 V); Figure 1 Circuit with ADP1147-3.3 ADP1147-3.3/ADP1147-5 VIN 4V–14V 3.3V 0V (a) Continuous Mode Operation D1 30BQ040 3.3V 0V ADP1147-3.3 (b) Power Saving Mode CT 620pF Figure 19. CT Waveforms L P-CHANNEL VIN CIN VIN P-DRIVE CT GND ITH SHUTDOWN L* 50mH 3300pF RC 1kV RSENSE SENSE(–) SENSE(+) 1nF VOUT D1 SHUTDOWN COUT RSENSE** 50mV 1mF GROUND PLANE ADP1147-3.3 CT 390pF 3300pF 1kV VIN P-DRIVE CT GROUND ITH SHUTDOWN SENSE(–) C IN 100mF 25V IRF7204 1mF *COILTRONICS CTX50-4 **KRL SL-1-C1-0R050J C OUT 220mF 6.3V X2 VOUT 3.3V/2A Figure 22. 3.3 V/2 A Regulator 100 SHUTDOWN 95 SENSE(+) VIN = 6 VOLTS 90 EFFICIENCY – % 1000pF Figure 20. Circuit Diagram Indicating the Recommended Ground Plane Scheme for PCB Layout VIN = 10 VOLTS 85 80 75 70 VIN 6V TO 14V 65 60 1 D1 1N4148 Q1 2N3906 R7 220V C8 1mF 1K 10K + Q2 2N2222 R6 470V C2-C4 220mF/16V OS-CON Q4 IRF7403 D3 1N4148 D2 30BQ040 C1 1mF + U1 ADP1147-5 R1 1kV C6 3.3nF 100 LOAD CURRENT – mA Figure 23. Efficiency vs. Load Current at VO = 3.3 V; Figure 22 Circuit R5 20kV C5 470pF 10 1 VIN P-DRV 8 2 CT GND 7 3 ITH SHD 6 4 SNS– SNS+ 5 C7 2.2nF L1 50mH Q3 VN2222LL R3 100V R4 100V R2 0.02V + C9–C11 220mF 3 10V OS-CON VOUT 5V/3A Figure 21. 5 V/3 A Regulator Using N-Channel Device –6– REV. 0 ADP1147-3.3/ADP1147-5 APPLICATIONS Determining the Output Current and the Value for R SENSE The ADP1147 family of regulators incorporate a current mode, constant off-time architecture to switch an external P-channel MOSFET. The external MOSFET can be switched at frequencies up to 250 kHz. The switching frequency of the device is determined by the value selected for capacitor CT. The value selected for RSENSE is determined by the required output current. The current comparator C has a threshold voltage range of 10 mV/RSENSE to 150 mV/RSENSE maximum. This threshold sets the peak current in the external inductor and yields a maximum output current of: A regulated output voltage is maintained by the feedback voltage at the SENSE(–) pin. The SENSE(–) pin is connected to an internal voltage divider. The voltage from this internal divider is fed to comparator V, and gain block G. It is then compared to an internal 1.25 volt reference. I MAX = I PEAK – I RIPPLE p − p 2 The resistance values for RSENSE can range from 20 mΩ to 200 mΩ. A graph for selecting RSENSE vs. the maximum output current is shown in Figure 3. The ADP1147 is capable of maintaining high levels of efficiency by automatically switching between the power saving and continuous modes. The internal R-S flip-flop #2 controls the device in the power saving mode, and gain block G assumes control when the device is in the continuous mode of operation. The value of RSENSE can be determined by using the following equation: RSENSE (in mΩ) = 100/IMAX This equation allows for a design margin due to component variations. During the P-MOSFET on time, the voltage developed across RSENSE is monitored by the SENSE(–) and SENSE(+) pins of the device. When this voltage reaches the threshold level of comparator C the output trips, switching the P drive to VIN, and turns the external P-MOSFET off. At this point capacitor CT begins to discharge at a rate that is determined by the off-time controller. The CT discharge current is proportional to the voltage measured at the SENSE(–) pin. When the voltage on cap CT decays to the threshold voltage (VTH1), comparator T switches and sets R-S flip-flop #1. This forces the P-drive output low, and turns on the P-MOSFET. The sequence is then repeated. As the load current is increased, the output voltage starts to drop. This causes the gain circuit to raise the threshold of the current comparator, and the load current is now tracked. The following equations are used to approximate the trip point for the power savings mode and the peak short circuit current. IPOWER SAVINGS ~ 5 mV/RSENSE + VO tOFF/2L ISC(PK) = 150 mV/RSENSE The ADP1147 automatically increases the tOFF time when a short circuit condition is encountered. This allows sufficient time for the inductor to decay between switching cycles. Due to the resulting inductor ripple current the average short circuit current ISC(AVG) is reduced to approximately IMAX. Determining the Operating Frequency and Selecting Values for CT and L When load currents are low, comparator B sets the R-S flip-flop #2 and asserts the power savings mode of operation. Comparator B monitors the voltage developed across RSENSE. As the load current decreases to 50% of the designed inductor ripple current, the voltage reverses polarity. This reversal causes comparator B to trip, setting the Q-bar output of R-S flip-flop #2 to a logic zero, and interrupts the cycle by cycle operation of the output. The output storage capacitors are then slowly discharged by the load. When the output cap voltage decays to the VOS level of comparator V, it resets flip-flop #2, and the normal cycle by cycle mode of operation resumes. If load currents are extremely small, the time it takes for flip-flop #2 to reset increases. During the extended wait for reset period, capacitor CT will discharge below the value of VTH2 causing comparator S to trip. This forces the internal sleep bar low and the device enters the sleep mode. A significant amount of the IC is disabled during the sleep mode, reducing the ground current from 1.6 mA to 160 µA, typical. In sleep mode the P-MOSFET is turned off until additional inductor current is required. The sleep mode is terminated when flip-flop #2 is reset. The ADP1147 incorporates a constant off-time architecture to switch an external P-MOSFET. The off-time (tOFF) is determined by the value of the external timing cap CT. When the P-MOSFET is turned on the voltage across CT is charged to approximately 3.3 volts. During the switch off-time the voltage on CT is discharged by a current that is proportional to the voltage level of VOUT. The voltage across CT is representative of the current in the inductor, which decays at a rate that is proportional to VOUT. Due to this relationship the value of the inductor must track the value selected for CT. Due to the constant off-time architecture, the input voltage has an effect on the device switching frequency. To limit the effects of this variation in frequency the discharge current is increased as the device approaches the dropout voltage of VIN +1.5 V. In the dropout mode the P-MOSFET is constantly turned on. The P-MOSFET gate charge losses increase with the operating frequency and results in lower efficiency (see the Efficiency section). REV. 0 The following equation is used to determine the desired continuous mode operating frequency: V OUT +V D V IN +V D CT = 1.3 ×10 4 × f 1− VD = the voltage drop across the Schottky diode. The graph in Figure 4 can be used to help determine the capacitance value of CT vs. the operating frequency and input voltage. –7– ADP1147-3.3/ADP1147-5 The formula used to calculate the continuous operating frequency is: 1− f = Using a ferrite cores in a design can produce very low core losses, allowing the designer to focus on minimizing copper loss and core saturation problems. Ferrite cores exhibit a condition known as “Hard Saturation,” which results in an abrupt collapse of the inductance when the peak design current is exceeded. This causes the inductor ripple current to rise sharply, the output ripple voltage to increase and the power savings mode of operation to be erroneously activated. To prevent this from occurring the core should never be allowed to saturate. V OUT +V D V IN +V D tOFF tOFF = 1.3 × 10 4 × CT × V REG V OUT VREG is the value of the desired output voltage. VOUT is the actual measured value of the output voltage. When in regulation VREG/VOUT is equal to 1. The switching frequency of the ADP1147 decreases as the input voltage decreases. The ADP1147 will reduce the tOFF time by increasing the discharge current in capacitor CT if the input to output voltage differential falls below 1.5 volts. This is to eliminate the possible occurrence of audible switching prior to dropout. Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for a toroids, but is more expensive than a ferrite core. A reasonable compromise between price and performance, from the same manufacturer is Kool Mu. Toroidal cores are extremely desirable where efficient use of available space and several layers of wire are required. They are available in various surface mount configurations from Coiltronics Inc. and other companies. Now that the operating frequency has been determined and the value selected for CT, the required inductance for inductor L can be computed. The inductor L should be chosen so it will generate no more than 25 mV/RSENSE of peak-to-peak inductor ripple current. Power MOSFET Selection and Considerations The ADP1147 requires the use of an external P-channel MOSFET. The major parameters to be considered when selecting the power MOSFET are the threshold voltage VGS(TH) and the on resistance of the device RDS(ON). The following equation is used to determine the required value for inductor L: The minimum input voltage determines if the design requires a logic level or a standard threshold MOSFET. In applications where the input voltage is > 8 volts, a standard threshold MOSFET with a VGS(TH) of < 4 volts can be used. In designs where VIN is < 8 volts, a logic level MOSFET with a VGS(TH) of < 2.5 volts is recommended. Note: If a logic level MOSFET is selected, the supply voltage to the ADP1147 must not exceed the absolute maximum for the VGS of the MOSFET (e.g., < ± 8 volts for IRF7304). 25 mV (V OUT +V D )× tOFF = or L MIN RSENSE L MIN = (V OUT +V D )× tOFF × RSENSE 25 mV The RDS(ON) requirement for the selected power MOSFET is determined by the maximum output current (IMAX). An assumption is made that when the ADP1147 is operating in the continuous mode, either the Schottky Diode or the MOSFET are always conducting the average load current. The following formulas are used to determine the duty cycle of each of the components. Substituting for tOFF above gives the minimum required inductor value of: LMIN = 5.1 × 105× RSENSE × CT × VREG The ESR requirements for the output storage capacitor can be relaxed by increasing the inductor value, but efficiency due to copper losses will be reduced. Conversely, the use of too low an inductance may allow the inductor current to become discontinuous, causing the device to enter the power savings mode prematurely. As a result of this the power savings threshold is lowered and the efficiency at lower current levels is severely reduced. P − Channel MOSFET Duty Cycle = Schottky Diode Duty Cycle = Inductor Core Considerations V OUT +V D V IN +V D V IN –V D V IN +V D Once the Duty Cycle is known, the RDS(ON) requirement for the Power MOSFET can be determined by: Now that the minimum inductance value for L has been determined, the inductor core selection can be made. High efficiency converters generally cannot afford the core losses found in low cost powdered iron cores. This forces the use of a more expensive ferrite, molypermalloy, or Kool Mu® cores. The typical efficiency in Figure 1 reflects the use of a molypermalloy core. The cost of the inductor can be cut in half by Using a Kool Mu core type CTX 50-4 by Coiltronics, but the efficiency will be approximately 1%–2% less. The actual core losses are not dependent on the size of the core, but on the amount of inductance. An increase in inductance will yield a decrease in the amount of core loss. Although this appears to be desirable, more inductance requires more turns of wire with added resistance and greater copper losses. RDS (ON ) = (V IN +V D )× P P (V OUT +V D )× I MAX 2 ×(1+ δ P ) where PP is the max allowable power dissipation and where δP is the temperature dependency of RDS(ON) for the MOSFET. Efficiency and thermal requirements will determine the value of PP, (refer to Efficiency section). MOSFETS usually specify the 1+ δ as a normalized RDS(ON ) vs. temperature trace, and δ can be approximated to 0.007/°C for most low voltage MOSFETs. Output Diode Considerations When selecting the output diode careful consideration should be given to peak current and average power dissipation so the maximum specifications for the diode are not exceeded. Kool Mu is a registered trademark of Magnetics, Inc. –8– REV. 0 ADP1147-3.3/ADP1147-5 Chemicon, Nichicon and Sprague are three manufacturers of high grade capacitors. Sprague offers a capacitor that uses an OS-CON semiconductor dielectric. This style capacitor provides the lowest amount of ESR for its size, but at a higher cost. Most capacitors that meet the ESR requirements for IP-P ripple will usually meet or exceed the rms current requirements. The specifications for the selected capacitor should be consulted. The Schottky diode is in conduction during the MOSFET offtime. A short circuit of VOUT = 0 is the most demanding situation on for the diode. During this time it must be capable of delivering ISC(PK) for duty cycles approaching 100%. The equation below is used to calculate the average current conducted by the diode under normal load conditions. I D1 = V IN –V OUT × I LOAD V IN +V D Surface mount applications may require the use of multiple capacitors in parallel to meet the ESR or rms current requirements. If dry tantalum capacitors are used it is critical that they be surge tested and recommended by the manufacturer for use in switching power supplies such as Type 593D from Sprague. AVX offers the TPS series of capacitors with various heights from 2 mm to 4 mm. The manufacturer should be consulted for the latest information, specifications and recommendations concerning specific capacitors. When operating with low supply voltages, a minimum output capacitance will be required to prevent the device from operating in a low frequency mode (see Figure 5). The output ripple also increases at low frequencies if COUT is too small. To guard against increased power dissipation due to undesired ringing, it is extremely important to adhere to the following: 1. Use proper grounding techniques. 2. Keep all track lengths as short as possible, especially connections made to the diode (refer to PCB Layout Considerations section). The allowable forward voltage drop of the diode is determined by the maximum short circuit current and power dissipation. The equation below is used to calculate VF: VF = PD/ISC(PK) Transient Response where PD is the maximum allowable power dissipation and is determined by the system efficiency and thermal requirements (refer to Efficiency Section). The response of the regulator loop can be verified by monitoring the transient load response. Several cycles may be required for a switching regulator circuit to respond to a step change in the dc load current (resistive load). When a step in the load current takes place a change in VOUT occurs. The amount of the change in VOUT is equal to the delta of ILOAD × ESR of COUT. The delta of ILOAD charges or discharges the output voltage on capacitor COUT. This continues until the regulator loop responds to the change in load and is able to restore VOUT to its original value. VOUT should be monitored during the step change in load for overshoot, undershoot or ringing, which may indicate a stability problem. The circuit shown in Figure 1 contains external components that should provide sufficient compensation for most applications. The most demanding form of a transient that can be placed on a switching regulator is the hot switching in of loads that contain bypass or other sources of capacitance greater than 1 µF. When a discharged capacitor is placed on the load it is effectively placed in parallel with the output cap COUT, and results in a rapid drop in the output voltage VOUT. Switching regulators are not capable of supplying enough instantaneous current to prevent this from occurring. Therefore, the inrush current to the load capacitors should be held below the current limit of the design. CIN Considerations During the continuous mode of operation the current drawn from the source is a square wave with a duty cycle equal to VOUT/VIN. To reduce or prevent large voltage transients an input capacitor with a low ESR value and capable of handling the maximum rms current should be selected. The formula below is used to determine the required maximum rms capacitor current: CIN IRMS = [VOUT (VIN–VOUT)]0.5 × IMAX/VIN The maximum for this formula is reached when VIN = 2 VOUT, where IRMS = IOUT/2. It is best to use this worst case scenario for design margin. Manufacturers of capacitors typically base the current ratings of their caps on a 2000-hour life. This requires a prudent designer to use capacitors that are derated or rated at a higher temperature. The use of multiple capacitors in parallel may also be used to meet design requirements. The capacitor manufacturer should be consulted for questions regarding specific capacitor selection. In addition, for high frequency decoupling a 0.1 µF to 1.0 µF ceramic capacitor should be placed and connected as close to the VIN pin as possible. Efficiency Efficiency is one of the most important reasons for choosing a switching regulator. The percentile efficiency of a regulator can be determined by dividing the output power of the device by the input power and then multiplying the results by 100. Efficiency losses can occur at any point in a circuit and it is important to analyze the individual losses to determine changes that would yield the most improvement. The efficiency of a circuit can be expressed as: COUT Considerations The minimum required ESR value is the primary consideration when selecting COUT. For proper circuit operation the ESR value of COUT must be less than two times the value selected for RSENSE (see equation below): COUT Minimum Required ESR < 2 RSENSE When selecting a capacitor for COUT, the minimum required ESR is the primary concern. Proper circuit operation mandates that the ESR value of COUT must be less than two times the value of RSENSE. % efficiency = 100% – (% L1 + % L2 + % L3 . . . etc.) L1, L2, L3, etc., are the individual losses as a percentage of the input power. In high efficiency circuits small errors result when expressing losses as a percentage of the output power. A capacitor with an ESR value equal to RSENSE will provide the best overall efficiency. If the ESR value of COUT increases to two times RSENSE a 1% decrease in efficiency results. United REV. 0 –9– ADP1147-3.3/ADP1147-5 ILOAD × % duty cycle × VDROP = Diode Loss Losses are encountered in all elements of the circuit, but the four major sources for the circuit shown in Figure 1 are: Figure 6 indicates the distribution of losses versus load current in a typical ADP1147 switching regulator circuit. With medium current loads the gate charge current is responsible for a substantial amount of efficiency loss. At lower loads the gate charge losses become large in comparison to the load, and result in unacceptable efficiency levels. When low load currents are encountered the ADP1147 employs a power savings mode to reduce the effects of the gate loss. In the power savings mode of operation the dc supply current is the major source of loss and becomes a greater percentage as the output current decreases. 1. The ADP1147 dc bias current. 2. The MOSFET gate charge current. 3. The I2 × R losses. 4. The voltage drop of the Schottky diode. 1. The ADP1147’s dc bias current is the amount of current that flows into VIN of the device minus the gate charge current. With VIN = 10 volts, the dc supply current to the device is typically 160 µA for a no load condition, and increases proportionally with load to a constant of 1.6 mA in the continuous mode of operation. Losses due to dc bias currents increase as the input voltage VIN is increased. At VIN = 10 volts the dc bias losses are usually less than 1% with a load current greater than 30 mA. When very low load currents are encountered the dc bias current becomes the primary point of loss. 2. The MOSFET gate charge current is due to the switching of the power MOSFET’s gate capacitance. As the MOSFET’s gate is switched from a low to a high and back to a low again, charge impulses dQ travel from VIN to ground. The current out of VIN is equal to dQ/dt and is usually much greater than the dc supply current. When the device is operating in the continuous mode the I gate charge is = f (QP). Typically a P-channel power MOSFET with an RDS on of 135 mΩ will have a gate charge of 40 nC. With a 100 kHz, switching frequency in the continuous mode, the I gate charge would equate to 4 mA or about a 2%–3% loss with a VIN of 10 volts. It should be noted that gate charge losses increase with switching frequency or input voltage. A design requiring the highest efficiency can be obtained by using more moderate switching frequencies. Losses at higher loads are primarily due to I2R and the Schottky diode. All other variables such as capacitor ESR dissipation, MOSFET switching, and inductor core losses typically contribute less than 2% additional loss. Circuit Design Example In using the design example below assumptions are as follows: VIN = 5 Volts VOUT = 3.3 Volts VDIODE drop (VD) = 0.4 Volts IMAX OUT = 1 Amp Max switching frequency (f) = 100 kHz. The values for RSENSE, CT and L can be calculated based on the above assumptions. RSENSE = 100 mV/1 Amp = 100 mΩ. tOFF time = (1/100 kHz) × [1 – (3.7/5.4)] = 3.15 µs. CT = 3.15 µs /(1.3 × 10 4) = 242 pF. L = 5.1 × 10 5 × 0.1 Ω × 242 pF × 3.3 V = 41 µH. If we further assume: 1. The data is specified at +25°C. 3. I2 × R loss is a result of the combined dc circuit resistance and the output load current. The primary contributors to circuit dc resistance are the MOSFET, the Inductor and RSENSE. In the continuous mode of operation the average output current is switched between the MOSFET and the Schottky diode and a continuous current flows through the inductor and RSENSE. Therefore the RDS(ON) of the MOSFET is multiplied by the on portion of the duty cycle. The result is then combined with the resistance of the Inductor and RSENSE. The following equations and example show how to approximate the I2 × R losses of a circuit. RDS(ON) × (Duty Cycle) + RINDUCTOR + RSENSE = R 2. MOSFET max power dissipation (PP) is limited to 250 mW. 3. MOSFET thermal resistance is 50°C/W. 4. The normalized RDS(ON) vs. temperature approximation (δP) is 0.007/°C. This results in 250 mW × 50°C per watt = 12.5°C of MOSFET heat rise. If the ambient temperature TA is 50°C, a junction temperature of 12.5°C +50°C, TA = 62.5°C. δP = 0.007 × (62.5°C –25°C) = 0.2625 We can now determine the required RDS(ON) for the MOSFET: RDS(ON) = 5(0.25)/3.3 (1)2 (1.2625) = 300 mΩ The above requirements can be met with the use of a P-channel IRF7204 or an Si9430. ILOAD2 × R = PLOSS VOUT × ILOAD = POUT When VOUT is short circuited the power dissipation of the Schottky diode is at worst case and the dissipation can rise greatly. The following equation can be used to determine the power dissipation: PLOSS/POUT × 100 = % I × RLOSS. 2 With the duty cycle = 0.5, RINDUCTOR = 0.15, RSENSE = 0.05 and ILOAD = 0.5 A. The result would be a 3% I2R loss. The effects of I2R losses causes the efficiency to fall off at higher output currents. PD = ISC(AVG) × VDIODE Drop 4. At high current loads the Schottky diode can be a substantial point of power loss. The diode efficiency is further reduced by the use of high input voltages. To calculate the diode loss, the load current should be multiplied by the duty cycle of the diode times the forward voltage drop of the diode. A 100 mΩ RSENSE resistor will yield an ISC(AVG) of 1 A. With a forward diode drop of 0.4 volts a 400 milliwatt diode power dissipation results. The rms current rating needed for CIN will be at least 0.5 A over the temperature range. –10– REV. 0 ADP1147-3.3/ADP1147-5 To obtain optimum efficiency the required ESR value of COUT is 100 mΩ or less. Printed Wire Board Layout Considerations The PWB layout is extremely critical for proper circuit operation and the items listed below should be carefully considered (see Figure 20) The circuit should also be evaluated with the minimum input voltage. This is done to assure that the power dissipation and junction temperature of the P-channel MOSFET are not exceeded. At lower input voltages the operating frequency of the ADP1147 decreases. This causes the P-channel MOSFET to remain in conduction for longer periods of time, resulting in more power dissipation in the MOSFET. 1. The signal and power grounds should be separate from each other. They should be tied together only at ground Pin 7 of the ADP1147. The power ground should be tied to the anode of the Schottky diode, and the (–) side of the CIN capacitor. The connections should be made with traces that are as wide and as short as possible. The signal ground should be connected to the (–) side of capacitor COUT using the same type of runs as above. The effects of VIN(MIN) can be evaluated if we assume the following: VIN(MIN) = 4.5 V VOUT = 3.3 V VD = 0.4 V fMIN = (1/3.15 µs) × (1– (3.7/4.9)) = 78 kHz. PD = 2. The sense(–) run to Pin 4 of the ADP1147 should be connected directly to the junction point of RSENSE and the + side of COUT. 3. The sense(–) and sense(+) traces should be routed together with minimum track spacing and run lengths. The 1000 pF filter capacitor across Pins 4 and 5 of the ADP1147 should be located as close to the device as possible. 3.3(0.125 Ω)(1 A)2 (1.2625 ) = 116 mW 4.5 Troubleshooting Hints 4. In order to supply sufficient ac current the (+) side of capacitor CIN should be connected with wide short traces and must be located as close to the source of the P-MOSFET as possible. Efficiency is the primary reason for choosing the ADP1147 for use in an application, and it is critical to determine that all portions of the circuit are functioning properly in all modes. After the design is complete the voltage waveforms on the timing capacitor, CT, at Pin 2 of the device, should be compared to the waveforms in Figures 19a and 19b. 5. In order to supply high frequency peak currents the input decoupling capacitors should range from 0.1 µF to 1.0 µF and must be located as close to the VIN pin and the ground Pin 7 as possible. In the continuous mode of operation the dc voltage level of the waveform on CT should never fall below the 2 V level and it should have a 0.9 V peak-to-peak sawtooth on it (see Figure 19a). 6. The shutdown Pin (6) is a high impedance input and it must not be allowed to float. The normal mode of operation of the device requires that this pin be pulled low. In the Power Savings Mode the sawtooth waveform on C T will decay to ground for extended periods of time (see Figure 19b). During the time that the capacitor voltage is at ground the ADP1147 is in the power savings or sleep mode and the quiescent current is reduced to 160 µA typical. The ripple current in the inductor should also be monitored to determine that it is approximately the same in both modes of operation. With a higher output currents the voltage level on C T should never decay to ground as this would indicate poor grounding and or decoupling. REV. 0 –11– ADP1147-3.3/ADP1147-5 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8 C3148–8–2/98 0.430 (10.92) 0.348 (8.84) 5 1 4 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 SEATING PLANE 5 1 4 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 0.0098 (0.25) 0.0040 (0.10) 8 –12– REV. 0