ETC XR2211ACD

XR-2211A
...the analog plus
FSK Demodulator/
Tone Decoder
company TM
June 1997–3
APPLICATIONS
FEATURES
Wide Frequency Range, 0.01Hz to 300kHz
Caller Identification Delivery
Wide Supply Voltage Range, 4.5V to 20V
FSK Demodulation
HCMOS/TTL/Logic Compatibility
Data Synchronization
FSK Demodulation, with Carrier Detection
Wide Dynamic Range, 10mV to 3V rms
Tone Decoding
Adjustable Tracking Range (+1% to 80%)
FM Detection
Excellent Temp. Stability, 100 ppm/°C, typ.
Carrier Detection
GENERAL DESCRIPTION
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211A is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
The XR-2211A is available in 14 pin packages specified
for commercial temperature ranges.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-2211ACP
14 Lead PDIP (0.300”)
0°C to +70°C
XR-2211ACD
14 Lead SOIC (Jedec, 0.150”)
0°C to +70°C
Rev. 1.04
1995
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017
1
XR-2211A
BLOCK DIAGRAM
VCC
GND
NC
1
4
9
Pre Amplifier
INP
TIM C1
2
Loop
-Det
14
Lock
Detect
Comparator
VCO
TIM C2
13
TIM R
12
Quad
-Det
11
LDO
3
LDF
6
LDOQ
5
LDOQN
7
DO
Internal
VREF
10
VREF
FSK Comp
Reference
COMP I
8
Figure 1. XR-2211A Block Diagram
Rev. 1.04
2
XR-2211A
PIN CONFIGURATION
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
INP
LDF
GND
LDOQN
LDOQ
DO
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
1
14
2
13
3
12
4
11
5
10
6
9
7
8
TIM C1
TIM C2
TIM R
LDO
VREF
NC
COMP I
14 Lead SOIC (Jedec, 0.150”)
14 Lead PDIP (0.300”)
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
VCC
2
INP
I
Receive Analog Input.
3
LDF
O
Lock Detect Filter.
Positive Power Supply.
4
GND
5
LDOQN
O
Ground Pin.
Lock Detect Output Not. This output will be low if the VCO is in the capture range.
6
LDOQ
O
Lock Detect Output. This output will be high if the VCO is in the capture range.
7
DO
O
Data Output. Decoded FSK output.
8
COMP I
I
FSK Comparator Input.
9
NC
10
VREF
O
Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
11
LDO
O
Loop Detect Output. This output provides the result of the quadrature phase detection.
12
TIM R
I
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13
TIM C2
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14
TIM C1
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
Not Connected.
Rev. 1.04
3
XR-2211A
PDC ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Max.
Unit
20
V
9
mA
R0 > 10KW. See Figure 4.
+3
%
Deviation from fO = 1/R0 C0
Temperature
+100
ppm/°C
Power Supply
0.25
%/V
VCC = 12 + 1V. See Figure 7.
0.2
%/V
VCC = + 5.0V. See Figure 7.
300
kHz
R0 = 8.2KW, C0 = 400pF
0.01
Hz
R0 = 2MW, C0 = 50mF
Parameter
Min.
Typ.
Conditions
General
Supply Voltage
4.5
Supply Current
5
Oscillator Section
Frequency Accuracy
Frequency Stability
Upper Frequency Limit
See Figure 8
Lowest Practical
Operating Frequency
Timing Resistor, R0 - See Figure 5
Operating Range
5
2000
KW
Recommended Range
5
100
KW
See Figure 7 and Figure 8.
+300
mA
Measured at Pin 11
Loop Phase Dectector Section
Peak Output Current
+100
Output Offset Current
Output Impedance
Maximum Swing
+4
+200
+2
mA
1
MW
+5
V
Quadrature Phase Detector
Measured at Pin 3
300
mA
Output Impedance
1
MW
Maximum Swing
11
VPP
20
KW
2
mV rms
Peak Output Current
Input Preampt Section
Input Impedance
Referenced to Pin 10
Measured at Pin 2
Input Signal
Voltage Required to
Cause Limiting
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 1.04
4
XR-2211A
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
2
MW
Measured at Pins 3 and 8
100
nA
70
dB
RL = 5.1KW
Voltage Comparator Section
Input Impedance
Input Bias Current
Voltage Gain
55
Output Voltage Low
300
500
mV
IC = 3mA
Output Leakage Current
0.01
10
mA
VO = 20V
5.3
5.85
V
Measured at Pin 10
AC Small Signal
Internal Reference
Voltage Level
4.75
Output Impedance
100
W
Maximum Source Current
80
mA
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above TA = 25°C . . . . . . . . .
JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above TA = 25°C . . . . . . . . . .
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW
800mW
6mW/°C
390mW
5mW/°C
SYSTEM DESCRIPTION
(internally connected). When in lock, these frequencies
are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz
when lock). By adding a capacitor to the phase detector
output, the 2 times fIN component is reduced, leaving a
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The main PLL within the XR-2211A is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(fO) set by a resistor (R0) to ground and its driving current
with a resistor (R1) from the phase detector.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
Rev. 1.04
5
XR-2211A
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20KW.
Recommended input signal level is in the range of 10mV
rms to 3V rms.
10 must be bypassed to ground with a 0.1mF capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 3). With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VREF. The peak to peak voltage swing
available at the phase detector output is equal to 2 x VREF.
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
connected to ground through a parallel combination of RD
and CD (see Figure 3) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used, pin 3
can be left open.
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R0,
connected from this terminal to ground. The VCO
free-running frequency, fO, is:
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type
output and requires a pull-up resistor, RL, to VCC for
proper operation. At “low” state, it can sink up to 5mA of
load current.
fO 1
Hz
R 0·C 0
where C0 is the timing capacitor across pins 13 and 14.
For optimum temperature stability, R0 must be in the
range of 10KW to 100KW (see Figure 9).
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or “on” state.
This terminal is a low impedance point, and is internally
biased at a DC level equal to VREF. The maximum timing
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to VCC for
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at “high” or “off”
state for low input frequency, and at “low” or “on” state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
capacitor, C0, connected across these terminals (see
Figure 6). C0 must be non-polar, and in the range of
200pF to 10mF.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with R0 at pin 12
(see Figure 10).
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
detector output (pin 11). This data filter is formed by RF
and CF (see Figure 3). The threshold voltage of the
comparator is set by the internal reference voltage, VREF,
available at pin 10.
VCO Free-Running Frequency, fO: XR-2211A does not
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3, and applying an
alternating bit pattern of O’s and 1’s at the known mark
and space frequencies. By adjusting R0, the VCO can
then be tuned to obtain a 50% duty cycle on the FSK
output (pin 7). This will ensure that the VCO fO value is
accurately referenced to the mark and space frequencies.
Reference Voltage, VREF (Pin 10): This pin is internally
biased at the reference voltage level, VREF: VREF = VCC /2
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
Rev. 1.04
6
XR-2211A
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Loop
Filter
φ Det
ÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎ
Data
Filter
FSK
Output
FSK
Comp
φ
VCO
Input
Preamp
φ
φ Det
Lock Detect
Filter
ÎÎ
ÎÎ
ÎÎÎ
ÎÎ
Lock Detect
Outputs
Lock Detect
Comp
Figure 2. Functional Block Diagram of a Tone and FSK Decoding System Using
XR-2211A
VCC
RB
Loop
Phase
Detect
RF
C1
VCO
Rl
8
7
CF
R1
2
Input
Signal
11
FSK
Comp.
10
12
Internal
Reference
0.1mF
0.1mF
14
13
R0
6
C0
LDOQ
Quad
Phase
Detect
LDOQN
3
RD
Lock
Detect
Comp.
CD
Figure 3. Generalized Circuit Connection for
FSK and Tone Detection
Rev. 1.04
7
5
XR-2211A
DESIGN EQUATIONS
(All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified)
(See Figure 3 for definition of components)
1. VCO Center Frequency, fO:
fO +
1
R 0·C 0
2. Internal Reference Voltage, VREF (measured at pin 10):
V REF +
ǒV2 Ǔ–650mV in volts
CC
3. Loop Low-Pass Filter Time Constant, t:
+ C 1·R PP (seconds)
where:
R PP +
ǒRR)·RR Ǔ
1
F
1
F
if RF is or CF reactance is , then RPP = R1
4. Loop Damping, j:
+
Ǹǒ
1250·C 0
R 1·C 1
Ǔ
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking
f
bandwidth, "+ f
0
f + R 0
R1
f0
Tracking
Bandwidth
Df
fLL
f1
Df
fO
f2
fLH
Rev. 1.04
8
XR-2211A
6. FSK Data filter time constant, tF:
tF +
RB · RF
·C (seconds)
( R B ) R F) F
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of
phase error at phase detector input):
Kd +
ƪ
ƫ
V REF · R 1 volt
10, 000·p radian
Note: For derivation/explanation of this equation, please see TAN-011.
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
K0 +
–2p
+
V REF ·C 0 · R 1
ńsecond
ǒradianvolt
Ǔ
9. The filter transfer function:
F(s) +
1
at 0 Hz.
1 ) SR 1·C 1
10. Total loop gain. KT:
K T + K O·K d·F(s) +
S = Jw and w = 0
1
ƫ
ǒ5, 000·C R·(R ) R )Ǔƪseconds
F
0
1
F
11. Peak detector current IA:
IA +
V REF
(V REF in volts and I A in amps)
20, 000
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 1.04
9
XR-2211A
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10, the functions
of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for
the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10 can be tailored for any FSK decoding application by the choice of five key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1, these parameters can be calculated as
follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Calculate PLL center frequency, fO:
f O + ǸF 1·F 2
b) Choose value of timing resistor R0, to be in the range of 10KW to 100KW. This choice is arbitrary. The recommended
value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX.
RO + RO )
RX
2
c) Calculate value of C0 from design equation (1) or from Figure 7:
CO +
1
R0 · f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R1 +
R 0·f 0
·2
(f 1–f 2)
e) Calculate C1 to set loop damping. (See design equation 4):
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R1 · 2
Rev. 1.04
10
XR-2211A
f)
The input to the XR-2211A may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211A from such noisy line conditions by the use of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
V IN minimum (peak) + V a–V b + V " 2.8mV offset + V REF
ǒ
V
20, 000
or R X + 20, 000 REF –1
(20, 000 ) R X)
V
Ǔ
VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
VCC
Input
ÎÎ
ÎÎ
To Phase
Detector
Va
Vb
2
Rx
20K
20K
ÎÎ
ÎÎ
VREF 10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
R sum +
CF +
(R F ) R 1)·R B
( R 1 ) R F ) R B)
0.25
(R sum·Baud Rate)
Baud rate in
1
seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 1.04
11
XR-2211A
1.0
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
R0=5KW
15
R0=10KW
R0=5KΩ
C0( mF)
Supply vs. Current (mA)
20
10
0.1
R0=10KΩ
R0=20KW
R0=40KW
5
R0=80KW
R0>100K
R0=160KW
0
4
6
8 10
12 14 16
Supply Voltage,
0.01
100
18 20 22 24
V+ (Volts)
Figure 5. Typical Supply Current vs. V+
(Logic Outputs Open Circuited)
1000
fO(HZ)
10000
Figure 6. VCO Frequency vs. Timing Resistor
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
1,000
C0=0.001mF
Normalized Frequency
1.02
R0(KW )
C0=0.0033mF
100
C0=0.01mF
C0=0.1mF
C0=0.0331mF
C0=0.33mF
10
0
1000
fO = 1kHz
RF = 10R0
5
1.01
4
4
2
0.98
1
0.97
4
6
8
10
fO(Hz)
Normalized Frequency Drift (% of f O )
12
14
Figure 8. Typical fO vs. Power Supply
Characteristics
+1.0
1MΩ
R0=10K
+0.5
500K
R0=50K
50K
R0=500K
10K
V+ = 12V
R1 = 10 R0
fO = 1 kHz
R0=1MΩ
-1.0
-50
-25
R0
Curve
1
5K
2
10K
3
30K
4
100K
300K
5
16 18
20 22
V+ (Volts)
-0.5
0
25
50
75
100
125
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 1.04
12
3
3
0.99
Figure 7. VCO Frequency vs. Timing Capacitor
5
2
1.00
10000
0
1
24
XR-2211A
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.
Step 1: Calculate fO: from design instructions
(a) f O + Ǹ1200·2200 =1624
Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instructions (b))
ǒ Ǔ
(b) R T + 10 ) 10 + 15K
2
Step 3: Calculate C0 from design instructions
(c) C O +
1
+ 39nF
15000·1624
Step 4: Calculate R1 : from design instructions
(d) R 1 + 20000·1624·2 + 51, 000
(2200–1200)
Step 5: Calculate C1 : from design instructions
(e) C 1 + 1250·39nF2 + 3.9nF
51000·0.5
Step 6: Calculate RF : RF should be at least five times R1, RF = 51,000⋅5 = 255 KW
Step 7: Calculate RB : RB should be at least five times RF, RB = 255,000⋅5 = 1.2 MW
Step 8: Calculate RSUM :
R SUM +
(R F ) R 1)·R B
+ 240K
(R F ) R 1 ) R B )
Step 9: Calculate CF :
CF +
0.25
+ 1nF
ǒ R SUM·Baud Rate Ǔ
Note: All values except R0 can be rounded to nearest standard value.
Rev. 1.04
13
XR-2211A
VCC
RB
11
Loop
Phase
Detect
R1
35.2K
1%
0.1µF
12
VCO
0.1µF
5%
1nF
C1
2.7nF
5%
2
Input
Signal
RF 178K
27nF
CO
1.8m
RL
5.1K
5%
5%
7
CF
10%
Data
Output
FSK
Comp.
10
Internal
Reference
R0
20K
1%
13
14
8
5%
Rx
20K
VCO
Fine
Tune
6
LDOQ
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)
VCC
RB
11
Loop
Phase
Detect
2
Input
Signal
0.1µF
RF
C1
14
CF
R1
12
VCO
8
10
0.1µF
13
7
RL
5.1k
FSK
Comp.
Internal
Reference
R0
C0
Rx
6 LDOQ
Quad
Phase
Detect
3
RD
CD
Lock
Detect
Comp.
5 LDOQN
Between 400K and 600K
Figure 11. External Connectors for FSK Demodulation with Carrier
Detect Capability
Rev. 1.04
14
XR-2211A
VCC
Loop
Phase
Detect
C1
220pF
5%
VCO
14
FSK
Comp.
R1
200K
10
1%
0.1µF
Internal
Reference
R0
20K
1%
13
C0
50nF 5%
Tone
Input
7
+
12
2
0.1µF
8
11
VCC
VCO
Fine
Tune
Rx
5K
6 LDOQ
+
Quad
Phase
Detect
RL2
5.1K
RL3
5.1K
Logic Output
5 LDOQN
3
CD
80nF
RD
470K
Lock
Detect
Comp.
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
The lock detect section of XR-2211A can be used as a
carrier detect option for FSK decoding.
The
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
frequency approaches the capture bandwidth.
Excessively large values of CD will slow the response time
of the lock detect output. For Caller I.D. applications
choose CD = 0.1mF.
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “low” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
CD is inversely proportional to the capture range, +Dfc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications, Dfc
> Df/2. For RD = 470KW, the approximate minimum value
of CD can be determined by:
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
C D § 16 C in F and f in Hz.
f
With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
follows: R0 and C0 set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter time
constant and the loop damping factor.
C in mF and f in Hz.
With values of CD that are too small, chatter can be
observed on the lock detect output as an incoming signal
Rev. 1.04
15
XR-2211A
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
CO +
1
R 0·fs
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f 0·2
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
1250·C 0
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D § 16
Df
C in mF
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
C0 +
1 +
1
+ 50nF
20, 000·1, 000
R 0·f S
Rev. 1.04
16
XR-2211A
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0·f O·2
20, 000·1, 000·2
+
+ 400K
100
f
Note: The total detection bandwidth covers the frequency range of fO +f
d) Calculate value of C0 for a given loop damping factor:
Normally, j = 0.5 is recommended.
C1 +
–9
1250·C 0
+ 1250·50·10 2 + 6.25pF
400, 000·0.5
R 1· 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D + 16 w 16 w 80nF
200
f
Increasing CD slows down the logic output response time.
f)
Fine tune center frequency with 5KW potentiometer, RX.
VCC
VCC
RF
0.1µF
100K
Loop
Phase
Detect
2
0.1µF
FM
Input
3
8
11
C1
12
VCO
14
13
R1
10
0.1µF
7
CF
FSK
Comp
.
Internal
Reference
4
1
2
11
LM324
R0
6
C0
LDOQ
Quad
Phase
Detect
LDOQN
Lock
Detect
Comp.
5
Figure 13. Linear FM Detector Using XR-2211A and an External Op Amp.
(See Section on Design Equation for Component Values.)
Rev. 1.04
17
Demodulated
Output
XR-2211A
Linear FM Detection
The FM detector gain, i.e., the output voltage change per
unit of FM deviation can be given as:
XR-2211A can be used as a linear FM detector for a wide
range of analog communications and telemetry
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
output is taken from the loop phase detector output (pin
11), through a post-detection filter made up of RF and CF,
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin
11. Normally, a non-inverting unity gain op amp can be
used as a buffer amplifier, as shown in Figure 13.
V OUT R 1·V REF
100·R 0
where VR is the internal reference voltage (VREF = VCC /2
- 650mV). For the choice of external components R1, R0,
CD, C1 and CF, see the section on design equations.
V+
1
REF
Voltage
Output
20K
Input
2
10
Lock
Detect
Filter
B
10K
10K
From
VCO
B’
3
6
Lock Detect
Outputs
20K
5
Internal Voltage
Reference
2K
Input Preamplifier
and Limiter
Lock Detect
Comparator
Quadrature
Phase Detector
2K
8
A
Timing
Capacitor
A’
13 C0 14
B’
B
11
A
From
VCO
A’
FSK
Comparator
Loop
Input
Detector
Output
7
FSK
Data
Output
4
12
R0 Timing
Resistor
8K
Ground
Voltage Controlled
Oscillator
Loop Phase Detector
Figure 14. Equivalent Schematic Diagram
Rev. 1.04
18
FSK Comparator
XR-2211A
14 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
14
8
1
7
E1
E
D
Seating
Plane
A2
A
L
α
A1
B
INCHES
SYMBOL
eA
eB
B1
e
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.145
0.210
3.68
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.725
0.795
18.42
20.19
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.04
19
C
XR-2211A
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
14
8
E
H
1
7
C
A
Seating
Plane
α
e
B
A1
L
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.337
0.344
8.55
8.75
E
0.150
0.157
3.80
4.00
e
0.050 BSC
MAX
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
α
0°
8°
0°
Note: The control dimension is the millimeter column
Rev. 1.04
20
8°
XR-2211A
Notes
Rev. 1.04
21
XR-2211A
Notes
Rev. 1.04
22
XR-2211A
Notes
Rev. 1.04
23
XR-2211A
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1995 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.04
24