ETC RC2211

Electronics
Semiconductor Division
RC2211
FSK Demodulator/Tone Decoder
Features
Applications
¥
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¥
¥
¥
¥
¥
¥
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Wide frequency range Ð 0.01 Hz to 300 kHz
Wide supply voltage range Ð 4.5V to 20V
DTL/TTL/ECL logic compatibility
FSK demodulation with carrier-detector
Wide dynamic range Ð 2 mV to 3 VRMS
Adjustable tracking range Ð ±1% to ±80%
Excellent temperature stability Ð 20 ppm/°C typical
FSK demodulation
Data synchronization
Tone decoding
FM detection
Carrier detection
Description
The RC2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications. It is
particularly well-suited for FSK modem applications, and
operates over a wide frequency range of 0.01 Hz to 300 kHz.
It can accommodate analog signals between 2 mV and 3V,
and can interface with conventional DTL, TTL and ECL
logic families. The circuit consists of a basic PLL for
tracking an input signal frequency within the passband, a
quadrature phase detector which provides carrier detection,
and an FSK voltage comparator which provides FSK
demodulation. External components are used to independently set carrier frequency, bandwidth and output delay.
Block Diagram
Loop Filter
Data Filter
FSK
Data
Output
f-Detector
FSK
Comparator
f
FSK
Input
VCO
f
Preamp
Lock
Detector
Outputs
f-Detector
Lock
Detector
Filter
Lock
Detector
Comparator
65-2211-01
Rev. 1.0.1
This document was created with FrameMaker 4 0 4
PRODUCT SPECIFICATION
RC2211
Description of Circuit Controls
FSK Data Output (Pin 7)
This output is an open collector stage which requires a
pull-up resistor, RL, to +VS for proper operation. It can sink
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a ÒhighÓ or off state for low input
frequency, and will switch to a ÒlowÓ or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
Signal Input (Pin 2)
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 kW. Recommended input signal
level is in the range of 10 mVRMS to 3 VRMS.
Quadrature Phase Detector Output, Q (Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
of RD and CD (see Figure 1) to eliminate chatter at the lock
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
FSK Comparator Input (Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Þlter is
connected between this terminal and the PLL phase detector
output (pin 11). This data Þlter is formed by RF and CF of
Figure 1. The threshold voltage of the comparator is set by
the internal reference voltage, VR, available at pin 10.
Lock Detector Output, Q (Pin 5)
Reference Bypass (Pin 9)
The output at pin 5 is at a ÒhighÓ state when the PLL is out of
lock and goes to a ÒlowÓ or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
resistor, RL, to +VS for proper operation. In the ÒlowÓ state it
can sink up to 5 mA of load current.
This pin can have an optional 0.1, mF capacitor connected to
the ground.
Reference Voltage, VR (Pin 10)
This pin is internally biased at the reference voltage level,
VR; VR = +VS/2 Ð 650 mV. The DC voltage level at this pin
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF
capacitor.
Lock Detector Complement, Q (Pin 6)
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
ÒonÓ state.
RB
510K
Loop
f-Detector
RF
100K
(11)
+VS
(8)
R1
CF
FSK
Output
FSK
Comparator
f
(2)
(12)
(10)
VCO
0.1 µF
(1)
(7)
C1
Input
Preamp
RL
Internal
Reference
f
(14)
Input
Signal
C0
(13)
R0
(6)
Lock
Detector
Outputs
Quad
f-Detector
(3)
RD
100K
to 470K
Q
0.1 µF
CD
Lock
Detector
Comparator
(5)
Q
65-2211-02
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
2
RC2211
Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop
phase detector. The PLL loop Þlter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to VR. The peak voltage swing available at
the phase detector output is equal to ±VR.
VCO Control Input (Pin 12)
PRODUCT SPECIFICATION
2.
æ +V S ö
V R = è ---------- ø -650 mV
2
3.
Loop Lowpass Filter Time Constant, t
t = R1C1
4.
VCO free running frequency is determined by external
timing resistor, R0, connected from this terminal to ground.
The VCO free running frequency, F0 is given by:
1
F 0 ( Hz ) = ------------R0 C0
Internal Reference Voltage, VR (measured at pin 10)
Loop Dampening, z:
æ C0 ö 1
z = ç ------ ÷ æè --- öø
è C1 ø 4
5.
Loop Tracking Bandwidth, ±DF/F0:
Df/FO = R0/R1
where C0 is the timing capacitor across pins 13 and 14. For
optimum temperature stability R0 must be in the range of
10 kW to 100 kW (see Typical Performance Characteristics).
Tracking
Bandwidth
Df
This terminal is a low impedance point, and is internally
biased at a DC level equal to VR. The maximum timing current drawn from pin 12 must be limited to £3 mA for proper
operation of the circuit.
FLL
F1
Df
F0
F2
FLH
65-2211-03
VCO Timing Capacitor (Pins 13 and 14)
VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals. C0 must
be non-polarized, and in the range of 200 pF to 10 mF.
6.
tF = RFCF
7.
VCO Frequency Adjustment
VCO can be Þne tuned by connecting a potentiometer, Rx, in
series with R0 at pin 12 (see Figure 2).
Design Equations
Loop Phase Detector Conversion Gain, Kf (Kf is the
differential DC voltage across pins 10 and 11, per unit
of phase error at phase-detector input):
( Ð2) ( VR)
kf ( in volts per radian ) = ---------------------------p
VCO Free-Running Frequency, F0
The RC2211 does not have a separate VCO output terminal.
Instead, the VCO outputs are internally connected to the
phase detector sections of the circuit. However, for set-up or
adjustment purposes, the VCO freerunning frequency can be
measured at pin 3 (with CD disconnected) with no input and
with pin 2 shorted to pin 10.
FSK Data Filter Time Constant, tF:
8.
VCO Conversion Gain, K0 is the amount of change in
VCO frequency per unit of DC voltage change at pin 11:
Ð1
K0 ( in Hertz per volt ) = --------------------C0 R1 VR
9.
Total Loop Gain, KT:
KT (in radians per second per volt)= 2 pKfK0
See Figure 1 for DeÞnitions of Components.
=
1.
VCO Center Frequency, F0:
1
F 0 ( Hz ) = ------------R0 C0
4
------------C0 R1
10. Peak Phase Detector Current, IA:
VR
I A ( mA ) = ------25
3
PRODUCT SPECIFICATION
RC2211
Pin Assignments
+VS
1
14
Timing Capacitor
Input
2
13
Timing Capacitor
Lock Detector Filter
3
12
Timing Resistor
GND
4
11
Loop f-Detector
Q
5
10
Reference Voltage Output
Q
6
9
Reference Bypass
FSK Data Output
7
8
FSK Comparator Input
65-2211-04
Absolute Maximum Ratings
Parameter
Min
Max
Unit
-20
+20
V
3
VRMS
-65
+150
°C
RM2211D
-55
+125
°C
RV2211N
-25
+85
°C
RC2211N
-0
+70
°C
PDIP
+125
°C
CerDIP
+175
°C
+300
°C
PDIP
468
mW
CerDIP
1042
mW
Supply Voltage
Input Signal Level
Storage Temperature Range
Operating Temperature Range
Junction Temperature
Lead Soldering Temperature (60 sec.)
Max. PD TA<50°C
Thermal Characteristics
Parameter
14 Lead Plastic DIP
14 Lead Ceramic DIP
Therm. Res qJC
—
60°C/W
Therm. Res. qJA
160°C/W
120°C/W
6.5 mW/°C
8.33 mW/°C
For TA > 50°C Derate at
4
RC2211
PRODUCT SPECIFICATION
Electrical Characteristics
(Test Conditions +VS = +12V, TA +25°C, R0 = 30 kW, C0 = 0.033 mF. See Figure 1 for component designations.)
RV/RM2211
Parameters
Test Conditlons
Min
Typ
RC2211
Max
Min
20
4.5
Typ
Max
Units
General
Supply Voltage2
4.5
Supply Current
20
V
11
mA
R0 ³ 10 kW
4.0
9.0
5.0
Deviation from f0 = 1/R0C0
±1.0
±3.0
±1.0
%
Oscillator
Frequency Accuracy
1
Frequency Stability
Temperature Coefficient
R1 = ¥
±20
±50
±20
ppm/°C
Power Supply Rejection
+VS = 12 ±1V
+VS = 5 ±0.5V
0.05
0.2
0.5
0.05
%/V
%/V
300
kHz
0.01
Hz
Upper Frequency Limit
R0 = 8.2 kW, C0 = 400 pF
Lowest Practical Operating
Frequency1
R0 = 2 MW, C0 = 50 mF
100
0.2
300
0.01
Timing Resistor, R0
Operating Range
5.0
2000
5.0
2000
kW
Recommended Range
15
100
15
100
kW
Loop Phase Detector
±150 ±200 ±300
±100 ±200 ±300
mA
Output Offset Current
±1.0
±2.0
mA
Output Impedance
1.0
1.0
MW
±5.0
V
Peak Output Current
Maximum Swing
Measured at pin 11
Ref. to pin 10
±4.0
±5.0
Measured at pin 3
100
±4.0
Quadrature Phase Detector
Peak Output Current3
150
150
mA
Output Impedance
1.0
1.0
MW
Maximum Swing
11
11
VP-P
20
20
kW
2.0
mVRMS
2.0
2.0
MW
100
100
nA
70
dB
Input Preamp
Input Impedance
Measured at pin 2
Input Signal Voltage
Required to Cause Limiting3
2.0
10
Voltage Comparator
Input Impedance
Measured at pins 3 & 8
Input Bias Current
1
Voltage Gain
RL = 5.1 kW
55
70
55
Output Voltage Low
IC = 3mA
300
300
mV
Output Leakage Current
V0 = 12V
0.01
0.01
mA
Internal Reference
Voltage Level
Measured at pin 10
4.9
Output Impedance
5.3
100
5.7
4.75
5.3
100
5.85
V
W
Notes:
1. Guaranteed by design.
2. Individual applications may need special circuitry to function at <12V.
3. Sample tested.
5
PRODUCT SPECIFICATION
RC2211
Applications
1.
Calculate PLL center frequency, F0
F1 + F2
fF 0 = ----------------2
FSK Decoding
Figure 2 shows the basic circuit connection for FSK decoding. With reference to Figures 1 and 2, the functions of
external components are deÞned as follows: R0 and C0 set
the PLL center frequency, R1 sets the system bandwidth, and
C1 sets the loop Þlter time constant and the loop damping
factor. CF and RF form a one pole post-detection Þlter for the
FSK data output. The resistor RB (510 kW) from pin 7 to pin
8 introduces positive feedback across FSK comparator to
facilitate rapid transition between output logic states.
Recommended component values for some of the most
commonly used FSK bauds are given in Table 1.
2.
Choose a value of timing resistor R0 to be in the range
of 10 kW to 100 kW. This choice is arbitrary. The recommended value is R0 = 20 kW. The Þnal value of R0 ios
normally Þnetuned with the series potentiometer, RX.
3.
Calculate value of C0 from Design Equation No. 1 or
from Typical Performance Characteristics:
C0 = 1/R0F0
4.
+VS
Calculate R1 to give a Df equal to the markspace
deviation:
R1 = R0 [F0/(F1 - F2)]
0.1 µF
5.
C0
FSK
Input
+VS
0.1 µF
RL
5.1K
FSK Data
Output
1
14
2
13
3
12
4
5
VCO
Fine Tune
11 0.1 µF
10
6
9
7
8
RB
510K
RX
5K
R1
C1
RF
100K
65-2211-05
CF
Figure 2. Circuit Connectbn for FSK Decoding
Table 1. Recommended Component Values
for Commonly Used FSK Bands
(see Circuit of Figure 2)
FSK Band
Normally, z » 1/2 is recommended
Then: C1 = C0/4 for z = 1/2
R0
RC2211
Component Values
Calculate C1 to set loop damping. (See Design Equation
No. 4)
6.
Calculate Data Filter Capacitance, CF:
For RF = 100 kW, RB = 510 kW, the recommended value
of CF is:
3
C F ( in mF ) = ------------------------Baud Rate
Note: All calculated component values except RO can be
rounded off to the nearest standard value, and R0 can
be varied to fine-tune center frequency through a series
potentiometer, RX (see Figure 2).
Design Example
75 Baud FSK demodulator with mark space frequencies of
1110/1170 Hz:
300 Baud
C0 = 0.039 mF, CF = 0.005 mF
F1 = 1070 Hz
C1 = 0.01 mF, R0 = 18 kW
F2 = 1270 Hz
R1 = 100 kW
300 Baud
C0 = 0.022 mF, CF = 0.005 mF
F1 = 2025 Hz
C1 = 0.0047 mF, R0 = 18 kW
F2 = 2225 Hz
R1 = 200 kW
1200 Baud
C0 = 0.027 mF, CF = 0.0022 mF
Step 3: Calculate C0 from VCO Frequency vs. Timing
Capacitor: C9 = 0.044mF
F1 = 1200 Hz
C1 = 0.01 mF, R0 = 18 kW
Step 4: Calculate R1: R1 = R0 (1140/60) = 380 kW
F2 = 2200 Hz
R1 = 30 kW
Step 1: Calculate F0:
F0=(1110+1170)(1/2)= 1140Hz
Step 2: Choose R0 = 20 kW (18 kW Þxed resistor in series
with 5 kW potentiometer)
Step 5: Calculate C1: C1 = C0/4 = 0.011 mF
Design Instructions
The circuit of Figure 2 can be tailored for any FSK decoding
application by the choice of Þve key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space
frequencies, F1 and F2, these parameters can be calculated as
follows:
6
Note: All values except R0 can be rounded off to nearest
standard value.
RC2211
PRODUCT SPECIFICATION
FSK Decoding with Carrier Detector
+VS
The lock detector section of the RC2211 can be used as a
carrier detector option for FSK decoding. The recommended
circuit connection for this application is shown in Figure 3.
The open-collector lock detector output, pin 6, is shorted to
the data output (pin 7). Thus, the data output will be disabled
at ÒlowÓ state, until there is a carrier within the detection
band of the PLL, and the pin 6 output goes ÒhighÓ to enable
the data output.
0.1 µF
C0
FSK
Inputs
CO
0.1 µF
470K
+VS
0.1 µF
C0
FSK
Inputs
CO
0.1 µF
470K
14
2
13
3
12
4
5
+VS
5.1K
11 0.1 µF
7
8
Data
Output
13
3
12
4
11
RC2211
R0
RX
5K
R1
0.1 µF
10
6
9
7
8
C1
+VS
RL2
Q
Q
Logic
Outputs
65-2211-07
Figure 4. Circuit Connection for Tone Detection
RX
5K
R1
C1
RF
100K
510K
2
VCO
Fine Tune
R0
10
9
RL1
Logic
Output
VCO
Fine Tune
RC2211
6
14
5
+VS
1
1
CF
65-2211-06
Note: Data output is "low" when no carrier is present.
Figure 3. External Connections for
FSK Demodulation with Carrier Detector Capability
The minimum value of the lock detector Þlter capacitance
CD is inversely proportional to the capture range, ±DfC.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications,
DFC< DF/2. For RD = 470 kW, the approximate minimum
value of CD can be determined by:
CD(mF) ³ 16/capture range in Hz
With values of CD that are too small, chatter can be observed
on the lock detector output as an incoming signal frequency
approaches the capture bandwidth. Excessively large values
of CD will slow the response time of the lock detector
output.
Both logic outputs at pins 5 and 6 are open-collector type
stages, and require external pull-up resistors RL1 and RL2 as
shown in Figure 4.
With reference to Figures 1 and 4, the function of the
external circuit components can be explained as follows:
R0 and C0 set VCO center frequency, R1 sets the detection
bandwidth, C1 sets the lowpass-loop Þlter time constant and
the loop dampening factor, and RL1 and RL2 are the respective pull-up resistors for the Q and Q logic outputs.
Design Instructions
The circuit of Figure 4 can be optimized for any tone-detection application by the choice of Þve key circuit components:
R0, R1, C0, C1 and CD. For a given input tone frequency, FS,
these parameters are calculated as follows:
1.
Choose R0 to be in the range of 15 kW to 100 kW.
This choice is arbitrary.
2.
Calculate C0 to set center frequency, f0 equal to
FS: C0 = 1/R0FS.
3.
Calculate R1 to set bandwidth ±DF (see Design Equation No. 5): R1 = R0(F0/DF). Note: The total detection
bandwidth covers the frequency range of F0 ± DF.
4.
Calculate value of C1 for a given loop damping factor:
Tone Detection
C1 =C0/16z2
Figure 4 shows the generalized circuit connection for tone
detection. The logic outputs, Q and Q at pins 5 and 6 are
normally at ÒhighÓ and ÒlowÓ logic states, respectively.
When a tone is present within the detection band of the PLL,
the logic state at these outputs becomes reversed to the
duration of the input tone. Each logic output can sink 5 mA
of load current.
Normally z = 1/2 is optimum for most tone detector
applications, giving C1 = 0.25 C0.
Increasing C1 improves the out-of-band signal rejection,
but increases the PLL capture time.
5.
Calculate value of Þlter capacitor CD. To avoid chatter
at the logic output, with RD = 470W, CD must be:
CD(mF) ³ (16/capture range in Hz)
Increasing CD slows the logic output response time.
7
PRODUCT SPECIFICATION
Design Examples
Tone detector with a detection band of 1 kHz ±20 Hz:
Step 1: Choose R0 = 20 kW (18 kW in series with 5 kW
potentiometer) .
Step 2: Choose C0 for F0 = 1 kHz: C0 = 0.05 mF.
Step 3: Calculate R1: R1 = (R0) (1000/20) = 1 MW.
Step 4: Calculate C1: for z = 1/2, C1 = 0.25 mF,
C0 = 0.013 mF.
Step 5: Calculate CD: CD = 16/38 = 0.42 mF.
RC2211
Linear FM Detection
The RC2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry applications.
The recommended circuit connection for the application is
shown in Figure 5. The demodulated output is taken from the
loop phase detector output (pin 11), through a post detection
Þlter made up of RF and CF, and an external buffer ampliÞer.
This buffer ampliÞer is necessary because of the high
impedance output at pin 11. Normally, a non-inverting unity
gain op amp can be used as a buffer ampliÞer, as shown in
Figure 5.
The FM detector gain, i.e., the output voltage change per unit
of FM deviation, can be given as:
Step 6: Fine tune the center frequency with the 5 kW
potentiometer. RX.
VOUT = R1 VR/100 R0 Volts/% deviation
where VR is the internal reference voltage. For the choice of
external components R1, R0, C0, C1 and CF, see the section
on Design Instructions.
FM
Input
0.1 µF (2)
(8)
0.1 µF
(1)
+VS
(10)
(13)
0.1 µF
RC2211
CO
CK
(14)
(4)
(12)
(11)
R0
R1
C1
RF
100K
CF
+VS
Demodulated
Ouput
65-2211-08
Figure 5. Linear FM Detector
Using RC2211 and an External Op Amp
8
RC2211
PRODUCT SPECIFICATION
Typical Performance Characteristics
10
20
R0 = 5 kWŸ
R0 = 10 kWŸ
R0 = 20 kWŸ
R0 = 40 kWŸ
R0 = 80 kWŸ
R0 = 160 kW
15
R0 > 100 kW
4
6
8
10
12 14 16
18
20 22
1.0
65-2211-10
5
0.1
24
100
FO (Hz)
Figure 6. Supply Current vs. Supply Voltage
(Logic Outputs Open Circuited)
Figure 7. Timing Resistor with Timing
Capacitor vs. VCO Frequency
1.0
10
0
0.5
500 kW
0
50 kW
-0.5
-1.0
-50
10
1
1 MW
R0 = 10 kWŸ
ŸR = 50 kWŸ
0
Ÿ
10 kW
R0 = 1 MWŸ
ŸR = 500 kWŸ
0
Ÿ
0
-25
FO (Hz)
+25
+50
+75
+100
+125
Temperature (¡C)
Figure 8. Timing Capacitor with Timing
Resistor vs. VCO Frequency
Figure 9. Center Frequency Drift vs. Temperature
Normalized Frequency
1.02
1.01
Curve
1
2
3
4
5
1.00
0.99
FO = 1 kHz
R 10 R0
0.98
0.97
4
6
8
10
12
14
16
18
20
22
R0
5K
10K
30K
100K
300K
65-2211-13
100
65-2211-11
C
0=
0.0
01
C
0=
µF
0.0
0
C
33
0=
µF
0.0
1µ
C
0
F
=0
C
0=
.03
0
3
.1
C
µF
µF
0=
0.3
3µ
F
Normalized Center
Frequency Drift (% of FO)
1K
R0 (kW)
10K
1K
+VS (V)
65-2211-12
0
C0 (µF)
R0 = 10 kW
10
65-2211-09
IS (mA)
R0 = 5 kW
24
-VS (V)
Figure 10. VCO Frequency vs. Supply Voltage
9
10
(4)
GND
+VS
(1)
Q17
Q18
Q109
(14)
B
Q103
(12)
R0
R37
Timing Resistor
8K
Q92
(13)
B
Q95 C0 Timing
Capacitor
Q97
D108
Voltage Controlled Oscillator
D89
A
R18
2K
D96
D101
A
R19
2K
A
From
VCO
A
D72
D57
B
From
VCO
B
Q60
Q68 Q62
Input Pramplifier and Limitter
D56
R11
18K
Q47 Q48
R12
18K
Reference
Voltage Input
(2)
Output
Intenal Voltage Reference
R3
20K
Q4
R2
20K
Q61
Q65
D111
D67
Q64
Q71
Loop Phase Detector
D73
Q80
Q83 Q84
D86
D87
(11)
Q68
Loop
f-Detector
Output
Q74
(8)
Q25
Q27
Q20
FSK Comparator
D24
Q38
Q42
(6)
Lock
Detector
Outputs
(5)
65-2211-14
FSK
Data
Output
(7)
Lock Detector Comparator
Q83 Q84
Q23
FSK
Comparator
Input
Q88
Lock
Detector
Q86 Filter
(3)
Q85
Quadature Phase Detector
Q79
Q81 Q82
D85
PRODUCT SPECIFICATION
RC2211
Schematic Diagram
RC2211
PRODUCT SPECIFICATION
Notes:
11
PRODUCT SPECIFICATION
Notes:
12
RC2211
RC2211
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
RC2211
Mechanical Dimensions
14-Lead Ceramic DIP Package
Inches
Symbol
Min.
A
b1
b2
c1
D
E
e
eA
L
Q
s1
a
Millimeters
Max.
—
.200
.014
.023
.045
.065
.008
.015
—
.785
.220
.310
.100 BSC
.300 BSC
.125
.200
.015
.060
.005
—
90¡
105¡
Min.
Notes:
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
19.94
5.59
7.87
2.54 BSC
7.62 BSC
3.18
5.08
.38
1.52
.13
—
90¡
105¡
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
8
2
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 7, 8 and 14 only.
8
4
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4
5, 9
7
4. This dimension allows for off-center lid, meniscus and glass overrun.
3
6
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 14.
6. Applies to all four corners (leads number 1, 7, 8, and 14).
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
8. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
9. Twelve spaces.
D
7
1
8
14
NOTE 1
E
s1
eA
e
A
Q
L
b2
14
b1
a
c1
RC2211
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Inches
Symbol
Min.
A
A1
A2
B
B1
C
D
D1
E
E1
e
eB
Millimeters
Max.
—
.210
.015
—
.115
.195
.014
.022
.045
.070
.008
.015
.725
.795
.005
—
.300
.325
.240
.280
.100 BSC
—
.430
.115
.200
14
L
N
Min.
Notes:
Notes
Max.
—
5.33
.38
—
2.93
4.95
.36
.56
1.14
1.78
.20
.38
18.42
20.19
.13
—
7.62
8.26
6.10
7.11
2.54 BSC
—
10.92
2.92
5.08
14
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
4
2
2
5
D
7
1
8
14
E1
D1
E
e
A
A1
C
L
B1
B
eB
15
PRODUCT SPECIFICATION
RC2211
Ordering Information
Part Number
Package
Operating Temperature Range
RC2211N
N
0°C to +70°C
RV2211N
N
-25°C to +85°C
RM2211D
D
-55°C to +125°C
RM2211D/883B
D
-55°C to +125°C
Notes:
/883B suffix denotes MIL-STD-883, Par 1.2.1 Compliant Devices
N = 14-Lead Plastic DIP
D = 14-Lead Ceramic DIP
The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the
terms and conditions of any subsequent sale. RaytheonÕs liability shall be determined solely by its standard terms and conditions of sale.
No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied.
Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors.
LIFE SUPPORT POLICY:
RaytheonÕs products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably
be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and
indemniÞes Raytheon Company against all damages
Raytheon Electronics
Semiconductor Division
350 Ellis Street
Mountain View CA 94043
415 968 9211
FAX 415 966 7742
12/95 0.0m
Stock#DS20002211
Ó Raytheon Company 1995