THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MA9000 Series MAY 1995 DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal CMOS/SOS gate arrays is a four transistor ‘cell-unit’ equivalent in size to a 2 input NAND gate. Back to back cellunits as illustrated, organised in rows, form the core of the array The interconnection patterns that cause groups of cell units within a row, to become defined logic cells, and the models which are used to simulate these cells, are stored as software in LIBRARIES. Cells up to the complexity of, say, multiple bit shift registers are treated in this way. Higher complexity functions are described by MACROS as the interconnection of defined cells. Macros are ‘hard’, ‘soft’, or ‘firm’ according to the constraints that are applied to the distribution of the component cells within the array and whether the full function is simulated by a model or by the additive effects of the component cells. FEATURES ■ ■ ■ ■ ■ Radiation Hard to 1MRad(Si) High SEU Immunity, Latch-Up Free Double-Level-Metal CMOS/SOS Technology 2.5 Micron Design Rules Typical Gate Delay 1.2nS With 2 Loads, 60MHz Toggle Speeds ■ Comprehensive Library of Logic Cells and Logic Function Building Macros ■ 100% Automatic Place and Route for Typically 70% Utilisation Figure 1: Cell Unit ARRAY OPTIONS Array Type Cell Units MA9007 MA9024 MA9040 748 2484 4048 I/O 46 80 102 Bonding Pads Power Total 2 4 4 48 84 106 Each cell-unit is equivalent to a 2 input NAND gate. Any l/O site may be configured as a power pad to give flexible bonding options, but to standardise testing, preferred positions exist. 1 MA9000 Series CHARACTERISITICS & RATINGS Symbol Parameter Min. Max. Units VDD VI TA TS Supply voltage Input voltage Operating temperature Storage temperature -0.5 -0.3 -55 -65 7 VDD + 0.3 125 150 V V ˚C ˚C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification. is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1: Absolute Maximum Ratings Symbol Parameter VDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 IL IOZ IDD Supply voltage TTL input high voltage TTL input low voltage CMOS input high voltage CMOS input low voltage TTL output high voltage TTL output low voltage CMOS output high voltage CMOS output low voltage Input leakage current Output leakage current Power supply current Conditions Min. Typ. Max. Units IOH = -2mA IOL = 5mA IOH = -4mA IOL = 4mA Tristate Output - 4.5 2.0 80 2.4 90 - 5.0 0.1 5.5 0.8 20 0.4 10 10 30 * V V V %VDD %VDD V V %VDD %VDD µA µA mA VDD = 5V ±10%, over full operating temperature. * Dependent on array type. Table 2: Electrical Characteristics AC CHARACTERISTICS Cell Name Function O/P Edge Inherent Delay Per 1pF Load* Units NOP Push/Pull Output Buffer 2 Input NOR RDT Reset D Type 0.5 0.3 1.6 0.8 4.6 7.8 7.1 4.4 0.4 0.2 13.6 5.0 13.7 13.6 - ns NOR2 Rising Falling Rising Falling Rising CK - QB Falling CK - QB Data Set-up time Data Hold time * 1pF is equivalent to fanout of 5 standard gates Table 3: Electrical Characteristics 2 ns ns MA9000 Series PROPAGATION DELAY Propagation Delay Factor Propagation Delay Factor Worst case maximum propagation delays for 5 volts working and 25°C are stated in the cell libraries. These are for the data change or state change which gives the greatest delay. Typical process figures under the same conditions are generally 60% of those listed. Use the following normalised graphs to obtain converstion factors to predict delays at any other working temperature or voltage: PACKAGE OPTIONS MA9007 196 x 129 DIL14 DIL16 DIL20 DIL24 DIL28 DIL40 DIL48 DIL64 X X X X X X LCC28 LCC40 LCC44 LCC48 LCC68 LCC84 X X X FPK16 FPK20 FPK24 FPK28 FPK64 FPK68 FPK84 X X X X PGA68 PGA84 PGA120 PGA144 MA9024 247 x 240 MA9040 301 x 302 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X DIL = Dual in line LCC = Leadless chip carrier FPK = Leaded flatpack PGA = Pin grid array These are standard packages. If your package requirement is not shown above, discuss other options with an applications engineer. Figure 2: Propogation Delay vs Temperature & Propogation Delay vs Supply Voltage 3 MA9000 Series RADIATION TOLERANCE For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GPS can provide radiation testing compliant with MIL-STD883C remote sensing method 1019 notice 5. Total Dose (Function to specification)* 3x105 Rad(Si) Transient Upset (Stored data loss) 5x1010 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification) >1x1015 n/cm2 Single Event Upset** <1x10-10 Errors/bit day Latch Up Not possible * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Table 4: Radiation Hardness Parameters CELL LIBRARY QUICK GUIDE Cell Name Function Cell Units COMBINATIONAL GATES INV DUALINV INVB INVC BUFF BUFFB BUFFC NAND2 NAND2B NAND3 NAND4 NAND8 NAND12 NAND16 AND2 AND3 AND4 NOR2 NOR2B NOR3 NOR4 NOR8 4 Inverter Dual inverter Fast inverter Super fast inverter Non-inverting buffer Fast non-inverting buffer Super fast non-inverting buffer 2 input NAND Fast 2 input NAND 3 input NAND 4 input NAND 8 input NAND 12 input NAND 16 input NAND 2 input AND 3 input AND 4 input AND 2 input NOR Fast 2 input NOR 3 input NOR 4 input NOR 8 input NOR 1 1 1 2 1 2 3 1 2 2 2 6 8 11 2 2 3 1 2 2 2 6 Cell Name NOR12 NOR16 OR2 OR3 OR4 ANDNOR ANDOR ORNAND ORAND A2N01 A201 02NA1 02A1 EXNOR EXORN SEL21NV SEL2 SEL41NV SEL4 Function 12 input NOR 16 input NOR 2 input OR 3 input OR 4 Input OR 2 + 2 input AND/NOR 2 + 2 input AND/OR 2 + 2 OR/NAND 2 + 2 OR/AND 2 + 1 Input AND/NOR 2 + 1 input AND/OR 2 + 1 input OR/NAND 2 + 1 input OR/AND Exclusive NOR Exclusive OR Select 1 of 2 (inverting) Select 1 of 2 4 bit data selector (inverting) 4 bit data selector Cell Units 8 11 2 2 3 2 3 2 3 2 2 2 2 3 3 3 3 6 7 MA9000 Series Cell Name Function Cell Units DECODERS DEC2T4 DEC3T8 DEC4T16 Cell Name 2 to 4 line decoder 3 to 8 line decoder 4 to 16 line decider 6 11 40 Half adder Full adder Fast look ahead adder 2 bit look ahead unit 3 bit look ahead unit 4 bit look ahead unit 4 bit look ahead adder 8 bit look ahead adder 5 8 6 10 14 24 50 106 SHRx RSHRx DREGx DREGTx HPLSx SIMPLE LATCHES NASR NOSR NAND set reset-latch NOR set-reset latch D-latch (Active low) D-latch(Actlve high) Set D-latch Reset D-latch Set/reset D-latch 3 3 4 4 4 4 5 EDGE TRIGGERED LATCHES RETS SRETS Latch with reset Latch with reset and set Multibit (x = 2-8) serial register 16-46 Multibit (x = 2-8) serial reg. with reset 18-54 Multibit parallel register (x = 2-8) 8-22 Multibit parallel register (x = 2-8) 12-36 with tri-state outputs Half parallel loading shift registers 22-64 (x = 2-8) INVERTING TRI-STATE BUFFERS TRIBUFF TRIBUFFL TRINV TRINVL Tristate buffer (enable high) Tristate buffer (enable low) Tristate inv buffer (enable high) Tristate inv. buffer (enable low) 2 2 2 2 INPUT OUTPUT AND PERIPHERAL CELLS TRANSPARENT LATCHES DL DLH SDL RDL SRDL Cell Units REGISTERS / SHIFT REGISTERS ARITHMETIC HAD FAD FLAD LAH2 LAH3 LAH4 ADD4 ADD8 Function 7 8 DIP PUP PDO TSCHMITT CSCHMITT CMOSIN TTLIN NOP WNOP BOP ZOP ODN ODP TRIOP BUSINT STEPUP Direct input (protection cicuit only) Pull up (approx 30 Kohms) Pull down (approx 40 Kohms) TTL compatible Schmitt 6 CMOS compatible Schmitt 6 CMOS buffer (non-inverting) 1 TTL buffer (non-inverting) 3 Push/pull output buffer (inverting) Multiple NOP Push/pull output buffer (non inverting) Tri-state output buffer Open drain output pull down Open drain output pull up Tristate I/O buffer 4 Bus interface 6 Output Buffer 6 MASTER-SLAVE FLIP-FLOPS POWER SUPPLY PADS DT D2T SDT RDT SRDT JK SDK RJK SRJK D-type Dual input D-type Set D-type Reset D-type Set/reset D-type JK flip-flop JK flip-flopwith set JK flip-flop with reset JK flip-flop with reset and set 6 8 7 7 8 10 11 11 12 VDD VSS VDD pad VSS pad TOGGLE FLIP-FLOPS STT RTT SRTT Set T-type Reset T-type Set/reset T-type 7 7 8 SYNCHRONOUS COUNTER SYNC Synchronous counter stage 10 5 MA9000 Series MACROS The following Macros are included in the MA9000 library. GPS are constantly adding new Macros to the library, please contact our nearest office for information on the latest additions. Macro name Macro name ACOUNTn ALU4 GCOUNTn JCOUNTn LADDn MCOMPn PARlTYn RADDn SEL8 SEL16 M2901 M2909 M2902 M2910 M2918 Asynchronous counters ALU Gray counters Johnson counters Lookahead adders Magnitude comparators Parity detectors Ripple carry adders Select 1 of 8 Select 1 of 16 4 bit slice microprocessor 4 bit microprogram controller Look ahead carry unit 12 bit microprogram sequencer Pipeline register INPUT BY CUSTOMER PERFORMED BY GPS Circuit Capture Circuit Simulation Layout Post Layout Simulation Verification Checks PG Mask Manufacture Fabrication Test DEVELOPMENT INTERFACES Circuit design, captive and simulation activities are carried out by the customer. Schematic capture and simulation libraries for Dazix and Mentor Graphics CAE systems are provided by GPS. GPS will accept a simulated design and perform layout, verification checks and PG. GPS will then procure masks and fabricate and test parts prior to prototype delivery. The MA9000 arrays fall within the ESA capability domain. DAZIX is a trademark of Intergraph UK Mentor Graphics is a trademark of Mentor Graphics Corporation. 6 Protoype Delivery Figure 3: Development Interfaces MA9000 Series ORDERING INFORMATION For details of Reliability, QA/QCI, Test, and Assembly options, see 'Manufacturing Capability and Quality Assurance Standards'. Base Type 07 MA9007 24 MA9024 40 MA9040 Unique Circuit Designator 3Sx24nnnxxxxx Radiation Tolerance S R Q H Radiation hard processing 100 kRads (Si) guaranteed 300 kRads (Si) guaranteed 1000 kRads (Si) guaranteed QA/QCI Process Test Process Package Type Assembly Process C F L N Ceramic DIL (solder seal) Flatpack (solder seal) Leadless Chip Carrier Naked Die Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S HEADQUARTERS OPERATIONS CUSTOMER SERVICE CENTRES GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire, SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 • GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55 • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 • JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 • NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 • SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 • SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 • TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 • UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1995 Publication No. DS3598-3.4 May 1995 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM. This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. 7