Features • • • • • • • • 4 Multiplier-Accumulators 40 Bits Accuracy 16 Bit Data and Coefficients 4-tap Filter With 27 MHz Sample Rate Programmable to Give up to 256 Taps With Sampling Reducing Proportionally to 421,875 kHz Programmable Rounding and Truncation to 16 Bit 8 Bit Standard Microprocessor Interface 64-pin PQFP, 68-pin PGA68 or 68-pin LCC68 Packaging Description The AT76C001 Programmable Finite Impulse Response (FIR) Filter implements a 4th order FIR cell built around 4 multiplier-accumulators. It contains a dual-port RAM and a RAM which are used to implement FIR filters of up to 256 taps. High order filters are achieved by multiplexing the 4th order cell and accumulating the intermediate results up to 40 bits, so that there is no loss of accuracy. The maximum frequency of the AT76C001 is 27 MHz. For 4-tap FIR filter, the incoming sample rate can be as high as 27 MHz. For higher order FIR filters, the sample rate can be as high as the circuit frequency divided by the 4th order cell multiplexing factor. CBIC Programmable FIR Filter AT76C001 A programmable normalization block allows the choice of the 16 significant bits from the 40 bit internal result which can be previously rounded by adding 0.5 LSB according to the 16 significant bit locations. The AT76C001 has a microprocessor interface which can be configured to be Intel or Motorola compatible. Applications • • • Digital Filters (video, audio, etc.) Correlation Image Processing AT76C001 Pin Description Pin Number Name Type Function QFP64 Packaging LCC68 Packaging PGA68 Packaging IN<15:0> 34-40, 42, 44-51 27-33, 35, 37-44 K10-11, J10-11, H1011, G10, F10, E10-11, D10-11, C10-11, B11-10 I Input sample DIV 33 26 L10 I Input sample valid. Active low RST_X1 32 24 K9 I Force input sample to 0. Useful for interpolation implementation OUT<15:0> 18-12, 10, 8-1 9-3, 1, 67-60 K1, J1-2, H1-2, G1-2, F2, E2, D1-2, C1-2, B12, A2 O Output filtered sample DOV 19 10 K2 O Output filtered sample valid. Active low I/O Microprocessor interface data bus. Used for accessing internal registers and to write the coefficients of the filter DATA<7:0> 21-24, 26, 28-30 13-16, 18, 20-22 L3, K4, L4, K5-7, L7, K8 CS 52 46 B9 I Chip select. Active low DS/WR 53 47 A9 I Microprocessor interface data strobe (Motorola mode) or Write signal (Intel mode). Active low RDWR/RD 54 48 B8 I Microprocessor interface Read/Write signal (Motorola mode) or Read signal (Intel mode). Active low ADD<1:0> 63-64 57-58 A4, B3 I Microprocessor interface address bus RESET 31 23 L8 I Circuit master reset. Active low CLOCK I For internal use. Connect to ground VCC Power supply (+5V) GND 9, 25, 41, 55, 57, 17, 34, 49, 51, 53 59 A6-8, E1, G11, L5 Ground A3, A10, L2, L9 No connection 50 49 48 47 46 45 44 43 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VCC 42 41 40 39 38 37 36 35 34 33 DIV 51 IN0 11, 25, 45, 59 52 CS RST-XI 32 53 DS/WR RESET 31 54 RDWR/RD DATA0 30 55 GND DATA1 29 56 CLOCK DATA2 28 57 GND VCC 27 58 VCC DATA3 26 59 GND GND 25 60 VCC DATA4 24 61 CLOCK_BIST(0) DATA5 23 62 VCC DATA6 22 63 ADD1 ADD 0 21 OUT7 GND OUT8 VCC OUT9 OUT10 6 7 8 9 10 11 12 13 DATA7 TEST_ BIST (0) 14 15 16 17 18 19 DOV OUT6 5 OUT15 OUT5 4 OUT14 OUT4 3 OUT13 OUT3 2 OUT11 OUT2 1 OUT12 OUT1 64 AT76C001 QFP64 OUT0 NC IN15 K3 IN14 12 IN13 20 11, 27, 43, 58, 60, 2, 19, 36, 52, 54, B4-6, F1, F11, L6 62 56 IN12 TEST_BIST IN11 Circuit clock (27 MHz max) For internal use. Connect to ground IN9 I I IN10 B7 A5 IN8 50 55 GND 56 CLOCK_BIST 61 (0): Connect to GND Plan View of AT76C001 in QFP64 Package 2 AT76C001 20 17 16 15 14 13 12 DATA3 GND DATA4 DATA5 DATA6 DATA7 TEST_BIST(0) 11 10 DOV 18 NC* 19 VCC 31 20 DATA2 IN12 21 DATA1 IN13 30 22 DATA0 29 23 RESET IN14 24 NC* IN15 28 25 RST_XI 27 26 DIV AT76C001 OUT15 9 OUT14 8 O UT13 7 O UT12 6 IN11 O UT11 5 32 IN10 O UT10 4 33 IN9 O U T9 3 34 GND VC C 2 35 IN8 O UT 8 1 36 VCC GND 68 37 IN7 O U T7 67 38 IN6 O U T6 66 39 IN5 OU T5 65 AT76C001 LCC68 53 54 55 56 57 58 59 OUT0 52 NC* 51 ADD0 50 VCC 49 ADD1 48 CLOCK_BIST(0) 47 VCC 46 VCC IN0 44 45 (0): Connect to GND GND IN1 GND 62 43 OUT2 OUT1 CLOCK IN2 GND 63 42 RDWR/RD 64 OUT3 DS/WR O UT 4 NC* IN4 IN3 CS 40 41 61 60 * No Connection 9 10 11 NC* DIV Plan view of AT76C001 in LCC68 package 1 2 L NC* K OUT15 DOV 3 4 DATA7 DATA5 TC(0) 5 6 GND VCC 7 8 DATA1 RESET DATA6 DATA4 DATA3 DATA2 DATA0 RST_XI IN15 IN14 J OUT14 OUT13 IN13 IN12 H OUT12 OUT11 IN11 IN10 G OUT10 IN9 GND IN8 VCC OUT9 AT76C001 PGA68 F VCC OUT8 E GND OUT7 IN7 IN6 D OUT6 OUT5 IN5 IN4 C OUT4 OUT3 IN3 IN2 B OUT2 OUT1 ADD0 VCC VCC VCC CLOCK RDWR/ RD CS IN0 IN1 OUT0 NC* ADD1 CB(0) GND GND GND DS/WR NC* A (0): Connect to GND * No Connection Plan view of AT76C001 in PGA68 package 3 Block Diagram DOV Internal Control Signals D AT A < 7 :0> Register Register C ontrol U nit Coefficient RAM OU T <15:0> Register Sam ple RAM Multiplexer IN<15:0> Register Fourth Order FIR Cell Normalisation ADD<1:0> CS D S/ W R R DW R /R D RST -XI DI V CL OC K RESET Fourth Order FIR Cell Fro m D ATA< 7 :0 > Fro m IN<1 5 :0 > Fro m Control U ni t Mu x Mul t Register Mu x Mul t Register Mu x Mul t Register Mu x Mul t Register Add Add Add Add Register Register Register Register To Normalisation 4 AT76C001 AT76C001 Functional Description The AT76C001 has an architecture built around a 4-tap non-recursive filter cell. This allows a 4-tap filter to be implemented, e.g. y(n) = a(0)x(n) + a(1)x(n-1) + a(2)x(n-2) + a(3)x(n-3) where x = 16 bit incoming sample y = 16 bit filtered sample If (N+3)/4 is greater than P, then some coefficients of the last sub-filter will be set to zero automatically by the circuit. In single mode, the incoming sample rate can be as high as the circuit frequency (27 MHz). A new incoming sample is notified by a low level on DIV input signal and clocked by the rising edge of the circuit clock CLOCK. If there is a low level set on DIV and then a low level is set on RST_XI input, then a ‘zero’ sample is fed internally into the circuit. a = 16 bit coefficient This operating mode is called ‘single mode’. The AT76C001 can implement up to 256-tap filters by multiplexing the 4th order structure, using internal RAMs. Nth order FIR filters can be divided into P 4th-order FIR sub-filters where P is the integer part of (N+3)/4. Thus the complete filter is evaluated by accumulating the contributions of each elementary 4th order sub-filter: y(n) = y(n,0) + y(n,1) + ....... + y(n,P-1) where y(n,j) = a(4j)x(n-4j) + a(4j+1)x(n-4j-1) + a(4j+2)x(n-4j-2) + a(4j+3)x(n-4j-3) j = number of the sub-filter This operating mode is called ‘sequential mode’. For each new sample, a filtered sample is calculated. Valid output filtered samples are notified by a low level on DOV output signal. The timing diagram below illustrates the single mode operation. In sequential mode, an N-tap filter is divided into P 4-tap filters. Consequently, the incoming sample rate must be at least P times slower than the circuit rate. As in single mode, a new incoming sample is notified by a low level on DIV input signal and clocked by the rising edge CLOCK. But here, DIV defines a temporal window where XIN is valid and whose width must be at least one CLOCK period and at most P-1 clock periods. The timing diagrams below illustrate the case for an N-tap filter, where N is greater than 4 but less than 9, i.e., DIV must go to high level between two incoming signals. Timing Diagram for Single Mode Operation CLOCK Input valid DIV Input forced to 0 RST_XI IN OUT DOV X0 X1 X2=0 X3=0 X4 Y0 Y1 X5 Y2 Y3 Y4 X7=0 X6 Y5 X8 Y6 Output valid 5 Microprocessor Interface Internal Registers The AT76C001 has an 8 bit configurable microprocessor interface comprising the following signals: The AT76C001 contains three internal registers accessible in Read and Write via the microprocessor interface, as soon as it is configured and locked. They are: DATA <7:0> AD– <1:0> CS DS/WR RDWR/RD 8 bit data bus 2 bit address bus Chip Select Data Strobe or Write signal Read/Write signal or Read signal Configuration register (CFGR) Normalization and Rounding Register (NORR) Filter Order Register (FILR) Configuration Register By setting bit 1 of the configuration interface (INTEL/ MOTO), it is possible to configure the microprocessor interface to be Motorola or Intel compatible. When chosen, the configuration must be locked by setting bit LOCK_CFG of the configuration register. This must be done first of all otherwise the circuit will not function properly. Configuration Motorola Mode Intel Mode Intel/Moto bit Bit set to 0 Bit set to 1 Signals DATA<7:0> DATA<7:0> ADD<1:0> ADD<1:0> CS CS DS WR RD/WR RD It is an 8 bit register mapped at address 1hex = 01bin Bit 0 = START/STOP Activates/deactivates filtering Bit 1 = INTEL/MOTO Configures microprocessor interface to be Intel or Motorola. Bit 2 = MSB/LSB Indicates if 16 bit coefficients are written with Most Significant Byte or Least Significant Byte ahead. Bit 3 = LOCK_CFG Locks the microprocessor interface configuration. Bit 4 = SING/SEQ Indicates the operating mode of the 4th order cell, i.e. Single Mode or Sequential Mode. Bit 5 = BUFF_FULL Indicates that the sample input buffer contains N samples when implementing an N-tap FIR filter. (continued) Timing Diagram for N-tap Filter where 4<N<9 CLOCK DIV RS T_ XI IN OUT X0 X1 X2 = 0 Y0 DO V 6 AT76C001 Y1 X3 X4 = 0 Y2 X5 = 0 Y3 Y4 AT76C001 Internal Registers (Continued) Bit 6 = LAST_SFILT Indicates that the last sub-filter is accessed. Bit 7 = END_INCOEFF Indicates that the last coefficient of the last sub-filter is being accessed. Bit No 7 6 Bit Name END_IN COEFF Acc. Mode Reset Value 5 Reset Values 7 6 5 4 3 2 1 0 MSB/LSB START/ STOP Bit Name FILT7 FILT6 FILT5 FILT4 FILT3 FILT2 FILT1 FILT0 R/W R/W R/W Acc. Mode R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 Reset Value 0 0 0 0 0 0 0 0 3 2 1 LAST_S BUFF_ FILT FULL SING/ SEQ CFG LOCK INT/ MOTO R R R R R/W 1 0 1 0 0 0 Coefficient Writing Normalization and Rounding Register The normalization and rounding register is a 5 bit register mapped at address 2h = 10b allows the selection of the 16 bit significant part of the internal 40 bit result; also defines the number of bits rounding value if rounding is desired. Selects the 16 bit part and defines the number of bits rounding value as illustrated in the following table: Bit 3:0 OUT<15:0> Rounding Value (Hex) 0000 RES<31:16> 00 0000 8000 0001 RES<32:17> 00 0001 0000 0010 RES<33:18> 00 0002 0000 0011 RES<34:19> 00 0004 0000 0100 RES<35:20> 00 0008 0000 0101 RES<36:21> 00 0010 0000 0110 RES<37:22> 00 0020 0000 0111 RES<38:23> 00 0040 0000 1XXX RES<39:24> 00 0080 0000 Bit 4 = ROUNDEN The filter order register is an 8 bit register mapped at address 3h=11b. It contains the number of the order of the filter to be implemented minus 1. Bit No 4 Bit <3:0>= SEL <3:0> Filter Order Register Filter coefficients are stored internally by writing to address 0hex = 00bin. The bit MSB/LSB of the configuration register indicates if the MSB is sent before the LSB and vice versa. Stored coefficients are not readable via the microprocessor interface. For an N-tap filter, 2xN writing is necessary. If N is not a multiple of 4, the remaining coefficients of the last sub-filter are set automatically to zero. Application Examples A 4-Tap FIR Filter in Motorola Mode Example with coefficient MSB ahead and rounding enabled. yn = c0xn + c1xn-1 + c2xn-2 + c3xn-3 Enables/disables rounding of the 40 bit result before normalization. Bit No 4 3 2 1 0 Bit Name ROUNDEN SEL3 SEL2 SEL1 SEL0 Access Mode R/W R/W R/W R/W R/W Reset Value 0 0 0 0 0 Where yn is the output filtered sample, c is the coefficient and x is the incoming samples. 1. Firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a Master reset). 2. Write 1100bin in the configuration register. This sets the configuration with bit 0 selecting stop mode, bit 1 selecting Motorola mode, bit 2 selecting MSB ahead, and bit 3 locks the configuration. 3. Write the Filter Order-1 in the FILT_ORD register, i.e. 03hex. 4. Write the 4 coefficients starting with the Most Significant Byte of c0, then the LSB of c0, etc. 5. Write 00010bin in the NORM register to enable rounding, and to select range of bits, for example bits 33 to18 of the 40 bit internal result. 6. Write 1101bin in the Configuration register to start the filter. At each new incoming sample, XIN, specified by a low level on DIV. The filtered sample XOUT is calculated and is notified by a low level on DOV. The (continued) 7 Application Examples (Continued) filtered XOUT is output 4 clock cycles after the sampling of the corresponding XIN input. A 130-Tap FIR Filter in Intel Mode Absolute Maximum Ratings (Continued) TA Temperature range -40 +85 C TSG Storage temperature -65 +150 C Industrial Example with coefficient LSB ahead and rounding disabled. 1. 2. 3. 4. 5. 6. yn=c0xn + c1xn-1 + ....... + c128xn-12 + c129xn-129 Firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a Master reset). Write 1010bin in the configuration register. This sets the configuration with bit 0 selecting stop mode, bit 1 selecting Intel mode, bit 2 selecting LSB ahead, and bit 3 locks the configuration. Write the Filter Order-1 in the FILT_ORD register, i.e. 81hex Write the 130 coefficients beginning with the LSB of c0, then the MSB of c0, etc. Write 11xxx in the NORM register to disable rounding and to select bits 39 to 24 of the 40 bit internal result.. Write 1011bin in the Configuration register to start the filter. At each new transition high to low on DIV input signal, a new sample is fed into the filter. The corresponding filtered sample is output 4+33 clock cycles later and specified by a low level on DOV output signal. Here the incoming sample rate must at most be 33 times less than the circuit clock rate, where 33 represents the number of times the 4th order cell is multiplexed. Electrical Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Conditions VDD DC supply voltage -0.5 5.5 V VI DC input voltage -0.5 VDD+ 0.5V V or see +-IIk VO DC output voltage -0.5 VDD+ 0.5V V or see +-IOk +-IIk DC input diode current 10 mA VI<-0.5V VI>VDD+0.5V +-IOk DC output diode current 20 mA VO<-0.5V VO>VDD+0.5V IOLMAX Continuous output current 10 mA Industrial IOHMAX Continuous output current 10 mA Industrial TSH Time of outputs shorted 5 sec (continued) 8 AT76C001 Recommended Operating Conditions Symbol Parameter Min Typ Max Unit Conditions VDD DC supply voltage 4.5 5.0 5.5 V VI DC input voltage 0 5.0 VDD V VO DC output voltage 0 5.0 VDD V TA Temperature range -40 +85 C Ind TR Input rise time 15 ns 10%-90% CMOS TF Input fall time 15 ns 10%-90% CMOS DC Characteristics Symbol Parameter Min Max Unit Conditions IIH Input leakage, no pullup -1.0 +1.0 uA VIN = VDD = 5.5V IIL Input leakage, no pullup -1.0 +1.0 uA VIN = 0 VDD=5.5V IOZ Highimpedance output current bi-directional pins -1.0 +1.0 uA VDD=5.5V VIL Low level input voltage 30% VDD V CMOS inputs and bi-dir VIH High level input voltage V CMOS inputs and bi-dir VOL Low level output voltage V IOL=5.0mA VOH High level output voltage V IOH=5.0mA CIN Input capacitance 70% VDD 0.5 VDD0.5 7 pF AT76C001 AC Characteristics Code Description Min Max Units TCPH Clock period 37 ns TCLH Clock high 15 ns TCLL Clock low 15 ns TWRP Write/read period 37 ns TWRH Write/read high 15 ns TWRL Write/read low 15 ns TSIS Synchronous signals to rising clock setup 5 ns TSIH Synchronous inputs to rising clock hold 5 ns TSOD Synchronous outputs to rising clock delay 10 ns TWRCLD Write/read to clock high 5 ns TACWS Asynchronous input setup 20 ns TACWH Asynchronous inputs hold 5 TAOE Asynchronous output enable 12 ns TAOD Asynchronous output disable 7 ns ns See the illustration below for the interpretations of these characteristics. AC Characteristics for Single Mode Operation T CL P TC LL C LOC K T CL H TS IS RST_XI DIV TS IH XIN T SO D DOV XOUT D S Motorola WR Intel RD Intel CS R D / W R M otor ola T WR L TWR CLD TWRH TACWS TWRP TACWH ADD TAOE D AT A DATA IN T AO D DATA O UT 9