GM72V28841AT/ALT 4Banks x 4M x 8Bit Synchronous DRAM Description Pin Configuration The GM72V28841AT/ALT is a synchronous dynamic random access memory comprised of 134,217,728 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC The GM72V28841AT/ALT provides four banks of 4,194,304 word by 8 bit to realize high bandwidth with the Clock frequency up to 133 Mhz. Features * PC133/PC100/PC66 Compatible -75(133MHz)/-8(125MHz) -7K(PC100,2-2-2)/-7J(PC100,3-2-2) -10K(PC66) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 100/125/133 MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh/ Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit * JEDEC Standard 54Pin 400mil TSOP II Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin Name CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ VCC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask VCC for DQ VSS for DQ Power for internal circuit Ground for internal circuit No Connection This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 GM72V28841AT/ALT Block Diagram A0 to A13 A0 to A9 Bank 2 4096 row x 1024 column x 8 bit DQ0 to DQ7 Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Bank 3 4096 row x 1024 column x 8 bit Control logic & timing generator DQM Output buffer Memory array CAS Input buffer Column decoder Sense amplifier & I/O bus 4096 row x 1024 column x 8 bit Memory array RAS Bank 1 Row decoder CS 4096 row x 1024 column x 8 bit Memory array CKE Bank 0 Refresh counter Row decoder Column decoder Sense amplifier & I/O bus Memory array Row decoder Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Row decoder Row address counter WE Column address buffer CLK Column address counter A0 to A13 2 GM72V28841AT/ALT Pin Description Pin Name DESCRIPTION CLK (input pin) CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CKE (input pin) This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. CS (input pin) When CS is Low, the command input cycle becomes valid. When CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins) Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 ~ A11 (input pins) A12/A13 (input pin) DQM, DQMU/DQML (input pins) Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address(AY0 to AY9; GM72V28841AT/ALT) is determined by A0 to A9 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. A12/A13 are bank select signal (BS). The memory array of the GM72V28841AT/ALT is divided into bank 0, bank 1, bank2 and bank 3. GM72V28841AT/ALT contain 4096-row x 1024-column x 8-bits. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. DQM, DQMU/DQML controls input/output buffers. - Read operation: If DQM, DQMU/DQML is High, The output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. - Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 GM72V28841AT/ALT Pin Description(Continued) Pin Name DESCRIPTION DQ0 ~ DQ3 (I/O pins) Data is input and output from these pins. These pins are the same as those of a conventional DRAM. VCC and VCCQ (power supply pins) 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VSS and VSSQ (power supply pins) Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) NC No Connection pins. Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. CKE n n-1 CS RAS CAS WE A12~ A13 A10 A0~ A11 X H X X X X X X H X L H H H X X X BST H X L H H L X X X READ H X L H L H V L V READ A H X L H L H V H V WRIT H X L H L L V L V Write with auto-precharge WRIT A H X L H L L V H V Row address strobe and bank active ACTV H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X REF/SELF H V L L L H X X X MRS H X L L L L V V V Function Symbol Ignore command DESL H No Operation NOP Burst stop in full page Column address and read command Read with auto-precharge Column address and write command Precharge select bank Precharge all banks Refresh Mode register set * Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 GM72V28841AT/ALT Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignores command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full page [BST] : This command stops a full-page burst operation (burst length = full-page(1024:GM72V28841AT/ALT), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for full-page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY9:GM72V28841AT/ALT,) and the bank select address (A12/A13). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY9; GM72V28841AT/ALT) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY9; GM72V28841AT/ALT) and the bank select address (A12/A13). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13(BS) and determines the row address (AX0 to AX11). If A12 is Low and if A13 is Low, bank 0 is activated. If A12 is High and A13 is Low, bank 1 is activated. If A12 is Low and A13 is High, bank 2 is activated. If A12 is High and A13 is High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 is Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 GM72V28841AT/ALT DQM Truth Table Function Symbol CKE n-1 n DQM Write enable/output enable ENB H X L Write inhibit/output disable MASK H X H * Notes : H: VIH, L: VIL, X: VIH or VIL. Write : lDID is needed. Read : lDOD is needed. The GM72V28841AT/ALT can mask input/output data by means of DQM. During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQM. For details, refer to the DQM control section of the GM72V28841AT/ALT operating instructions. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 GM72V28841AT/ALT CKE Truth Table Current State CKE Function n -1 n CS RAS CAS WE Address Active Clock suspend mode entry H L H X X X X Any Clock suspend L L X X X X X Clock Suspend Clock suspend mode exit L H X X X X X Idle Auto-refresh command (REF) H H L L L H X Idle Self-refresh entry (SELF) H L L L L H X Power down entry H L L H H H X Idle H L H X X X X L H L H H H X L H H X X X X L H L H H H X L H H X X X X Self refresh Power down Self refresh exit (SELFX) Power down Exit * Notes : H: VIH, L: VIL, X: VIH or VIL. Clock suspend mode entry: The synchronous DRAM enters Clock suspend mode from active mode by setting CKE to Low. The Clock suspend mode changes depending on the current status (1 Clock before) as shown below. ACTIVE Clock suspend: This suspend mode ignores inputs after the next Clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During Clock suspend mode, keep the CKE to Low. Clock suspend mode exit : The synchronous DRAM exits from Clock suspend mode by setting CKE to High during the Clock suspend state. IDLE: In this state, all banks are not selected, and completed Precharge operation. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 GM72V28841AT/ALT Auto-refresh command[REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4,096 times are required to refresh the entire memory. Before executing the autorefresh command, all the banks must be in the IDLE state. In addition, since the Precharge for all banks is automatically performed after autorefresh, no Precharge command is required after auto-refresh. Self-refresh exit[SELFX]: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters Power down mode. In Power down mode, Power consumption is suppressed by cutting off the initial input circuit. Power down exit: When this command is executed at the Power down mode, the synchronous DRAM can exit from Power down mode. After exiting from Power down mode, the synchronous DRAM enters the IDLE state. Self-refresh entry[SELF]: W h e n t h i s command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state CS RAS CAS WE Precharge H X X X X DESL Enter IDLE after tRP L H H H X NOP Enter IDLE after tRP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL NOP Address Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Command Operation 8 GM72V28841AT/ALT Function Truth Table (Continued) Current state CS RAS CAS WE Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL NOP L L L H X REF, SELF Refresh L L L L MODE MRS Mode register set H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Idle Row active Address Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Command Operation 9 GM72V28841AT/ALT Function Truth Table (Continued) Current state CS RAS CAS WE Read H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop to full page L H L H BA, CA, A10 READ/READ A Continue burst read to CAS latency and New read L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Term burst read and Precharge L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and precharge L H H H X NOP Continue burst to end and precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Read with autoprecharge Address Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Command Operation 10 GM72V28841AT/ALT Function Truth Table (Continued) Current state CS RAS CAS WE Write H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Term burst and New read L H L L BA, CA, A10 WRIT/WRIT A L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL Term burst write and precharge*2 L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H X X X X DESL Continue burst to end and precharge L H H H X NOP Continue burst to end and precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active *3 ILLEGAL on same bank L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Write with autoprecharge Address Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Command Operation Term burst and New write 11 GM72V28841AT/ALT Function Truth Table (Continued) Current state Refresh (auto-refresh) CS RAS CAS WE Address Command Operation H X X X X DESL Enter IDLE after tRC L H H H X NOP Enter IDLE after tRC L H H L X BST Enter IDLE after tRC L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL ILLEGAL L L L H X REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL * Notes : 1. H: VIH, L: VIL, X: VIH or VIL. The other combinations are inhibit. 2. An interval of tRWL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 4. BA:Bank Address, RA:Row Address, CA:Column Address From [PRECHARGE] From [ROW ACTIVE] To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge From [IDLE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of t RCD is required.) To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t RCD is required.) To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of tRAS is required.) 12 GM72V28841AT/ALT From [READ] From [WRITE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. From [READ with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank-active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an autorefresh cycle (after t RC ), the synchronous DRAM automatically enters the Idle state. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 GM72V28841AT/ALT Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT -0.5 to Vcc+0.5 (<= 4.6 (max)) V 1 Supply voltage relative to VSS VCC -0.5 to +4.6 V 1 Short circuit output current IOUT 50 mA PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Power dissipation Notes : 1. Respect to VSS Recommended DC Operating Conditions (Ta = 0 to + 70C) Parameter Symbol Min Max Unit Note VCC, VCCQ 3.0 3.6 V 1 VSS, VSSQ 0 0 V Input high voltage VIH 2.0 Vcc + 0.3 V 1, 2 Input low voltage VIL -0.3 0.8 V 1,3 Supply voltage Notes : 1. All voltage referred to VSS. 2. VIH (max) = 5.6V for pulse width <= 3ns 3. VIL (min) = -2.0V for pulse width <= 3ns Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 GM72V28841AT/ALT DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) Parameter - 75 -8 - 7K - 7J - 10K Max Max Max Max Max Symbol Unit Test conditions Notes Burst length= 1 tRC = min CKE = VIL, tCK = 12 ns Operating current ICC1 130 120 120 120 110 mA Standby current in power down ICC2P 2 2 2 2 2 mA 1 1 1 1 1 0.4 0.4 0.4 0.4 0.4 ICC2N 15 15 15 15 15 mA CKE,CS = VIH, tCK = 12ns 4 ICC2NS 15 15 15 15 15 mA CKE,CS = VIH, tCK = Infinity 4 1,2,5 2,6 Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) ICC2PS mA CKE=VIL, tCK= Infinity 1, 2, 3 5 6 6,8 ICC3P 5 5 5 5 5 mA CKE = VIL, tCK = 12 ns, DQ = High-Z Active standby current in power down ICC3PS (input signal stable) 5 5 5 5 5 mA CKE = VIL, tCK = Infinity 1,2,4 2,9 Active standby current in power down ICC3N 30 30 30 30 30 mA CKE,CS = VIH, tCK = 12 ns, DQ = High-Z Active standby current in non power down ICC3NS (input signal stable) 30 30 30 30 30 mA CKE,CS = VIH, tCK = Infinity tCK = min Active standby current in non power down Burst operating current ( CL= 2 ) ICC4 130 130 130 100 100 mA ( CL= 3 ) ICC4 150 140 130 130 130 mA Refresh current ICC5 230 230 220 220 190 mA tRC = min 3 2 2 2 2 2 Self refresh current ICC6 mA VIH >=VCC - 0.2 VIL <=0.2V 7 0.8 0.8 0.8 Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.8 0.8 BL = 4 1,2,3 7,8 15 GM72V28841AT/ALT - 75, - 8, - 7K, -7J, -10K Parameter Symbol Unit Test conditions Notes Min Max Input leakage current ILI -1 1 uA 0<=Vin<=VCC Output leakage current ILO -1.5 1.5 uA 0<=Vout <=VCC DQ = disable Output high voltage VOH 2.4 - V IOH = -2 mA Output low voltage VOL - 0.4 V IOL =2 mA Notes : 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. L-Version. 9. Input signals are VIH or VIL fixed. Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V +/- 0.3 V) Parameter Symbol Min. Max. Unit Notes Input capacitance (CLK) CI1 2.5 4 pF 1, 3, 4 Input capacitance (Signals) CI2 2.5 5 pF 1, 3, 4 Output capacitance (DQ) CO 4.0 6.5 pF 1, 2, 3, 4 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM, DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. 4. Measured with 1.4 V bias and 200mV swing at the pin under measurement. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 GM72V28841AT/ALT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) - 75 Parameter System clock cycle time (CL=2) (CL=3) CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Symbol tCK tCK tCKH tCKL tAC tAC tOH -8 - 7K - 7J - 10K Min Max Min Max Min Max Min Max Min Max 12 - 12 - 10 - 15 - 15 - 7.5 - 8 - 10 - 10 - 10 - 2.5 - 3 - 3 - 3 - 3 2.5 - 3 - 3 - 3 - - 6 - 6 - 6 - - 5.4 - 6 - 6 2.7 - 3 - 3 tLZ 1.5 - 2 - tHZ - 5.4 - tDS tDH tAS tAH tCES 1.5 - 0.8 Unit Notes ns 1 - ns 1 3 - ns 1 8 - 9 ns 1, 2 - 6 - 8 - 3 - 3 - ns 1, 2 2 - 2 - 2 - ns 1, 2, 3 6 - 6 - 6 - 7 ns 1, 4 2 - 2 - 2 - 2 - ns 1 - 1 - 1 - 1 - 1 - ns 1 1.5 - 2 - 2 - 2 - 2 - ns 1 0.8 - 1 - 1 - 1 - 1 - ns 1 1.5 - 2 - 2 - 2 - 2 - ns 1, 5 tCESP 1.5 - 2 - 2 - 2 - 2 - ns 1 tCEH 0.8 - 1 - 1 - 1 - 1 - ns 1 tCS 1.5 - 2 - 2 - 2 - 2 - ns 1 tCH 0.8 - 1 - 1 - 1 - 1 - ns 1 tRC 67.5 - 72 - 70 - 70 - 90 - ns 1 tRAS 45 120000 48 120000 50 120000 50 120000 60 120000 ns 1 tRCD 20 - 20 - 20 - 20 - 30 - ns 1 tRP 20 - 20 - 20 - 20 - 30 - ns 1 Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 17 GM72V28841AT/ALT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) (Continued) - 75 Parameter Symbol Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Refresh period -8 - 7K - 7J - 10K Min Max Min Max Min Max Min Max Min Max Unit Notes tRWL 7.5 - 8 - 10 - 10 - 15 - ns 1 tRRD 15 - 16 - 20 - 20 - 20 - ns 1 tREF - 64 - 64 - 64 - 64 - 64 ms Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V. If tT is longer than 1ns,transition time compensation should be considered. 2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination. 3. tLZ (min)defines the time at which the outputs achieves the low impedance state. 4. tHZ (max)defines the time at which the outputs achieves the high impedance state. 5. tCES define CKE setup time to CKE rising edge except Power down exit command. Test Condition • Input and output-timing reference levels: 1.4V • Input waveform and output load: See following figures I/O 2.4V OPEN 80% input 0.4V 20% CL tT tT Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 18 GM72V28841AT/ALT Relationship Between Frequency and Minimum Latency -75 Parameter frequency(MHz) DQM to data out CKE to CLK disable Register set to active command CS to command disable Power down exit to command input -7K Symbol 133 83 125 83 tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in -8 -7J -10K 100 100 100 66 100 66 Notes 7.5 12 8 12 10 10 10 15 10 15 lRCD 3 2 3 2 2 2 2 2 3 2 1 lRC 9 6 9 6 7 7 7 6 9 6 = [lRAS +lRP], 1 lRAS 6 4 6 4 5 5 5 4 6 4 1 lRP 3 2 3 2 2 2 2 2 3 2 1 lRWL 1 1 1 1 1 1 1 1 1 1 1 lRRD 2 2 2 2 2 2 2 2 2 2 1 lSREX 1 1 1 2 1 1 1 2 2 2 lAPW 4 3 4 3 3 3 3 3 5 3 = [lRWL +lRP], 1 lSEC 9 6 9 6 7 7 7 6 9 6 = [lRC] lHZP lHZP - 2 - 2 2 2 - 2 - 2 3 3 3 3 3 3 3 3 3 3 lAPR 1 1 1 1 1 1 1 1 1 1 lEP lEP - -1 - -1 -1 -1 - -1 - -1 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 lCCD 1 1 1 1 1 1 1 1 1 1 lWCD 0 0 0 0 0 0 0 0 0 0 lDID lDOD lCLE lRSA lCDD 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 lPEC 1 1 1 1 1 1 1 1 1 1 Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 19 GM72V28841AT/ALT Relationship Between Frequency and Minimum Latency -75 Parameter frequency(MHz) Symbol 133 83 tCK (ns) Burst stop to (CL=2) output valid (CL=3) data hold Burst stop to (CL=2) output high (CL=3) impedance Burst stop to write data ignore -8 lBSR lBSR lBSH lBSH lBSW - 7K - 7J - 10K 125 83 100 100 100 66 100 66 7.5 12 8 12 10 10 10 15 10 15 - 1 - 1 1 1 - 1 - 1 2 2 2 2 2 2 2 2 2 2 - 2 - 2 2 2 - 2 - 2 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 Notes Notes : 1. lRCD to lRRD are recommended value. Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 20 GM72V28841AT/ALT Package Dimensions GM72V28841AT/ALT Series (TTP-54D) Unit: (mm) Preliminary 22.22 22.72 Max 28 10.16 54 0.80 1 27 +0.10 - 0.05 0.30 0.28 + 0.05 0.13 M 0.80 11.76 + 0.20 Dimension including the plating thickness Base material dimension Rev. 1.0/Dec.99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 £ 0.13+ 0.05 0.125 + 0.04 0.10 0.145 + 0.05 1.20 MAX 0 ~¡5 0.50 + 0.10 Hitachi Code TTP-54D JEDEC Code - EIAJ Code - Weight(reference value) 0.53g 0.68 0.91 MAX 21