FUJITSU MB81ES123245-10

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11440-2E
MEMORY
CMOS
128 M-BIT (4-BANK × 1 M-WORD × 32-BIT)
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES123245-10
■ DESCRIPTION
The Fujitsu MB81ES123245 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 134,217,728 memory cells accessible in a 32-bit format. The MB81ES123245 features a fully synchronous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES123245 is dedicated for SiP (System in a Package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
■ PRODUCT LINEUP
Parameter
MB81ES123245-10
Clock Frequency (Max)
Burst Mode Cycle Time (Min)
Access Time from CLK (Max)
CL = 2
54 MHz
CL = 3
108 MHz
CL = 2
18.5 ns
CL = 3
9.2 ns
CL = 2
9 ns
CL = 3
7 ns
Operating Current (Max) (64 page length)
35 mA
Power Down Mode Current (Max) (IDD2PS)
0.5 mA
Self-Refresh Current (Max)
Tj = +35 °C Max
Copyright©2006 FUJITSU LIMITED All rights reserved
200 µA
MB81ES123245-10
■ FEATURES
• 1 M word × 32 bit × 4 banks organization
• Low power supply
- VDD : +1.7 V to +1.9 V
- VDDQ : +1.7 V to +1.9 V
• 1.8V CMOS I/O interface
• 4 K refresh cycles every 64 ms
• Auto- and Self-refresh
• Four banks operation
• Programmable burst type, burst length, and CAS Latency
• Burst read/write operation and burst read/single write operation capability
• Programmable page length function
• Programmable Partial Array Self-Refresh (PASR)
• Programmable Driver Strength (DS)
• Deep power down mode
• Junction temperature (Tj) : −25 °C to +95 °C
• CKE power down mode
• Output enable and input data mask
• Self burn-in function for TEST
• Built In Self Test (BIST) function for TEST
2
MB81ES123245-10
■ PAD LAYOUT
Pad No.1
VDD
VSS
⎯
VSS
⎯
⎯
⎯
DQ15
⎯
DQ14
⎯
⎯
DQ12
⎯
DQ13
⎯
⎯
DQ11
⎯
DQ10
VDDQ
VSSQ
DQ8
⎯
DQ9
⎯
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VSS
VDD
CKE
CLK
CSB
RASB
CASB
WEB
BA0
BA1
A11
A12
A13
VSS
⎯
DQ1
⎯
DQ0
VSSQ
VDDQ
DQ2
⎯
DQ3
⎯
⎯
DQ5
⎯
DQ4
⎯
⎯
DQ8
⎯
DQ7
⎯
VSS
VSS
VDD
Pad No.74
Pad No.75
VDD
VSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DQ23
⎯
DQ22
⎯
⎯
DQ20
⎯
DQ21
⎯
⎯
DQ19
⎯
DQ18
VDDQ
VSSQ
DQ16
⎯
DQ17
⎯
⎯
DQM1
⎯
DQM0
VDD
VSS
DQM2
⎯
DQM3
⎯
⎯
DQ25
⎯
DQ24
VSSQ
VDDQ
DQ26
⎯
DQ27
⎯
⎯
DQ29
⎯
DQ28
⎯
⎯
DQ30
⎯
DQ31
⎯
⎯
⎯
VSS
VDD
Pad No.138
Pad No. 74
Pad No. 1
MB81ES123245
Pad No. 75
Pad No.138
3
MB81ES123245-10
■ PAD DESCRIPTIONS
Symbol
VDDQ, VDD
Function
Supply Voltage
DQ31 to DQ0
Data I/O
VSSQ, VSS
Ground
WE (WEB)
Write Enable
CAS (CASB)
Column Address Strobe
RAS (RASB)
Row Address Strobe
CS (CSB)
Chip Select
BA1, BA0
Bank Select (Bank Address)
AP
A13 to A0 *
Auto Precharge Enable
Address Input
CKE
Clock Enable
CLK
Clock Input
DQM3 to DQM0
⎯
Row
Column
256 page
A11 to A0
A7 to A0
128 page
A12 to A0
A6 to A0
64 page
A13 to A0
A5 to A0
Input Mask/Output Enable
Don’t Bond
* : A12 must be connected to VSS in 256 page length mode. A13 must be connected to VSS in 256 page length
mode and 128 page length mode.
4
MB81ES123245-10
■ BLOCK DIAGRAM
BANK-3
To each block
CLK
BANK-2
CLOCK
BUFFER
BANK-1
CKE
BANK-0
RAS
CS
CONTROL
SIGNAL
LATCH
RAS
CAS
WE
COMMAND
DECODER
WE
MODE
REGISTER
A9 to A0,
A10/AP,
A13 to A11
BA1, BA0
CAS
FCRAM
CORE
(1,048,576 × 32)
ROW
ADDRESS
ADDRESS
BUFFER/
REGISTER
COL.
ADDRESS
COLUMN
ADDRESS
COUNTER
DQM3
to
DQM0
DQ31
to
DQ0
I/O DATA
BUFFER/
REGISTER
I/O
VDDQ
VDD
VSS
VSSQ
5
MB81ES123245-10
■ FUNCTIONAL TRUTH TABLE *1
1. COMMAND TRUTH TABLE *2, *3, *4
Function
Command
Device Deselect *5
CKE
n-1
n
CS RAS CAS WE
BA
A10
(AP)
Address
(Except for A10)
DESL
H
X
H
X
X
X
X
X
X
5
NOP
H
X
L
H
H
H
X
X
X
7
BST
H
X
L
H
H
L
X
X
X
READ
H
X
L
H
L
H
V
L
Column Address
READA
H
X
L
H
L
H
V
H
Column Address
WRIT
H
X
L
H
L
L
V
L
Column Address
WRITA
H
X
L
H
L
L
V
H
Column Address
ACTV
H
X
L
L
H
H
V
Precharge Single Bank
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
H
X
MRS
H
X
L
L
L
L
V
V
V
No Operation *
6
Burst Stop * , *
Read *7
Read with Auto-precharge *7
Write *
7
Write with Auto-precharge *
Bank Active *8
9
Mode Register Set * , *
10
7
Row Address
*1 : V = Valid, L = VIL, H = VIH, X = either VIL or VIH.
Row Address
256 page length : A11 to A0
128 page length : A12 to A0
64 page length : A13 to A0
Column Address
256 page length : A7 to A0
128 page length : A6 to A0
64 page length : A5 to A0
*2 : All commands assume no CSUS command on previous rising edge of clock.
*3 : All commands are assumed to be valid state transitions.
*4 : All inputs are latched on the rising edge of clock.
*5 : NOP and DESL commands have the same effect. Unless specifically noted, NOP will represent both NOP
and DESL command in later description.
*6 : When the current state is idle and CKE = L, BST command will represent Deep Power Down command.
Refer to “1. COMMAND TRUTH TABLE” and “3. CKE TRUTH TABLE”.
*7 : READ, READA, WRIT, WRITA and BST commands should only be issued after the corresponding bank has
been activated (ACTV command) . Refer to “■STATE DIAGRAM”.
*8 : ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command) .
*9 : Required after power up. Refer to “22. POWER-UP INITIALIZATION” in section “■FUNCTIONAL
DESCRIPTION”.
*10 : MRS command should only be issued after all banks have been precharged (PRE or PALL command) .
Refer to “■STATE DIAGRAM”.
6
MB81ES123245-10
2. DQM TRUTH TABLE
Function
CKE
Symbol
n-1
n
DQMi *1, *2
Data Write/Output Enable
ENBi *1
H
X
L
Data Mask/Output Disable
MASKi *1
H
X
H
*1 : i = 0, 1, 2, 3
*2 : DQM0, DQM1, DQM2 and DQM3 controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and DQ31 to DQ24, respectively.
3. CKE TRUTH TABLE *1
BA
A10
(AP)
Address
(Except
for A10)
CKE
Current State
Function
Command
n-1
n
CS
RAS CAS WE
Bank Active
Clock Suspend
Mode Entry *2
CSUS
H
L
X
X
X
X
X
X
X
Any
(Except Idle)
Clock Suspend
Continue *2
⎯
L
L
X
X
X
X
X
X
X
Clock Suspend
Clock Suspend
Mode Exit
⎯
L
H
X
X
X
X
X
X
X
Idle
Auto-refresh
Command *3
REF
H
H
L
L
L
H
X
X
X
Idle
Self-refresh Entry
*3, *4
SELF
H
L
L
L
L
H
X
X
X
Self Refresh
Self-refresh Exit *5
SELFX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
Idle
Power Down Entry
*3, *4
PD
H
L
L
H
H
H
X
X
X
H
L
H
X
X
X
X
X
X
Power Down
Power Down Exit
PDX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
Idle
Deep Power Down
Entry *3, *4
DPD
H
L
L
H
H
L
X
X
X
Deep Power
Down
Deep Power Down
Exit
DPDX
L
H
L
H
H
H
X
X
X
L
H
H
X
X
X
X
X
X
*1 : Address : A11 to A0 @256 page length mode
: A12 to A0 @128 page length mode
: A13 to A0 @64 page length mode
*2 : The CSUS command requires that at least one bank is active. Refer to “■STATE DIAGRAM”.
*3 : REF, SELF, PD and DPD commands should only be issued after all banks have been precharged
(PRE or PALL command) . Refer to “■STATE DIAGRAM”.
*4 : SELF, PD and DPD commands should only be issued after the last read data have been appeared on DQ.
*5 : CKE should be held High during tREFC period after tCKSP.
7
MB81ES123245-10
4. OPERATION COMMAND TABLE (single bank operation) *1
Current
State
Idle
Bank Active
Read
CS
RAS
CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
NOP *5
L
L
L
H
X
REF/SELF
Auto-refresh or Self-refresh *3, *6
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA Begin Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, New Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, Start Write;
Determine AP *4
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
NOP
Illegal *2
Bank Active after tRCD
Mode Register Set
(Idle after tRSC) *3, *7
NOP
Begin Write; Determine AP
Illegal *2
Begin Precharge; Determine
Precharge Type
Illegal
Illegal *2
Terminate Burst, Precharge →
Idle
Illegal
(Continued)
8
MB81ES123245-10
Current
State
Write
Read with
Autoprecharge
Write with
Autoprecharge
CS
RAS
CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Burst Stop → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, Start Read;
Determine AP *4
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, New Write;
Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge → Idle)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
Illegal *2
Terminate Burst, Precharge →
Idle
Illegal
Illegal *2
Illegal
Illegal *2
Illegal
(Continued)
9
MB81ES123245-10
(Continued)
Current
State
Precharging
Bank
Activating
CS
RAS
CAS
WE
Address
Command
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
H
BA, CA, AP
READ/READA
L
H
L
L
BA, CA, AP
WRIT/WRITA
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE/PALL
L
L
L
H
X
REF/SELF
L
L
L
L
MODE
MRS
H
X
X
X
X
DESL
L
H
H
X
X
NOP/BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
L
L
H
X
X
ACTV/
PRE/PALL
L
L
L
X
X
REF/SELF/
MRS
H
X
X
X
X
DESL
L
H
H
H
X
NOP
L
H
H
L
X
BST
L
H
L
X
X
READ/READA/
WRIT/WRITA
X
ACTV/PRE/
PALL/REF/
SELF/MRS
Refreshing
Mode
Register
Setting
L
L
X
X
RA = Row Address
BA = Bank Address
CA = Column Address AP = Auto Precharge
10
Function
NOP (Idle after tRP)
NOP (Idle after tRP) *8
Illegal *2
NOP (PALL may affect other
bank) *5
Illegal
NOP (Bank Active after tRCD)
Illegal *2
Illegal
NOP (Idle after tRC)
NOP (Idle after tRC) *8
Illegal
NOP (Idle after tRSC)
Illegal
MB81ES123245-10
*1 : When a command is input, CKE should be held High from the preceding clock cycle. If any illegal command is
asserted, following command operation and data cannot be guaranteed. If the illegal command is input, the
power-up initialization is needed again.
*2 : Illegal to bank in the specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*3 : Illegal if any bank is not idle.
*4 : Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to “7. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ BL = 4) ” and “12. WRITE TO READ
TIMING (EXAMPLE @ CL = 3, BL = 4) ” in section “■TIMING DIAGRAMS”.
*5 : NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP) .
*6 : SELF command should only be issued after the last read data have been appeared on DQ.
*7 : MRS command should only be issued on condition that all DQ are in High-Z.
*8 : BST command should only be issued with CKE = High.
11
MB81ES123245-10
5. COMMAND TRUTH TABLE FOR CKE *1
Current State
Selfrefresh
Selfrefresh
Recovery
Power
Down
Deep Power
Down
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
Exit Self-refresh
(Self-refresh Recovery
→ Idle after tRC)
L
H
L
H
H
L
X
L
H
L
H
L
X
X
L
H
L
L
X
X
X
L
L
X
X
X
X
X
NOP (Maintain Self-refresh)
L
X
X
X
X
X
X
Invalid
H
H
H
X
X
X
X
H
H
L
H
H
H
X
H
H
L
H
H
L
X
H
H
L
H
L
X
X
H
H
L
L
X
X
X
H
H
X
X
X
X
X
H
L
X
X
X
X
X
Illegal *2
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
L
L
X
X
X
X
X
L
H
L
L
X
X
X
L
H
L
H
L
X
X
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
L
H
L
H
H
H
X
Exit Deep Power Down Mode →
Idle *3
L
L
X
X
X
X
X
L
H
L
L
X
X
X
L
H
L
H
L
X
X
Function
Illegal
Idle after tRC
Illegal
Exit Power Down Mode → Idle
NOP
(Maintain Power Down Mode)
Illegal
NOP (Maintain Deep Power Down
Mode)
Illegal
(Continued)
12
MB81ES123245-10
(Continued)
Current State
Bank Active
Bank
Activating
Read/Write
All Banks Idle
Precharging
Refreshing
Clock
Suspend
Any State
Other Than
Listed Above
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
X
X
X
X
X
Refer to “4. Operation Command
Table”. Start Clock Suspend next
cycle
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
L
H
H
L
X
Illegal
H
L
H
X
X
X
X
H
L
L
L
X
X
X
H
L
L
H
L
X
X
H
L
L
H
H
H
X
L
X
X
X
X
X
X
Invalid
H
X
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to “4. Operation Command
Table”.
H
L
X
X
X
X
X
Illegal
Function
Refer to “4. Operation Command
Table”.
*1 : All entries are specified at CKE (n) state. CKE input must satisfy corresponding set up and hold time for CKE.
*2 : CKE should be held High during tREFC period.
*3 : After deep power down exit, it requires “19. DEEP POWER DOWN EXIT” procedure in section “■TIMING
DIAGRAMS”.
13
MB81ES123245-10
■ FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM BASIC FUNCTION
This SDR I/F FCRAMs have major three features of which are the same functions as conventional SDRAMs :
“synchronized operation”, “burst mode”, and “mode register” for setting the operation mode. The MB81ES123245
are compatible with conventional SDRAMs regarding the basic electrical function and interface.
The synchronized operation is the fundamental function. An MB81ES123245 requires an external clock input
(CLK) for the synchronization. Each operation of MB81ES123245 is determined by commands and all operations
function synchronizing with the rising edge of the clock.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to justify the MB81ES123245 operation and function into desired system conditions. Refer
to “■MODE REGISTER TABLE”.
2. FCRAM
The MB81ES123245 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access
Memory, which provides very fast random cycle time, low latency and low power consumption than conventional
SDRAMs.
3. CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of MB81ES123245 use register type buffers. A CLK is used as a trigger for the
registers and internal burst counter increment. All inputs are latched by a rising edge of CLK. All outputs are
validated by the CLK. CKE is a high active clock enable signal, and controls an internal clock generator. CKE is
latched at the rising edge of CLK. It is required to set High one clock cycle before the command input cycle.
When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During
idle state (all banks have been precharged) , the Power Down mode is entered with CKE = Low and this will
make low standby current. The standby current of the Deep Power Down mode is lower than that of the Power
Down mode. This mode is entered with CKE = Low, RAS = CAS = High and WE = Low.
4. CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, WE, and address input. When CS is High, command signals are
negated but internal operation such as burst cycle are not stopped. If such a control isn’t needed, CS can be
tied to ground level.
5. COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply MB81ES123245 operation, such as Row
address strobe by RAS. Instead, a combination of RAS, CAS, and WE input referring CS input at a rising
edge of the CLK determines MB81ES123245 operation. Refer to “1. COMMAND TRUTH TABLE” in section
“■FUNCTIONAL TRUTH TABLE.”
6. ADDRESS INPUT (A13 to A0)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Row address
field defined by selected page length is as follows : 256 page length = A11 to A0, 128 page length = A12 to A0,
64 page length = A13 to A0. Total twenty address input signals by a combination of row address and column
address are required to decode a matrix. MB81ES123245 adopts an address multiplexer in order to reduce the
pin count of the address line. The row address is first latched by the Bank Active command (ACTV) , and the
column address is then latched by a column address strobe command of either the Read command (READ or
READA) or the Write command (WRIT or WRITA) .
14
MB81ES123245-10
7. BANK SELECT (BA1, BA0)
This MB81ES123245 has four banks and each bank is organized as 1 M words by 32-bit. Bank selection by BA
occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRITA) , and
precharge command (PRE) .
8. DATA I/O (DQ31 to DQ0)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input :
tRAC ; Time from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.)
tCAC ; Time from the read command when tRCD is greater than tRCD (Min) . (This parameter is reference only.)
tAC ; Time from the rising clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input data. Data valid period is between access time
(determined by the three conditions above) and the next rising clock edge plus output hold time (tOH) .
9. INPUT MASK/OUTPUT ENABLE (DQM3 to DQM0)
DQM is an active high enable input and has an output disable and input mask function. When DQM = High is
latched during burst cycle, input is masked at the same clock and output will be masked at the second clock
later while internal burst counter will increment by one or will go to the next stage depending on burst type.
DQM0, DQM1, DQM2, DQM3, controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, DQ31 to DQ24, respectively.
10. BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same row
address and by automatic strobing column address. Access time and cycle time of burst mode is specified as
tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which
defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary or full column. In order to terminate or
to move from the current burst mode to the next stage while the remaining burst count is more than 1, the
following combinations will be required.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Burst Read
Burst Write
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
Read Command
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after lOWD
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential
mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns
+ 1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least
significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A2 and A0. If the first access
of column address is even (the least significant bit is 0) , the next address will be odd (the least significant bit is
1) , or vice-versa. When the full column burst operation is executed at single write mode, Auto-precharge
command is valid only at write operation.
15
MB81ES123245-10
Burst
Length
2
4
8
Starting Column
Address
A2 A1 A0
Sequential Mode
Interleave Mode
X X 0
0−1
0−1
X X 1
1−0
1−0
X 0 0
0−1−2−3
0−1−2−3
X 0 1
1−2−3−0
1−0−3−2
X 1 0
2−3−0−1
2−3−0−1
X 1 1
3−0−1−2
3−2−1−0
0 0 0
0−1−2−3−4−5−6−7
0−1−2−3−4−5−6−7
0 0 1
1−2−3−4−5−6−7−0
1−0−3−2−5−4−7−6
0 1 0
2−3−4−5−6−7−0−1
2−3−0−1−6−7−4−5
0 1 1
3−4−5−6−7−0−1−2
3−2−1−0−7−6−5−4
1 0 0
4−5−6−7−0−1−2−3
4−5−6−7−0−1−2−3
1 0 1
5−6−7−0−1−2−3−4
5−4−7−6−1−0−3−2
1 1 0
6−7−0−1−2−3−4−5
6−7−4−5−2−3−0−1
1 1 1
7−0−1−2−3−4−5−6
7−6−5−4−3−2−1−0
11. FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full
column burst mode executes by automatically strobing the column address while keeping the same row address.
If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and
continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop
(BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the
burst mode, its operation is terminated immediately and the internal state moves to Bank Active.
When a read mode is interrupted by the BST command, the output will be in High-Z. For the detailed rule, please
refer to “8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 3, BL = Full Column” in section
“■TIMING DIAGRAMS”. When a write mode is interrupted by the BST command, the data to be input at the
same time with the BST command will be ignored.
12. BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
13. PROGRAMMABLE PAGE LENGTH FUNCTION
The programmable page length function provides lower operation current than regular SDRAM. Page length is
selected by Mode Register Set, and the composition of the row address field and column address field are
defined for selected page length as below.
256 page length
128 page length
64 page length
16
Row address
A11 to A0
A12 to A0
A13 to A0
Column address
A7 to A0
A6 to A0
A5 to A0
MB81ES123245-10
Row/column address allocation at each page length is shown as the following table. For example, A13 (row
address) at 64 page length mode is corresponded to A6 (column address) at 128 page length mode.
64 page
length
Row : A13 to A0
128 page
length
Row : A12 to A0
256 page
length
Row : A11 to A0
0
0
0
1
1
1
2
2
2
Column : A5 to A0
3
4
5
6
7
8
9
10
11
12
13
5
4
3
2
1
0
Column : A6 to A0
3
4
5
6
7
8
9
10
11
12
6
5
4
3
2
1
0
Column : A7 to A0
3
4
5
6
7
8
9
10
11
7
6
5
4
3
2
1
0
14. PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
The MB81ES123245 memory core is the same as conventional SDRAMs, requiring precharge and refresh
operations. Precharge rewrites the bit line and resets the internal row address line. With the Precharge command
(PRE) , MB81ES123245 will automatically be in a standby state after precharge time (tRP) . The precharged
bank is selected by combination of AP and BA when Precharge command is asserted. If AP = High, all banks
are precharged regardless of BA (PALL command) . If AP = Low, a bank to be selected by BA is precharged
(PRE command) . The Auto-precharge enters precharge mode at the end of burst mode of read or write without
Precharge command assertion. This Auto-precharge is entered by setting AP = High when a read or write
command is asserted. Refer to “1. COMMAND TRUTH TABLE” in section “■FUNCTIONAL TRUTH TABLE”.
15. AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The MB81ES123245 Auto-refresh command (REF)
generates Precharge command internally. All banks of MB81ES123245 should be precharged prior to asserting
the Auto-refresh command. The Auto-refresh command should also be asserted every 15.6 µs or a total 4,096
refresh commands within every 64 ms period to ensure data stored.
16. SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by the Self-refresh Exit command (SELFX) . The Self-refresh is entered by
applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once MB81ES123245 enters the
Self-refresh mode, all inputs except for CKE will be in a “don’t care” state (High or Low) and all outputs will be
in a High-Z state.
During the Self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after
last read data has been appeared on DQ.
Note : When the burst refresh method is used, a total of 4,096 Auto-refresh commands within 2 ms must be asserted
prior to the Self-refresh mode entry.
17. SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, apply the Self-refresh Exit command (SELFX) after minimum tCKSP from CKE brought
High. After SELFX, the No Operation command (NOP) or the Deselect command (DESL) should be asserted
during tREFC period. CKE should be held High during tREFC period after tCKSP. Refer to “16. SELF-REFRESH ENTRY
AND EXIT” in section “■TIMING DIAGRAMS” for the detail. It is recommended to assert the Auto-refresh
command just after the tREFC period to prevent row addresses not to be refreshed.
Note : When the burst refresh method is used, a total of 4,096 Auto-refresh commands within 2 ms must be asserted
after the Self-refresh Exit.
17
MB81ES123245-10
18. MODE REGISTER SET (MRS)
The mode register of MB81ES123245 provides a variety of different operations. The register consists of five
operation fields : Burst Length, Burst Type, CAS Latency, Operation Code and Page Length. Refer to “■MODE
REGISTER TABLE”. The mode register can be programmed by the Mode Register Set command (MRS) . Once
a mode register is programmed, the contents of the register will be held until re-programmed by another MRS
command. MRS command should only be issued on condition that all DQ is in High-Z. The condition of the mode
register is undefined after the power-up stage. Set each field after initialization of this device. Refer to “22.
POWER-UP INITIALIZATION”.
19. EXTENDED MODE REGISTER SET (EMRS)
The extended mode register consists of two operation fields : Partial Array Self Refresh (PASR) and Driver
Strength (DS) . Refer to “■MODE REGISTER TABLE”. The state of the extended mode register is undefined
after the Power-up stage. Set each field after initialization. Refer to “22. POWER-UP INITIALIZATION”.
20. PARTIAL ARRAY SELF-REFRESH (PASR)
Partial Array Self-Refresh is a function that limits the memory array size to be refreshed during self-refresh in
order to reduce the self-refresh current. Data outside the defined area will not be retained.
21. DRIVER STRENGTH (DS)
This function is to adjust the driver strength of the data output.
22. POWER-UP INITIALIZATION
The state of MB81ES123245 internal conditions after power-up will be undefined. Follow the following Power
On Sequence to execute read or write operation.
1. Apply power (VDD should be applied before or in parallel with VDDQ) and start clock. Attempt to maintain either
NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 300 µs.
3. Precharge all banks by single bank precharge command (PRE) or all banks precharge command (PALL) .
4. Assert minimum of 2 Auto-refresh commands (REF) .
5. Program the mode register by Mode Register Set command (MRS) .
6. Program the extended mode register by Extended Mode Register Set command (EMRS) .
In addition, it is recommended DQM and CKE track VDD to insure that output is High-Z state. The Mode Register
Set command (MRS) and Extended Mode Register Set command (EMRS) can also be set before 2 Auto-refresh
commands (REF) .
23. AUTOMATIC TEMPERATURE COMPENSATED SELF-REFRESH (ATCSR)
The MB81ES123245 has an ATCSR feature for low-power self-refresh current at room temperature.
18
MB81ES123245-10
■ STATE DIAGRAM
MRS
MODE
REGISTER
SET
SELF
EMRS
CKE(DPDX)
REF
CKE\
(DPD)
CKE
CKE\
(PD)
AUTO
REFRESH
ACTV
EXTENDED
MODE
REGISTER
SET
SELF
REFRESH
SELFX
IDLE
DEEP
POWER
DOWN
POWER
DOWN
CKE\ (CSUS)
BANK
ACTIVE
SUSPEND
BANK
ACTIVE
CKE
BST
WRIT
WRITA
WRITE
CKE
CKE\ (CSUS)
WRITE
SUSPEND
POWER
ON
POWER
APPLIED
CKE
WRITE WITH
AUTO
PRECHARGE
CKE\ (CSUS)
READ
WRIT
WRITA
READA
WRITA
PRE
or
PALL
PRE or PALL
READ
READA
READ
PRE or PALL
WRITE
SUSPEND
READ
WRIT
CKE\ (CSUS)
BST
CKE
READ
SUSPEND
READA
READ WITH
AUTO
PRECHARGE
CKE\ (CSUS)
CKE
READ
SUSPEND
PRE
or
PALL
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
Automatic
Sequence
Note : CKE\ means CKE goes Low-level from High-level.
19
MB81ES123245-10
■ BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second command
(same
*4
*4
bank) MRS ACTV READ READA WRIT WRITA PRE PALL
First command
SELF
BST
MRS
tRSC
tRSC
⎯
⎯
⎯
⎯
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
⎯
⎯
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
⎯
⎯
1
READ
⎯
⎯
1
1
*5
1
*5
1
*4
1
*4
1
⎯
⎯
1
*1, *2
BL
+ tRP
BL
+ tRP
⎯
⎯
⎯
⎯
*4
BL
+ tRP
*4
BL
+ tRP
*2
BL
+ tRP
*2, *7
BL
+ tRP
⎯
⎯
⎯
tWR
tWR
1
1
*4
*4
tDPL
tDPL
⎯
⎯
1
WRITA
*2
BL−1
+ tDAL
BL−1
+ tDAL
⎯
⎯
⎯
⎯
*4
BL−1
+ tDAL
*4
BL−1
+ tDAL
*2
BL−1
+ tDAL
*2
BL−1
+ tDAL
⎯
PRE
*2, *3
tRP
tRP
⎯
⎯
⎯
⎯
1
*4
1
*2
tRP
*2, *6
tRP
1
PALL
*3
tRP
tRP
⎯
⎯
⎯
⎯
1
1
tRP
*6
tRP
1
REF
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
READA
WRIT
SELFX
⎯ : Illegal Command
*1 : If tRP (Min) < CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2 : Assume all banks are in Idle state.
*3 : Assume output is in High-Z state.
*4 : Assume tRAS (Min) is satisfied.
*5 : Assume no I/O conflict.
*6 : Assume after the last data have been appeared on DQ.
*7 : If tRP (Min) < (CL − 1) × tCK, minimum latency is a sum of (BL + CL − 1) × tCK.
20
REF
MB81ES123245-10
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second command
(other
*5,*6
*5
*5, *6
*5
bank) MRS ACTV READ READA WRIT WRITA PRE PALL
First command
MRS
tRSC
tRSC
2
⎯
⎯
⎯
⎯
7
7
7
7
tRSC
6
7
REF
SELF
BST
tRSC
tRSC
tRSC
*
tRAS
⎯
⎯
1
tRSC
7
ACTV
⎯
*
tRRD
*
1
*
1
*
1
*
1
*,*
1
READ
⎯
*2, *4
1
1
1
*10
1
*10
1
*6
1
*6
1
⎯
⎯
1
*1, *2
BL +
tRP
*2, *4
1
*6
1
*6
1
*6, *10
1
*6, *10
1
*6
1
*6
BL +
tRP
*2
BL +
tRP
*2, *9
BL +
tRP
⎯
⎯
*2, *4
1
1
1
1
1
*6
1
*6
⎯
⎯
1
WRITA
*2
BL−1
+ tDAL
*2, *4
1
*6
1
*6
1
*6
1
*6
1
*6
1
PRE
*2, *3
tRP
*2, *4
1
*7
1
*7
1
*7
1
*7
1
*6, *7
1
*7
1
*2
tRP
*2, *8
tRP
1
PALL
*3
tRP
tRP
⎯
⎯
⎯
⎯
1
1
tRP
*8
tRP
1
REF
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
tRC
tRC
⎯
⎯
⎯
⎯
tRC
tRC
tRC
tRC
tRC
READA
WRIT
SELFX
⎯ : Illegal Command
tDPL
*2
*2
*6
BL−1 BL−1 BL−1
+ tDAL + tDAL + tDAL
⎯
*1 : If tRP (Min) < CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2 : Assume bank of the object is in Idle state.
*3 : Assume output is in High-Z state.
*4 : tRRD (Min) of other bank (second command will be asserted) is satisfied.
*5 : Assume other bank is in active, read or write state.
*6 : Assume tRAS (Min) is satisfied.
*7 : Assume other banks are not in READA/WRITA state.
*8 : Assume after the last data have been appeared on DQ.
*9 : If tRP (Min) < (CL − 1) × tCK, minimum latency is a sum of (BL + CL − 1) × tCK.
*10 : Assume no I/O conflict.
21
MB81ES123245-10
■ MODE REGISTER TABLE
• MODE REGISTER SET
BA1 BA0 A13*5 A12*4 A11 A10
0
0
PL
0
A9
0
A8*3 A7*3
Opcode
0
A6
A5
0
CL
PAGE
LENGTH
A6
A5
A4 CAS Latency
0
0
0
Reserved
GND GND
256 page
0
0
1
GND
1
128 page
0
1
1
0
64 page
0
1
1
Reserved
A13
A12
A3
A2
BT
A1
A0
ADDRESS
MODE
REGISTER
BL
A2
A1
A0
Reserved
0
0
0
2
0
1
1
3
1
0
0
1
0
1
1
1
1
1
Burst Length
BT = 0
BT = 1*2
0
1
Reserved
0
1
2
2
0
1
0
4
4
Reserved
0
1
1
8
8
Reserved
1
0
0
Reserved
Reserved
0
Reserved
1
0
1
Reserved
Reserved
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full
Column
Reserved
A9
Operation Code
0
Burst Read & Burst Write
1
A4
Burst Read & Single Write
A3
Burst Type
0
Sequential (Wrap round, Binary-up)
1
Interleave (Wrap round, Binary-up)
*1
• EXTENDED MODE REGISTER
BA1 BA0 A13*5 A12*4 A11
1
0
0
0
0
A10
A9
A8
A7
0
0
0
0
A6
A5
DS
A4
A3
0
0
A2
A1
A0
EXTENDED MODE
REGISTER
PASR
A6
A5
Driver Strength
A2
A1
A0
SELF REFRESH AREA
0
0
100% (Normal)
0
0
0
128 M bit
0
1
64 M bit (BA1 = 0)
0
1
70%
0
1
0
60%
0
1
0
Reserved
1
1
30%
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
*1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 are reserved for vendor test.
*4. A12 should be connected to GND at 256 page length mode.
*5. A13 should be connected to GND at 128 and 256 page length mode.
22
ADDRESS
MB81ES123245-10
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage*
Input/Output Voltage*
Short Circuit Output Current
Power Dissipation
Storage Temperature
VDD, VDDQ
VIN, VOUT
IOUT
PD
TSTG
Rating
Min
− 0.5
− 0.5
− 50
⎯
− 55
Max
+ 2.6
+ 2.6
+ 50
1.0
+ 125
Unit
V
V
mA
W
°C
* : All voltages are referenced to VSS.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
VIL
Tj
Supply Voltage
Input High Voltage *1
Input Low Voltage *2
Junction Temperature *3
2.6 V
VIH
50% of pulse amplitude
VIH
VIH Min
VIL
Min
1.7
0
VDDQ × 0.8
− 0.3
− 25
Pulse width ≤ 5 ns
*1 : Overshoot limit :
VIH (Max) = 2.6 V for pulse width ≤ 5 ns,
pulse width measured at 50% of pulse amplitude.
VIL Max
VIL
Value
Typ
1.8
0
⎯
⎯
⎯
Max
1.9
0
VDDQ + 0.3
VDDQ × 0.2
+ 95
Unit
V
V
V
V
°C
Pulse width ≤ 5 ns
50% of pulse amplitude
−1.0 V
*2 : Undershoot limit :
VIL (Min) = VSSQ − 1.0 V for pulse width ≤ 5 ns,
pulse width measured at 50% of pulse amplitude.
*3 : The maximum junction temperature of FCRAM (Tj) should not be more than +95 °C.
Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI (PD) , the thermal resistance
of the package (θ ja) , and the maximum ambient temperature of the SiP (Tamax) .
Σ pmax[W] = PFCRAM + PD
Tjmax[ °C] = Tamax[ °C] + θ ja[ °C/W] × Σ pmax[W]
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
23
MB81ES123245-10
■ CAPACITANCE
(Ta = +25 °C, f = 1 MHz)
Parameter
24
Symbol
Min
Typ
Max
Unit
Input Capacitance, Except for CLK
CIN1
1.5
⎯
3.0
pF
Input Capacitance for CLK
CIN2
1.5
⎯
3.0
pF
I/O Capacitance
CI/O
2.0
⎯
4.0
pF
MB81ES123245-10
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
Value
Condition
Min
Max
Unit
Output High Voltage
VOH (DC) IOH = −0.1 mA
VDDQ − 0.2
⎯
V
Output Low Voltage
VOL (DC) IOL = 0.1 mA
⎯
0.2
V
Input Leakage
Current
ILI
0 V ≤ VIN ≤ VDDQ,
All other pins not under test = 0 V
−5
+5
µA
Output Leakage
Current
ILO
0 V ≤ VIN ≤ VDDQ,
Data out disabled
−5
+5
µA
256 page length
⎯
60
IDD1
Burst Length = 1,
tRC = Min, tCK = Min,
One bank active,
Output pin open,
Address changed up to 1 time
during tRC (Min) ,
0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDD
128 page length
⎯
45
64 page length
⎯
35
Operating Current
(Average Power
Supply Current)
Precharge Standby
Current
(Power Supply
Current)
mA
IDD2P
CKE = VIL, All banks idle, tCK = Min,
Power down mode,
0 V ≤ VIN ≤ VIL (Max) , VIH (Min) ≤ VIN ≤ VDD
⎯
0.8
mA
IDD2PS
CKE = VIL, All banks idle, CLK = VIH or VIL,
Power down mode, 0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDD
⎯
0.5
mA
IDD2N
CKE = VIH, All banks idle, tCK = 20 ns,
NOP commands only,
Input signals (except for commands) are changed
1 time during 2 clocks, 0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDD
⎯
10
mA
IDD2NS
CKE = VIH, All banks idle, CLK = VIH or VIL,
Input signals are stable, 0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDD
⎯
1
mA
⎯
40
Burst mode Current
(Average Power
Supply Current)
IDD4
Refresh Current#1
(Average Power
Supply Current)
IDD5
tCK = Min, Burst Length = 4,
Output pin open,
All-banks active,
Gapless data,
0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDD
CL = 2
mA
CL = 3
Auto-refresh, tCK = Min, tRC = Min,
0 V ≤ VIN ≤ VIL (Max) , VIH (Min) ≤ VIN ≤ VDD
⎯
70
⎯
150
mA
(Continued)
25
MB81ES123245-10
(Continued)
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Refresh Current #2
(Average Power
Supply Current)
Symbol
IDD6
Precharge Standby
Current in Deep Power IDD7
Down mode
Value
Condition
Min
Max
Tj ≤ +35 °C
⎯
200
Tj ≤ +95 °C
⎯
800
CKE ≤ 0.2 V, All banks idle,
Deep Power Down mode,
0 V ≤ VIN ≤ VIL (Max) , VIH (Min) ≤ VIN ≤ VDD
⎯
15
Self-refresh (128M-bit) ,
tCK = Min, CKE ≤ 0.2 V,
0 V ≤ VIN ≤ VIL (Max) ,
VIH (Min) ≤ VIN ≤ VDDQ
Unit
µA
µA
*1 : All voltages are referenced to VSS.
*2 : DC characteristics are measured after following the “22. POWER-UP INITIALIZATION” procedure in section
“■FUNCTIONAL DESCRIPTION.”
*3 : IDD depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination resistor.
26
MB81ES123245-10
■ AC CHARACTERISTICS
1. BASIC AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3
Parameter
Symbol
Value
Min
Max
Unit
CL = 2
tCK2
18.5
⎯
ns
CL = 3
tCK3
9.2
⎯
ns
Clock High Pulse Width *5
tCH
3
⎯
ns
Clock Low Pulse Width *5
tCL
3
⎯
ns
tSI
2.5
⎯
ns
tHI
1
⎯
ns
CL = 2
tAC2
⎯
9
ns
CL = 3
tAC3
⎯
7
ns
tLZ
0
⎯
ns
CL = 2
tHZ2
2.5
9
ns
CL = 3
tHZ3
2.5
7
ns
tOH
2.5
⎯
ns
Time between Auto-Refresh Command Interval *
tREFI
⎯
15.6
µs
Time between Refresh
tREF
⎯
64
ms
Refresh Cycle Time
tREFC
82.8
⎯
ns
tT
0.5
10
ns
tCKSP
2.5
⎯
ns
Clock Period
Input Setup Time *
Input Hold Time *
5
5
Access Time from CLK
(tCK = Min) *5, *6, *7
CLK to Output in Low-Z Delay Time *
5
CLK to Output in High-Z Delay Time *5, *7, *8
Output Hold Time *4
9
Transition Time
CKE Setup Time for Power Down Exit *
5
*1 : AC characteristics are measured after following the “22. POWER-UP INITIALIZATION” procedure in section
“■FUNCTIONAL DESCRIPTION”.
*2 : AC characteristics assume tT = 1 ns, 50Ω of termination resistor. Refer to “5. MEASUREMENT CONDITION OF
AC CHARACTERISTICS”.
*3 : 0.9 V is the reference level for 1.8 V I/O for measuring timing of input/output signals. Transition times are
measured between VIH (Min) and VIL (Max) .
*4 : This value is for reference only.
*5 : If input signal transition time (tT) is longer than 1 ns : [ (tT/2) − 0.5] ns should be added to tAC (Max) , tHZ (Max) ,
and tCKSP (Min) spec values, [ (tT/2) − 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH (Min) spec
values, and (tT − 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values.
*6 : tAC also specifies the access time at burst mode.
*7 : tAC and tOH are measured under output load circuit shown in “5. MEASUREMENT CONDITION OF AC
CHARACTERISTICS”.
*8 : Specified where output buffer is no longer driven.
*9 : Auto refresh command is allowed to input maximum 32 times a tREFI (Max) period.
27
MB81ES123245-10
2. BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter
Symbol
Value
Min
Max
Unit
RAS Cycle Time *
tRC
82.8
⎯
ns
RAS Precharge Time
tRP
24
⎯
ns
RAS Active Time
tRAS
55.2
110000
ns
RAS to CAS Delay Time
tRCD
24
⎯
ns
Write Recovery Time
tWR
9.2
⎯
ns
RAS to RAS Bank Active Delay Time
tRRD
16
⎯
ns
Data-in to Precharge Lead Time
tDPL
18.4
⎯
ns
CL = 2
tDAL2
1 cyc + tRP
⎯
ns
CL = 3
tDAL3
2 cyc + tRP
⎯
ns
tRSC
16
⎯
ns
Data-in to Active/Refresh Command Period
Mode Register Set Cycle Time
* : Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP) .
3. CLOCK COUNT FORMULA
Base Value
Clock Period
Clock ≥
(Round up a whole number)
Note : All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by above formula.
4. LATENCY (The latency values on these parameters are fixed regardless of clock period.)
Parameter
Symbol
Value
Unit
CKE to Clock Disable
lCKE
1
cycle
DQM to Output in High-Z
lDQZ
2
cycle
DQM to Input Data Delay
lDQD
0
cycle
Last Output to Write Command Delay
lOWD
2
cycle
Write Command to Input Data Delay
lDWD
0
cycle
CL = 2
lROH2
2
cycle
CL = 3
lROH3
3
cycle
CL = 2
lBSH2
2
cycle
CL = 3
lBSH3
3
cycle
CAS to CAS Delay (Min)
lCCD
1
cycle
CAS Bank Delay (Min)
lCBD
1
cycle
Precharge to Output in High-Z Delay
Burst Stop Command to Output
in High-Z Delay
28
MB81ES123245-10
5. MEASUREMENT CONDITION OF AC CHARACTERISTICS
R = 50Ω
Output
VDD × 0.5
CL
6. SETUP, HOLD AND DELAY TIME
tCK
tCH
1.44 V
CLK
tCL
0.9 V
0.36 V
tSI
tHI
Iutput
(Control,
Address,
and Data)
1.44 V
0.9 V
0.36 V
tHZ
tAC
tLZ
Output
tOH
0.9 V
Note : Reference level of input signal is 0.9 V.
Access time is measured at 0.9 V.
AC characteristics are also measured in this condition.
29
MB81ES123245-10
7. DELAY TIME FOR POWER DOWN EXIT
CLK
H or L
tCKSP (Min)
1 clock (Min)
CKE
Command
H or L
NOP
NOP
ACTV
8. PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF, tREFC,
Input
(Control)
tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND
COMMAND
Note : These parameters are a limit value of the rising edge of the clock from one command input to next input.
tCKSP is the latency value from the rising edge of CKE.
Measurement reference voltage is 0.9 V.
30
MB81ES123245-10
9. ACCESS TIME
CLK
Command
READ
tAC
tAC
tAC
(CAS Latency − 1) × tCK
DQ31 to DQ0
(Output)
Q (Valid)
Q (Valid)
Q (Valid)
31
MB81ES123245-10
■ TIMING DIAGRAMS
1.
CLOCK ENABLE READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
ICKE
∗1
(1 clock)
lCKE
∗1
(1 clock)
CLK
(Internal)
DQ31 to DQ0
(Read)
Q1
DQ31 to DQ0
(Write)
D1
Q2
(NO CHANGE)
NOT ∗3
WRITTEN
∗2
D2
Q3
∗2
(NO CHANGE)
NOT ∗3
WRITTEN
Q4
D3
D4
*1 : The latency of CKE (lCKE) is one clock.
*2 : During read mode, the burst counter is not be incremented at the following clock of CSUS command.
The output data remain the same.
*3 : During write mode, the data at the following clock of CSUS command is ignored.
2. POWER DOWN ENTRY AND EXIT
CLK
tCKSP (Min)
1clock (Min)
CKE
Command
∗1
NOP
PD (NOP)∗2
H or L
PDX
NOP
∗3
ACTV
∗4
tREF (Max)
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2 : Precharge command can be posted in conjunction with CKE after the last read data have been appeared
on DQ.
*3 : It is recommended to apply NOP command in conjunction with CKE.
*4 : The ACTV command can be latched after tCKSP (Min) + 1 clock (Min) .
32
MB81ES123245-10
3.
COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
ICCD
(1 clock)
tRCD (Min)
ICCD
ICCD
ICCD
CAS
Address
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Note : CAS to CAS delay (lCCD) can be one or more clock period.
4. DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (Min)
RAS
ICBD
(1 clock)
tRCD (Min)
CAS
tRCD(Min)
Address
BA
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Note : CAS Bank delay (lCBD) can be one or more clock period.
33
MB81ES123245-10
5.
INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM3 to DQM0
(@ Read)
IDQZ (2 clocks)
DQ31 to DQ0
(@ Read)
Q1
High-Z
Q2
Q4
End of burst
DQM3 to DQM0
(@ Write)
IDQD (same clock)
DQ31 to DQ0
(@ Write)
D1
MASKED
D3
D4
6. PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (Min)
Command
ACTV
* : PRE means ’PRE’ or ’PALL’.
34
PRE∗
End of burst
MB81ES123245-10
7. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ BL = 4)
CLK
Command
PRE∗2
IROH (3 clocks) *1
High-Z
DQ31 to DQ0
Q1
Command
PRE∗2
Q2
IROH (3 clocks) *1
DQ31 to DQ0
High-Z
Q1
Q2
Q3
PRE∗2
Command
No effect (end of burst)
High-Z
DQ31 to DQ0
Q1
Q2
Q3
Q4
*1 : In case of CL = 3, the latency from the Precharge command (PRE) to output in High-Z (lROH) is 3 clocks.
*2 : PRE means ’PRE’ or ’PALL’.
35
MB81ES123245-10
8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 3, BL = Full Column)
CLK
Command
BST
IBSH (3 clocks)
DQ31 to DQ0
Qn − 2
Qn − 1
Qn + 1
Qn
9. WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
DQ31 to DQ0
36
WRIT
BST
LAST
DATA INPUT
Masked
by BST
Qn + 2
High-Z
MB81ES123245-10
10. WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3, BL = 4)
CLK
tDPL (Min)
Command
PRE*1, *2
WRIT
ACTV
tRP (Min)
DQ31 to DQ0
D1
D2
MASKED
by PRE
*1 : The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
*2 : PRE means “PRE” or “PALL”.
11. READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
IOWD (2 clocks)
Command
DQM3 to DQM0
READ
WRIT
∗1
∗2
∗3
IDQZ (2 clocks)
IDWD (same clock)
DQ31 to DQ0
Q1
Masked
D1
D2
*1 : First DQM makes High-Z state between last output and first input data.
*2 : Second DQM makes internal output data mask to avoid bus contention.
*3 : Third DQM also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
37
MB81ES123245-10
12. WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
tWR (Min)
WRIT
Command
READ
DQM3 to DQM0
(CL − 1) × tCK
DQ31 to DQ0
D1
D2
tAC (Max)
D3
Masked
by READ
Q1
Q2
Q3
Note : Read command should be issued after tWR of final data input is satisfied.
13. READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 3, BL = 2, Applied to same bank)
tRAS (Min)
CLK
tRP (Min)
Command
ACTV
READA∗1,∗2
NOP
ACTV
2 clocks *1
(same value as BL)
BL + tRP (Min)∗2
DQM3 to DQM0
DQ31 to DQ0
Q1
Q2
*1 : Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the
same as Burst Length (BL) after the READA command is asserted.
*2 : Next ACTV command should be issued after BL + tRP (Min) from READA command.
38
MB81ES123245-10
14. WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 3, BL = 2, Applied to same bank) *1, *2, *3
tRAS (Min)
CLK
2 clocks *4
tDAL (Min)
BL + 1 + tRP (Min) *5
Command
ACTV
WRITA
ACTV
NOP
DQM3 to DQM0
DQ31 to DQ0
D1
D2
*1 : Even if the final input data are masked by DQM, the precharge is started at same timing as the case final
data are not masked.
*2 : Once auto precharge command is asserted, no new command within the same bank can be issued.
*3 : Auto-precharge command doesn’t affect at full column burst operation except Burst Read & Single Write.
*4 : Precharge at write with Auto-precharge is started after 1 clock at CL = 2, 2 clocks at CL = 3 from the end of
burst.
*5 : Next command should be issued after BL + tRP (Min) at CL = 2, BL + 1 + tRP (Min) at CL = 3 from WRITA
command.
15. AUTO-REFRESH
CLK
Command
REF ∗1
NOP ∗3
REF
tREFC (Min)
BA
H or L ∗2
NOP ∗3
COMMAND ∗4
tREFC (Min)
H or L ∗2
BA
*1 : All banks should be precharged prior to the first Auto-refresh command (REF) .
*2 : Bank select is ignored at REF command. The refresh address and bank select are selected by internal
refresh counter.
*3 : Either NOP or DESL command should be asserted during tREFC period while Auto-refresh mode.
*4 : Any activation command such as ACTV or MRS command other than REF command should be asserted
after tREFC from the last REF command.
39
MB81ES123245-10
16. SELF-REFRESH ENTRY AND EXIT
CLK
tCKSP (Min)
tSI (Min)
CKE
∗5
tREFC (Min) *4
Command
H or L
NOP ∗1
SELF
H or L
NOP ∗2
SELFX
NOP ∗3
COMMAND
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry
command (SELF) .
*2 : The Self-refresh Exit command (SELFX) is latched after tCKSP (Min) . It is recommended to apply NOP
command on the rising edge of CKE.
*3 : Either NOP or DESL command can be asserted during tREFC period.
*4 : CKE should be held High during tREFC period after tCKSP.
*5 : CKE level should be held less than 0.2 V during self-refresh mode.
17. MODE REGISTER SET
CLK
tRSC (Min)
Command
MRS or
EMRS
Address
MODE
NOP
ACTV
ROW
ADDRESS
Note : The Mode Register Set command (MRS) or Extended Mode Register Set command (EMRS) should
only be asserted after all banks have been precharged.
40
MB81ES123245-10
18. DEEP POWER DOWN ENTRY
CLK
tSI (Min)
CKE
Command
H or L
NOP
DPD
H or L
Note : Deep Power Down Entry command (DPD) should only be asserted if all banks have been precharged
and all outputs are in High-Z.
19. DEEP POWER DOWN EXIT
CLK
tCKSP
(Min)
CKE
300 µs (Min)
Command
H or L
NOP DPDX
NOP
tRP
(Min)
tREFC (Min)
PALL REF
tREFC (Min)
REF
tRSC tRSC
(Min) (Min)
MRS EMRS ACTV
41
MB81ES123245-10
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
The company names and brand names herein are the trademarks or
registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0612