The CSC6502 provides eight inputs that can be routed to any of six outputs. Each input can be
routed to one or more outputs, but only one input may be routed to any output.
Each input supports an integrated clamp option to set the output sync tip level of video with
sync to ~300mV. Alternatively, the input may be internally biased to center output signals without
sync (Chroma, Pb, Pr) at ~1.25V. All outputs are designed to drive a 150Ω.DC-coupled load.
Each output can be programmed to provide either 0dB or 6dB of signal gain.
Input-to-output routing and input bias mode functions are controlled via an I2C-compatible
digital interface. CSC6502 is substitution of FMS6502
8 x 6 Crosspoint Switch Matrix
Supports SD, PS, and HD 1080i / 1080p Video
Input Clamp and Bias Circuitry
Doubly Terminated 75Ω Cable Drivers
Programmable 0dB or 6dB Gain
AC- or DC-Coupled Inputs
AC- or DC-Coupled Outputs
One-to-One or One-to-Many Input-to-Output Switching
I2CTM-Compatible Digital Interface, Standard Mode
3.3V or 5V Single Supply Operation
TSSOP-24 Package
Cable and Satellite Set-Top Boxes
TV and HDTV Sets
A / V Switchers
Personal Video Recorders (PVR)
Security and Surveillance
Video Distribution
Automotive (In-Cabin Entertainment)
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Block Diagram
Figure 1. Block Diagram
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not
function or be operable above the recommended operating conditions and stressing the parts to
these levels is not recommended. In addition, extended exposure to stresses above the
recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation.
Recommended operating conditions are specified to ensure optimal performance to the datasheet
specifications. does not recommend exceeding them or designing to Absolute Maximum Ratings.
Reliability Information
Electrostatic Discharge Information
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Digital Interface
The I2C-compatibe interface is used to program output enables, input-to-output routing, and
input bias configuration. The I2C address of the CSC6502 is 0x06 (00000110) with the ability to
offset based upon the values of the ADDR0 and ADDR1 inputs. Offset addresses are defined
Data and address data of eight bits each are written to the CSC6502 I2C address register to
access control functions.
For efficiency, a single data register is shared between two outputs for input selection. More
than one output can select the same input channel for one-to-many routing. The clamp / bias
control bits are written to their own internal address since they should remain the same regardless
of signal routing. They are set based on the input signal that is connected to the CSC6502.
All undefined addresses may be written without effect.
Output Control Register Contents and Defaults
Output Control Register MAP
Clamp Control Register Contents and Defaults
Clamp Control Register Map
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Gain Control Register Contents and Defaults
Gain Control Register Map
1. When the OFF input selection is used, the output amplifier is powered down and enters a
high-impedance state.
DC Electrical Characteristics
TA = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs
AC-coupled with 0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs
AC-coupled with 220µF into 150Ω, referenced to 400kHz unless otherwise noted.
1. 100% tested at 25°C.
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AC Electrical Characteristics
TA = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs
AC-coupled with 0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs
AC-coupled with 220µF into 150Ω, referenced to 400kHz unless otherwise noted.
1. 100% tested at 25°C.
2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch.
3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch.
4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output.
5. SNR = 20 * log (714mV / rms noise).
I2C BUS Characteristics
TA = 25°C, Vcc = 5V unless otherwise noted.
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1. 100% tested at 25°C.
Figure 3. I2C Bus Timing
I2C Interface
The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual
addresses may be written, but there is no read capability. The interface consists of two lines: a
serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive
supply through an external resistor. Data transfer may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line during this time are
interpreted as control signals.
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Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition
of the data line, while the clock is HIGH, is defined as start condition (S). A LOW-to-HIGH
transition of the data line, while the clock is HIGH, is defined as stop condition (P).
Figure 5. START and STOP conditions
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge
bit is a HIGH level signal put on the bus by the transmitter while the master generates an extra
acknowledge-related clock pulse. The slave receiver addressed must generate an acknowledge
after the reception of each byte. A master receiver must generate an acknowledge after the
reception of each byte clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so the SDA line is stable LOW during the HIGH period of the acknowledge- related clock
pulse (set-up and hold times must be taken into consideration). A master receiver must signal an
end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate
a stop condition.
Figure 6. Acknowledgement on the I2C Bus
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I2C Bus Protocol
Before any data is transmitted on the I2C bus, the device which is to respond is addressed first.
The addressing is always carried out with the first byte transmitted after the start procedure. The
I2C bus configuration for a data write to the CSC6502 is shown in Figure 7.
Figure 7. Write Register Address to Pointer Register;
Write Data to Selected Register
3.3V Operation
The CSC6502 operates from a single 3.3V supply. With Vcc = 3.3V, the digital input low (Vil) is
0V to 1V and the digital input high (Vih) is 1.8V to 2.9V.
Applications Information
Input Clamp / Bias Circuitry
The CSC6502 can accommodate AC- or DC-coupled inputs. Internal clamping and bias
circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits
via the I2C -compatible interface. For DC-coupled inputs, the device should be programmed to use
the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through
a 100kΩ resistor. Distortion is optimized with the output levels set between 250mV above ground
and 500mV below the power supply.
With AC-coupled inputs, the CSC6502 uses a simple clamp rather than a full DC-restore circuit.
For video signals with and without sync; (Y,CV,R,G,B), the lowest voltage at the output pins is
clamped to approximately 300mV above ground.
If symmetric AC-coupled input signals are used (Chroma,Pb,Pr,Cb,Cr), the bias circuit can be
used to center them within the input common range. The average DC value at the output is
approximately 1.27V. Figure 8 shows the clamp mode input circuit and the internally controlled
voltage at the input pin for AC-coupled inputs.
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Figure 8. Clamp Mode Input Circuit
Figure 9 shows the bias mode input circuit and the internally controlled voltage at the input pin for
AC-coupled inputs.
Figure 9. Bias Mode Input Circuit
Output Configuration
The CSC6502 outputs may be AC or DC-coupled. DC-coupled loads can drive a 150Ω load.
AC-coupled outputs are capable of driving a single, doubly terminated video load of 150Ω. An
external transistor is needed to drive DC low-impedance loads. DC-coupled outputs should be
connected as indicated in Figure 10.
Figure 10. DC-Coupled Load Connection
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Configure AC-coupled loads as shown in Figure 11.
Figure 11. AC-Coupled Load Connection
When an output channel is not connected to an input, the input to that particular channel’s
amplifier is forced to approximately 150mV. The output amplifier is still active unless specifically
disabled by the I2C interface. Voltage output levels depend on the programmed gain for that
Driving Capacitive Loads
When driving capacitive loads, use a 10Ω-series resistance to buffer the output, as indicated in
Figure 12.
Figure 12. Driving Capacitive Loads
Crosstalk is an important consideration when using the CSC6502. Input and output crosstalk
represent the two major coupling modes that may be present in a typical application. Input
crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open
switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It
decreases rapidly as the interfering signal moves further away from the pin adjacent to the input
signal selected. Output crosstalk is coupling from one driven output to another active output. It
decreases with increasing load impedance as it is caused mainly by ground and power coupling
between output amplifiers. If a signal is driving an open switch, its crosstalk is mainly input
crosstalk. If it is driving a load through an active output, its crosstalk is mainly output crosstalk.
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Input and output crosstalk measurements are performed with the test configuration shown in
Figure 13.
Figure 13. Test Configuration for Crosstalk
For input crosstalk, the switch is open and all inputs are in bias mode. Channel 1 input is driven
with a 1Vpp signal, while all other inputs are AC terminated with 75Ω. All outputs are enabled and
crosstalk is measured from IN1 to any output.
For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured.
Crosstalk from multiple sources into a given channel is measured with the setup shown in
Figure 14. Input In1 is driven with a 1Vpp pulse source and connected to outputs Out1 to Out8.
Input In9 is driven with a secondary, asynchronous gray field video signal and is connected to
Out9. All other inputs are AC terminated with 75Ω. Crosstalk effects on the gray field are
measured and calculated with respect to a standard 1Vpp output measured at the load.
If not all inputs and outputs are needed, avoid using adjacent channels to reduce crosstalk.
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Figure 14. Test Configuration for Multi-Channel Crosstalk
Layout Considerations
General layout and supply bypassing play a major role in high-frequency performance and
thermal characteristics. offers a demonstration board to guide layout and aid device evaluation.
The demo board is a four-layer board with full power and ground planes. Following this layout
configuration provides optimum performance and thermal characteristics for the device. For the
best results, follow the steps and recommended routing rules listed below.
Recommended Routing/Layout Rules
• Do not run analog and digital signals in parallel.
• Use separate analog and digital power planes to supply power.
• Traces should run on top of the ground plane at all times.
• No trace should run over ground/power splits.
• Avoid routing at 90-degree angles.
• Minimize clock and video data trace length differences.
• Include 10µF and 0.1µF ceramic power supply bypass capacitors.
• Place the 0.1µF capacitor within 0.1 inches of the device power pin.
• Place the 10µF capacitor within 0.75 inches of the device power pin.
• For multilayer boards, use a large ground plane to help dissipate heat.
• For two-layer boards, use a ground plane that extends beyond the device body by at least 0.5
inches on all sides. Include a metal paddle under the device on the top layer.
• Minimize all trace lengths to reduce series inductance.
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Thermal Considerations
Since the interior of most systems, such as set-top boxes, TVs, and DVD players, are at
+70ºC; consideration must be given to providing an adequate heat sink for the device package for
maximum heat dissipation. When designing a system board, determine how much power each
device dissipates. Ensure that devices of high power are not placed in the same location, such as
directly above (top plane) or below (bottom plane) each other on the PCB.
Power Dissipation
Worst-case, additional die power due to DC loading can be estimated at Vcc 2/4Rload per output
channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual DC video
load, add 25/(4*75) = 83mW, per channel.
PCB Thermal Layout Considerations
• Understand the system power requirements and environmental conditions.
• Maximize thermal performance of the PCB.
• Consider using 70µm of copper for high-power designs.
• Make the PCB as thin as possible by reducing FR4 thickness.
• Use vias in power pad to tie adjacent layers together.
• Remember that baseline temperature is a function of board area, not copper thickness.
• Modeling techniques can provide a first-order approximation.
Applications for the CSC6502 Video Switch Matrix
The increased demand for consumer multimedia systems has created a large challenge for
system designers to provide cost-effective solutions to capitalize on the growth potential in
graphics display technologies. These applications require cost-effective video switching and
filtering solutions to deploy high-quality display technologies rapidly and effectively to the target
audience. Areas of specific interest include HDTV, media centers, and automotive infotainment
(such as navigation, in-cabin entertainment, and back-up cameras). In all cases, the advantages the
integrated video switch matrix provides are high-quality video switching specific to the
application, as well as video input clamps and on-chip, low-impedance output cable drivers with
switchable gain.
Generally the largest application for a video switch is for the front-end of an HDTV. This is
used to take multiple inputs and route them to their appropriate signal paths
(main picture and picture-in-picture, or PiP). These are normally routed into ADCs that are
followed by decoders. Technologies for HDTV include LCD, plasma, and CRT, which have
similar analog switching circuitry.
VIPDEMOTM Control Software
The CSC6502 is configured via an I2C-compatible digital interface. To facilitate demonstration,
Semiconductor had developed the VIPDEMOTM GUI-based control software to write to the
CSC6502 register map. This software is included in the CSC6502DEMO kit. A parallel port I2C
adapter and an interface cable to connect to the demo board are also included. Besides using the
full CSC6502 interface, the VIPDEMOTM can also be used to control single register read and
writes for I2C.
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