a FEATURES Monolithic (BiMOS ll) Tracking R/D Converter Ratiometric Conversion Low Power Consumption: 300 mW Typ Dynamic Performance Set by User Velocity Output ESD Class 2 Protection (2,000 V Min) AD2S81A 28-Lead DIP Package Low Cost AD2S82A 44-Lead PLCC Package 10-, 12-, 14- and 16-Bit Resolution Set by User High Max Tracking Rate 1040 RPS (10 Bits) VCO Output (Inter LSB Output) Data Complement Facility Industrial Temperature Range APPLICATIONS DC Brushless and AC Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control GENERAL DESCRIPTION The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 44-lead J leaded PLCC package. Two extra functions are provided in the new surface mount package–COMPLEMENT and VCO output. The AD2S81A is a monolithic 12-bit fixed resolution tracking resolver-to-digital converter packaged in a 28-lead DIP. The converters allow users to select their own dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The AD2S82A allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S81A and AD2S82A convert resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver. The output word is in a three-state digital logic form available in two bytes on the 16 output data lines for the AD2S82A and on eight output data lines for the AD2S81A. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A AD2S82A FUNCTIONAL BLOCK DIAGRAM DEMOD DEMOD INTEGRATOR I/P O/P I/P AD2S82A SIN I/P SIGNAL GND COS I/P ANALOG GND RIPPLE CLK +12V –12V COMP DATA LOAD A1 SEGMENT SWITCHING PHASE SENSITIVE DETECTOR R-2R DAC A2 INTEGRATOR O/P A3 VCO DATA TRANSFER LOGIC 16-BIT UP/DOWN COUNTER AC ERROR O/P VCO I/P INHIBIT VCO O/P +5V OUTPUT DATA LATCH SC2 SC1 ENABLE 16 DATA BITS DIGITAL GND BUSY DIR BYTE SELECT An analog signal proportional to velocity is also available and can be used to replace a tachogenerator. PRODUCT HIGHLIGHTS Monolithic. A one-chip solution reduces the package size required and increases the reliability. Resolution Set by User. Two control pins are used to select the resolution of the AD2S82A to be 10, 12, 14 or 16 bits allowing the user to use the AD2S82A with the optimum resolution for each application. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost, preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. Low Power Consumption. Typically only 300 mW. MODELS AVAILABLE Information on the models available is given in the Ordering Guide. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD2S81A/AD2S82A–SPECIFICATIONS (@ T = +25ⴗC, unless otherwise noted) A Parameter Conditions SIGNAL INPUTS Frequency Voltage Level Input Bias Current Input Impedance Maximum Voltage Bandwidth1 AD2S81A Typ Max 400 1.8 2.0 60 1.0 REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance CONTROL DYNAMICS Repeatability Allowable Phase Shift Tracking Rate Min ±8 400 1.0 60 (Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable DIGITAL POSITION Resolution Output Format Load 1.0 20,000 2.2 150 ±8 50 1.0 1 +10 1040 260 65 16.25 LSB Degrees rps rps rps rps ⴞ22 + 1 LSB ⴞ8 + 1 LSB ⴞ4 + 1 LSB ⴞ2 + 1 LSB arc min arc min arc min arc min 4 1 Codes Code ⴞ3 ±2 6 ⴞ10 ± 10.5 1.5 1.0 % FSD % FSD mV µV/°C % FSD V % rms O/P kΩ ± 10.4 V mA 3 3 LSTTL 600 600 ns 60 –10 ⴞ30 + 1 LSB ±1 ±8 ±9 ± 5.6 ±8 ±8 Hz V rms nA MΩ V pk Hz V pk nA MΩ 260 –22 Overvoltage Protection Short Circuit O/P Protection 2.0 60 Units 20,000 8.0 150 1 +10 –10 Over Full Range 1 mA Load Mean Value 50 1.8 AD2S82A Typ Max 1.0 H J K L Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) J, K L INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs 20,000 8.0 150 1.0 ACCURACY Angular Accuracy VELOCITY SIGNAL Linearity Reversion Error DC Zero Offset2 DC Zero Offset Tempco Gain Scaling Accuracy Output Voltage Dynamic Ripple Output Load 20,000 2.2 150 Min ±1 ⴞ3 ±2 6 ⴞ10 ± 10.5 1.5 1.0 ± 10.4 –22 ±8 ±9 ± 5.6 ±8 ±8 10, 12, 14 and 16 Bidirectional Natural Binary 3 INHIBIT Sense Time to Stable Data ENABLE3 Logic LO to Inhibit Logic LO Enables Position Output. Logic HI Outputs in High Impedance State ENABLE/Disable Time BYTE SELECT3 Sense Logic HI Logic LO SC1 0 0 1 1 SC2 0 1 0 1 DATA LOAD4, 5 Sense 110 35 110 ns 60 140 60 140 ns 300 ns MS Byte DB1–DB8, (LS Byte DB9–DB16)4 LS Byte DB1–DB8, (LS Byte DB9–DB16)4 Time to Data Available SHORT CYCLE INPUTS4, 5 35 Internally Pulled High (100 kΩ) to +VS 10 Bit 12 Bit 14 Bit 16 Bit Internally Pulled High (100 kΩ) to +VS; Logic LO Allows Data to Be Loaded into the Counters from the Data Lines 150 –2– REV. B AD2S81A/AD2S82A Parameter COMPLEMENT Conditions 4, 5 BUSY3 Sense Width Load DIRECTION3 Sense Min AD2S81A Typ Max Width Reset Load DIGITAL INPUTS High Voltage, VIH Low Voltage, VIL DIGITAL INPUTS High Current, IIH Low Current, IIL DIGITAL INPUTS Low Voltage, VIL Low Current, IIL DIGITAL OUTPUTS High Voltage, VOH Low Voltage, VOL THREE-STATE LEAKAGE Current IL POWER SUPPLIES Voltage Levels +VS –VS +VL Current +IS +IS +IL AD2S82A Typ Max Logic HI When Position O/P Changing 200 600 1 Use Additional Pull-Up 200 600 1 ns LSTTL 3 LSTTL 3 LSTTL Logic HI Counting Up Logic LO Counting Down 3 Logic HI, All 1s to All 0s All 0s to All 1s Dependent On Input Velocity Before Next Busy 300 300 3 INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 10.8 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.0 V 2.0 2.0 V 0.8 0.8 V INHIBIT, ENABLE DB1–DB16 ± VS = ± 13.2 V, VL = 5.5 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.5 V ⴞ100 ⴞ100 µA ⴞ100 ⴞ100 µA ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V 1.0 1.0 V –400 –400 µA DB1–DB16; RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1–DB16, RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA 2.4 2.4 DB1–DB16 Only +VS = ± 12.0 V, VL = 5.5 V VOL = 0 V +VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V +10.8 –10.8 +5 ± VS @ ± 12 V ± VS @ ± 13.2 V ± VL @ ± 5.0 V 0.4 0.4 V ± 100 ± 100 µA ± 100 ± 100 µA +13.2 –13.2 +13.2 V V V ⴞ23 ⴞ30 ⴞ1.5 mA mA mA +13.2 –13.2 +13.2 ⴞ12 ⴞ19 ⴞ0.5 V ⴞ23 ⴞ30 ⴞ1.5 +10.8 –10.8 +5 ⴞ12 ⴞ19 ⴞ0.5 NOTES 1 Refers to small signal bandwidth. 2 Output offset dependent on value for R6. 3 Refer to timing diagram. 4 AD2S82A only. 5 These pins are referenced to +V S (i.e., HI = +12 V, LO = 0 V). Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. REV. B Units Internally Pulled High (100 kΩ) to +VS; Logic LO to Activate; No Connect for Normal Operation Max Load RIPPLE CLOCK3 Sense Min –3– AD2S81A/AD2S82A–SPECIFICATIONS (typical @ +25ⴗC unless otherwise noted) Parameter RATIO MULTIPLIER AC Error Output Scaling PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Increase Decrease Conditions Min AD2S81A Typ Max 10 Bit 12 Bit 14 Bit 16 Bit 44.4 12 w.r.t. REF w.r.t. REF –0.882 –0.9 60 1 At 10 kHz ± VS = ± 10.8 V dc –0.918 0.04 150 ±8 57 63 ±7 100 1 60 5 150 1.1 7.9 7.9 8.7 8.7 AD2S82A Typ Max Units 177.6 44.4 11.1 2.775 mV/Bit mV/Bit mV/Bit mV/Bit 12 mV –0.882 –0.9 60 1 –0.918 0.04 150 ±8 57 63 100 1 60 5 150 1.1 7.9 7.9 8.7 8.7 V rms/V dc V rms/V dc nA MΩ V dB nA/LSB mV nA V ± VS = ± 12 V dc Positive DIR Negative DIR 1.0 7.1 7.1 +VS –VS +VS –VS +0.5 –8.0 –8.0 +2.0 1 70 –1.22 Input Offset Voltage Input Bias Current Input Bias Current Tempco Input Voltage Range Linearity of Absolute Rate Full Range Over 0% to 50% of Full Range Reversion Error Sensitivity of Reversion Error to Symmetry of Power Supplies VCO Output1, 2 POWER SUPPLIES Voltage Levels +VS –VS +VL Current +IS +IS +IL Min ±8 1.0 7.1 7.1 +0.5 –8.0 –8.0 +2.0 1 70 –1.22 5 380 ±8 <2 <1 1.5 ±8 ± 2.7 +10.8 –10.8 +5 +13.2 –13.2 +13.2 ± VS @ ± 12 V ± VS @ ± 13.2 V ± VL @ ± 5.0 V ⴞ12 ⴞ19 ⴞ0.5 +10.8 –10.8 +5 ⴞ23 ⴞ30 ⴞ1.5 NOTES 1 The VCO output swings between ±3 V depending on the resolver direction. 2 AD2S82A only. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. AD2S81AJD AD2S82AHP AD2S82AJP AD2S82AKP AD2S82ALP ± 3.0 ⴞ12 ⴞ19 ⴞ0.5 MHz kHz/µA kHz/µA %/V %/V %/V %/V mV nA nA/°C V 5 380 ±8 <2 <1 1.5 ± 3.3 % FSD % FSD % FSD %/V of Asymmetry V/LSB +13.2 –13.2 +13.2 V V V ⴞ23 ⴞ30 ⴞ1.5 mA mA mA ORDERING GUIDE Operating Temperature Accuracy Ranges Package Options* 30 arc min 22 arc min 8 arc min 4 arc min 2 arc min D-28 P-44A P-44A P-44A P-44A 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C *D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package. ESD SENSITIVITY The AD2S81A and AD2S82A features an input protection circuit consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model) and fast, low energy pulses (Charges Device Model). WARNING! The AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual. –4– ESD SENSITIVE DEVICE REV. B AD2S81A/AD2S82A RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS 1 (with respect to GND) Power Supply Voltage (+VS to –VS) . . . . . . . . . ± 12 V dc ± 10% Power Supply Voltage VL . . . . . . . . . . . . . . . . . . +5 V dc ± 10% Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10% Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Signal and Reference Harmonic Distortion . . . . . . . 10% (max) Phase Shift Between Signal and Reference . ± 10 Degrees (max) Ambient Operating Temperature Range Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial (HP, JP, KP, LP) . . . . . . . . . . . . –40°C to +85°C +VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc +VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW Operating Temperature Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial (HP, JP, KP, LP) . . . . . . . . . . . . . –40°C to +85°C Storage Temperature (All Grades) . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C PIN FUNCTION DESCRIPTIONS Mnemonic REFERENCE I/P DEMOD I/P AC ERROR O/P COS I/P ANALOG GND SIGNAL GND SIN I/P +VS DB1–DB16 +VL ENABLE Description Reference Signal Input Demodulator Input Ratio Multiplier Output Cosine Input Power Ground Resolver Signal Ground Sine Input Positive Power Supply Parallel Output Data Logic Power Supply Logic Hi-Output Data in High Impedance State Logic Lo Present Data to the Output Latches BYTE SELECT Logic Hi-Most Significant Byte to DB1–DB8 Logic Lo-Most Significant Byte to DB1–DB8 INHIBIT Logic Lo Inhibits Data Transfer to Output Latches DIGITAL GND Digital Ground SC1–SC2* Select Converter Resolution DATA LOAD* Logic Lo DB1–DB16 Inputs Logic Hi DB1–DB16 Outputs BUSY Converter Busy, Data Not Valid While Busy Hi DIR Logic State Defines Direction of Input Signal Rotation RIPPLE CLK Positive Pulse when Converter Output Changes from 1s to All 0s or Vice Versa –VS Negative Power Supply VCO I/P VCO Input INTEGRATOR I/P Integrator Input INTEGRATOR O/P Integrator Output DEMOD O/P Demodulator Output COMPLEMENT* Active Logic Lo VCO O/P* VCO Output CAUTION 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. 2. Correct polarity voltages must be maintained on the +V S and –V S pins. AD2S81A/AD2S82A PIN CONFIGURATIONS REFERENCE I/P 1 28 DEMOD I/P 2 27 INTEGRATOR O/P AC ERROR O/P 3 26 INTEGRATOR I/P COS I/P 4 25 VCO I/P ANALOG GND 5 24 –VS SIN I/P 6 23 RIPPLE CLK +VS 7 DB2 0.3515625 0.1757813 0.0878906 0.0439453 0.0219727 21.09375 10.546875 5.273438 2.636719 1.318359 1265.625 632.8125 316.40625 158.20313 79.10156 15 16 17 18 32768 65536 131072 262144 0.0109836 0.0054932 0.0027466 0.0013733 0.659180 0.329590 0.164795 0.082397 39.55078 19.77539 9.88770 4.94385 REV. B ENABLE 16 +VL DB7 14 15 DB8 LSB 6 2 1 44 43 42 41 40 5 4 3 VCO I/P REFERENCE I/P DEMOD O/P INTEGRATOR I/P VCO O/P DEMOD I/P INTEGRATOR O/P 17 DB6 13 DIGITAL GND PIN 1 IDENTIFIER DB2 DB3 DB4 DB5 RIPPLE CLK DIR 36 BUSY 11 AD2S82A 35 12 TOP VIEW (Not to Scale) 34 13 DATA LOAD COMPLEMENT SC2 32 SC1 33 14 31 DIGITAL GND 30 INHIBIT NC 29 18 19 20 21 22 23 24 25 26 27 28 NC = NO CONNECT –VS 37 DB6 15 DB7 16 DB8 17 –5– 39 38 +VS 8 NC 9 MSB DB1 10 ENABLE BYTE SELECT 1024 2048 4096 8192 116384 DB5 12 SIN O/P 7 40500.0 20250.0 10125.0 5062.5 2531.25 10 11 12 13 14 BYTE SELECT LSB DB16 +VL 675.0 337.5 168.75 84.375 42.1875 18 DB14 DB15 11.25 5.625 2.8125 1.40625 0.703125 1296000.0 648000.0 324000.0 162000.0 81000.0 INHIBIT DB4 11 DB12 32 64 128 256 512 21600.0 10800.0 5400.0 2700.0 1350.0 19 DB13 5 6 7 8 9 360.0 180.0 90.0 45.0 22.5 DB9 1 2 4 8 16 Seconds /Bit 20 DB10 DB11 0 1 2 3 4 Minutes /Bit 9 DB3 10 SIGNAL GND ANALOG GND COS I/P AC ERROR O/P Bit Weight Table Resolution Degrees (2N) /Bit AD2S81A TOP VIEW 22 DIR 8 (Not to Scale) 21 BUSY MSB DB1 *AD2S82A Only. Binary Bits (N) DEMOD O/P AD2S81A/AD2S82A CONNECTING THE CONVERTER in Figure 7 and described in the Connecting the Resolver section. The power supply voltages connected to +VS and –VS pins should be +12 V dc and –12 V dc and must not be reversed. The voltage applied to VL can be +5 V dc to +VS. The two signal ground wires from the resolver should be joined at the SIGNAL GROUND pin of the resolver to minimize the coupling between the sine and cosine signals. For this reason it is also recommended that the resolver is connected using individually screened twisted pair cables with the sine, cosine and reference signals twisted separately. It is recommended that the decoupling capacitors are connected in parallel between the power lines +VS, –VS and ANALOG GND adjacent to the converter. Recommended values are 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and 10 µF should be connected between +VL and DIGITAL GND adjacent to the converter. SIGNAL GND and ANALOG GND are connected internally. ANALOG GND and DIGITAL GND must be connected externally. When more than one converter is used on a card, then separate decoupling capacitors should be used for each converter. The external components required should be connected as shown in Figures 1a and 1b. The resolver connections should be made to the SIN and COS inputs, REFERENCE I/P and SIGNAL GND as shown REFERENCE I/P OFFSET ADJUST R9 –12V +12V C3 HP FILTER R3 C1 R8 R2 BANDWIDTH SELECTION C2 R4 R1 DEMOD I/P AC ERROR O/P SIN I/P SIGNAL GND A1 COS I/P ANALOG GND A2 SEGMENT SWITCHING R-2R DAC DEMOD O/P INTEGRATOR I/P AD2S82A RIPPLE CLK +12V –12V VELOCITY SIGNAL R6 16-BIT UP/DOWN COUNTER VCO DATA TRANSFER LOGIC OUTPUT DATA LATCH COMP C5 R5 INTEGRATOR O/P PHASE-SENSITIVE DETECTOR A3 C4 VCO I/P TRACKING RATE SELECTION R7 C6 DATA SC1 SC2 LOAD ENABLE +5V DIGITAL BUSY VCO DIR INHIBIT O/P GND BYTE SELECT 16 DATA BITS Figure 1a. AD2S82A Connection Diagram REFERENCE I/P OFFSET ADJUST R9 –12V C3 HP FILTER +12V R3 C1 R8 R2 BANDWIDTH SELECTION C2 R4 R1 DEMOD I/P AC ERROR O/P SIN I/P COS I/P RIPPLE CLK +12V –12V PHASE-SENSITIVE DETECTOR A1 SEGMENT SWITCHING SIGNAL GND DEMOD O/P INTEGRATOR I/P C4 C5 R5 INTEGRATOR O/P A3 R-2R DAC A2 AD2S81A 16-BIT UP/DOWN COUNTER R6 VCO DATA TRANSFER LOGIC OUTPUT DATA LATCH VELOCITY SIGNAL VCO I/P TRACKING RATE SELECTION R7 C6 ENABLE 8 DATA BITS BYTE SELECT +5V DIGITAL GND BUSY DIR INHIBIT Figure 1b. AD2S81A Connection Diagram –6– REV. B AD2S81A/AD2S82A CONVERTER RESOLUTION (AD2S82A ONLY) HARMONIC DISTORTION Two major areas of the AD2S82A specification can be selected by the user to optimize the total system performance. The resolution of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12, 14 or 16 bits and the dynamic characteristics of bandwidth and tracking rate are selected by the choice of external components. The amount of harmonic distortion allowable on the signal and reference lines is 10%. The choice of the resolution will affect the values of R4 and R6 which scale the inputs to the integrator and the VCO, respectively (see the Component Selection section). If the resolution is changed, then new values of R4 and R6 must be switched into the circuit. Note: The figure specified of 10% harmonic distortion is for calibration convenience only. Square waveforms can be used but the input levels should be adjusted so that the average value is 1.9 V rms. (For example, a square wave should be 1.9 V peak). Triangular and sawtooth waveforms should have a amplitude of 2 V rms. POSITION OUTPUT The resolver shaft position is represented at the converter output by a natural binary parallel digital word. Note: When changing resolution under dynamic conditions, do it when the BUSY is low, i.e., when Data is not changing. As the digital position output of the converter passes through the major carries, i.e., all “1s” to all “0s” or the converse, a RIPPLE CLK logic output is initiated indicating that a revolution or a pitch of the input has been completed. CONVERTER OPERATION When connected in a circuit such as shown in Figure 1, the AD2S81A/AD2S82A operates as a tracking resolver-to-digital converter and forms a type 2 closed loop system. The output will automatically follow the input for speeds up to the selected maximum tracking rate. No convert command is necessary as the conversion is automatically initiated by each LSB increment, or decrement, of the input. Each LSB change of the converter initiates a BUSY pulse. The direction of input rotation is indicated by the DIRECTION (DIR) logic output. This direction data is always valid in advance of a RIPPLE CLK pulse and, as it is internally latched, only changing state (1 LSB min change) with a corresponding change in direction. Both the RIPPLE CLK pulse and the DIR data are unaffected by the application of the INHIBIT. The AD2S81A/AD2S82A is remarkably tolerant of input amplitude and frequency variation because the conversion depends only on the ratio of the input signals. Consequently there is no need for accurate, stable oscillator to produce the reference signal. The inclusion of the phase sensitive detector in the conversion loop ensures a high immunity to signals that are not coherent or are in quadrature with the reference signal. The static positional accuracy quoted is the worst case error that can occur over the full operating temperature excluding the effects of offset signals at the INTEGRATOR I/P (which can be trimmed out–see Figures 1a and 1b), and with the following conditions: input signal amplitudes are within 10% of the nominal; phase shift between signal and reference is less than 10 degrees. SIGNAL CONDITIONING These operating conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national standards. In practice, the AD2S81A/AD2S82A can be used well outside these operating conditions providing the above points are observed. The amplitude of the SINE and COSINE signal inputs should be maintained within 10% of the nominal values if full performance is required from the velocity signal. The digital position output is relatively insensitive to amplitude variation. Increasing the input signal levels by more than 10% will result in a loss in accuracy due to internal overload. Reducing levels will result in a steady decline in accuracy. With the signal levels at 50% of the correct value, the angular error will increase to an amount equivalent to 1.3 LSB. At this level the repeatability will also degrade to 2 LSB and the dynamic response will also change, since the dynamic characteristics are proportional to the signal level. VELOCITY SIGNAL The tracking converter technique generates an internal signal at the output of the integrator (the INTEGRATOR O/P pin) that is proportional to the rate of change of the input angle. This is a dc analog output referred to as the VELOCITY signal. In many applications it is possible to use the velocity signal of the AD2S81A/AD2S82A to replace a conventional tachogenerator. The AD2S81A/AD2S82A will not be damaged if the signal inputs are applied to the converter without the power supplies and/or the reference. DC ERROR SIGNAL The signal at the output of the phase-sensitive detector (DEMOD O/P) is the signal to be nulled by the tracking loop and is, therefore, proportional to the error between the input angle and the output digital angle. This is the dc error of the converter; and as the converter is a type 2 servo loop, it will increase if the output fails to track the input for any reason. It is an indication that the input has exceeded the maximum tracking rate of the converter or, due to some internal malfunction, the converter is unable to reach a null. By connecting two external comparators, this voltage can be used as a “built-in test.” REFERENCE INPUT The amplitude of the reference signal applied to the converter’s input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. The AD2S81A/AD2S82A will not be damaged if the reference is supplied to the converter without the power supplies and/or the signal inputs. REV. B –7– AD2S81A/AD2S82A COMPONENT SELECTION The following instructions describe how to select the external components for the converter in order to achieve the required bandwidth and tracking rate. In all cases the nearest “preferred value’’ component should be used and a 5% tolerance will not degrade the overall performance of the converter. Care should be taken that the resistors and capacitors will function over the required operating temperature range. The components should be connected as shown in Figure 1. 4. Maximum Tracking Rate (R6) The VCO input resistor R6 sets the maximum tracking rate of the converter, and hence the velocity scaling as at the max tracking rate, the velocity output will be 8 V. Decide on your maximum tracking rate, “T,” in revolutions per second. Note that “T” must not exceed the maximum tracking rate or 1/16 of the reference frequency. 10 R6 = PC compatible software is available to help users select the optimum component values for the AD2S81A and AD2S82A, and display the transfer gain, phase and small step response. Resolution 10 12 14 16 1 2 π R1 fREF C4 = (Hz) This filter gives an attenuation of three times at the input to the phase sensitive detector. EDC 100 × 10 −9 × 1 Ω R5 = 3 where 100 × 10 = current/LSB If R1, C2 are not fitted, then: –9 R4 = –9 Ω where E DC = 160 × 10–3 for 10 bits resolution = 40 × 10–3 for 12 bits = 10 × 10–3 for 14 bits = 2.5 × 10–3 for 16 bits = Scaling of the DC ERROR in volts 3. AC Coupling of Reference Input (R3, C3) Select R3 and C3 so that there is no significant phase shift at the reference frequency. That is, R3 = 100 kΩ C3 > with R3 in Ω. R6 × fBW 2 F 4 2 × π × f BW × C5 Ω 6. VCO Phase Compensation The following values of C6 and R7 should be fitted. EDC 100 × 10 21 with R6 in Ω and fBW, in Hz selected above. c. C5 is given by C5 = 5 × C4 F d. R5 is given by 2. Gain Scaling Resistor (R4) If R1, C2 are fitted, then: R4 = Ratio of Reference Frequency/Bandwidth 2.5 : 1 4 :1 6 :1 7.5 : 1 Typical values may be 100 Hz for a 400 Hz reference frequency and 500 Hz to 1000 Hz for a 5 kHz reference frequency. b. Select C4 so that 15 kΩ ≤ R1 = R2 ≤ 56 kΩ and fREF = Reference Frequency Ω 5. Closed-Loop Bandwidth Selection (C4, C5, R5) a. Choose the closed-loop bandwidth (fBW) required ensuring that the ratio of reference frequency to bandwidth does exceed the following guidelines: Values should be chosen so that C1 = C2 T ×n where n = bits per revolution = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits For more detailed information and explanation, see the Circuit Functions and Dynamic Performance section. 1. HF Filter (R1, R2, C1, C2) The function of the HF filter is to remove any dc offset and to reduce the amount of noise present on the signal inputs to the AD2S81A/AD2S82A, reaching the Phase Sensitive Detector and affecting the outputs. R1 and C2 may be omitted—in which case R2 = R3 and C1 = C3, calculated below— but their use is particularly recommended if noise from switch mode power supplies and brushless motor drive is present. 6. 32 × 10 1 R3 × fREF F C6 = 470 pF, R7 = 68 Ω 7. Offset Adjust Offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. If this can be tolerated, then R8 and R9 can be omitted from the circuit. If fitted, the following values of R8 and R9 should be used: R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer To adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. Connect the COS pin to the REFERENCE I/P and the SIN pin to the SIGNAL GND and with the power and reference applied, adjust the potentiometer to give all “0s” on the digital output bits. The potentiometer may be replaced with select on test resistors if preferred. –8– REV. B AD2S81A/AD2S82A If the AD2S81A/AD2S82A is being used in a pitch and revolution counting application, the ripple and busy will need to be gated to prevent false decrement or increment (see Figure 2). RIPPLE CLK is unaffected by INHIBIT. DATA TRANSFER To transfer data the INHIBIT input should be used. The data will be valid 600 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is applied and allows time for an active BUSY to clear. By using the ENABLE input the two bytes of data can be transferred after which the INHIBIT should be returned to a logic “HI” state to enable the output latches to be updated. +5V 1kV 10kV BUSY Output 1N414 8 RIPPLE CLK The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL level. A BUSY pulse is initiated each time the input moves by the analog equivalent of one LSB and the internal counter is incremented or decremented. 2N3904 0V +5V 5k1 TO COUNTER (CLOCK) 1N4148 BUSY NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS “LO.” Figure 2. Diode Transistor Logic Nand Gate INHIBIT Input The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a BUSY pulse to refresh the output data. DIRECTION Output The DIRECTION (DIR) logic output indicates the direction of the input rotation. Any change in the state of DIR precedes the corresponding BUSY, DATA, and RIPPLE CLK updates. DIR can be considered as an asynchronous output and can make multiple changes in state between two consecutive LSB update cycles. This corresponds to a change in input rotation direction but less than 1 LSB. ENABLE Input The ENABLE input determines the state of the output data. A logic “HI” maintains the output data pins in the high impedance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the ENABLE has no effect on the conversion process. COMPLEMENT (AD2S82A Only) The COMPLEMENT input is internally pulled to +12 V in the INACTIVE STATE. It is pulled down to DIGITAL GROUND (100 µA) to ACTIVATE. BYTE SELECT Input The BYTE SELECT input on the AD2S82A selects the byte of the position data to be presented at the data output DB1 to DB8. The least significant byte will be presented on data output DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S82A is used with a resolution less than 16 bits, the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “LO” will present the least significant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate data outputs 9 to 16. When used in conjunction with DATA LOAD, strobing DATA LOAD and COMPLEMENT pins to logic LO, will set the logic HIGH bits of the AD2S82A counter to a LO state. Those bits of the applied data which are logic LO will not change the corresponding bits in the AD2S82A counter: For Example: When the BYTE select pin is a logic “HI” on the AD2S81A, the most significant byte is presented on Pins 8 to 15 (with the ENABLE input taken to a logic “LO”). A logic “HI” presents the 4 least significant bits on Pins 8 to 11 and places a logic “LO” on Pins 12 to 15 (with the ENABLE input taken to a logic “LO”). 10101 11000 11000 Initial Counter State Applied Data Word Counter State after Data Load and Complement 10101 11000 00101 In order to read the output the following procedures should be followed: The operation of the BYTE SELECT has no effect on the conversion process of the converter. 1. Place Outputs in high impedance (ENABLE = HI). 2. Present data to pins. 3. Pull DATA LOAD and COMPLEMENT pins to ground. 4. Wait 100 ns. 5. Remove data from pins. 6. Remove outputs from high impedance state (ENABLE = LO). 7. Read outputs. RIPPLE CLOCK As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on the RIPPLE CLK output is initiated indicating that a revolution, or a pitch, of the input has been completed. The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE CLK is normally set high before a BUSY pulse and resets before the next positive going edge of the next consecutive pulse. The only exception to this is when DIR changes while the RIPPLE CLK is high. Resetting of the RIPPLE CLK will only occur if the DIR remains stable for two consecutive positive BUSY pulse edges. REV. B Initial Counter State Applied Data Word Counter State after Data Load –9– AD2S81A/AD2S82A CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE VH BUSY t1 RIPPLE CLK VH t2 t4 VL t5 VH t3 VH VH DATA INHIBIT The AD2S81A/AD2S82A allows the user greater flexibility in choosing the dynamic characteristics of the resolver-to-digital conversion to ensure the optimum system performance. The characteristics are set by the external components shown in Figure 1, and the Component Selection section explains how to select desired maximum tracking rate and bandwidth values. The following paragraphs explain in greater detail the circuit of the AD2S81A/AD2S82A and the variations in the dynamic performance available to the user. VL VH VL t6 VH DIR t7 Loop Compensation VL The AD2S81A and AD2S82A (connected as shown in Figure 1a and 1b) operates as a type 2 tracking servo loop where the VCO/counter combination and integrator perform the two integration functions inherent in a type 2 loop. t8 INHIBIT t9 VL DATA Additional compensation in the form of a pole/zero pair is required to stabilize any type 2 loop to avoid the loop gain characteristic crossing the 0 dB axis with 180° of additional phase lag, as shown in Figure 6. This compensation is implemented by the integrator components (R4, C4, R5, C5). VL ENABLE VH t 10 VZ t 11 VL VL BYTE SELECT VH The overall response of such a system is that of a unity gain second order low pass filter, with the angle of the resolver as the input and the digital position data as the output. VH DATA t 12 VL t 13 PARAMETER TMIN TMAX CONDITION t1 t2 t3 200 10 470 600 25 580 BUSY WIDTH VH –VH RIPPLE CLOCK VH TO BUSY V H RIPPLE CLOCK VL TO NEXT BUSY VH t4 t5 t6 t7 16 3 70 485 45 25 140 625 BUSY VH TO DATA VH BUSY VH TO DATA VL INHIBIT V H TO BUSY VH MIN DIR VH TO BUSY V H t8 t9 t 10 515 – 40 670 600 110 MIN DIR VH TO BUSY V H INHIBIT V L TO DATA STABLE ENABLE V L TO DATA VH t 11 t 12 t 13 35 60 60 110 140 125 ENABLE V L TO DATA VL BYTE SELECT V L TO DATA STABLE BYTE SELECT V H TO DATA STABLE The AD2S81A/AD2S82A does not have to be connected as tracking converter, parts of the circuit can be used independently. This is particularly true of the Ratio Multiplier which can be used as a control transformer (see Application Note). A block diagram of the AD2S81A/AD2S82A is given in Figure 4. Figure 3. Digital Timing C5 R5 AC ERROR C4 sin u sin vt cos u sin vt RATIO MULTIPLIER PHASESENSITIVE DEMODULATOR A1 sin (u – f) sin vt R4 INTEGRATOR CLOCK R6 DIGITAL f DIRECTION VCO VELOCITY Figure 4. AD2S81A/AD2S82A Functional Diagram –10– REV. B AD2S81A/AD2S82A Ratio Multiplier Phase Sensitive Demodulator The ratio multiplier is the input section of the AD2S81A/ AD2S82A and compares the signal from the resolver input angle, θ, to the digital angle, φ, held in the counter. Any difference between these two angles results in an analog voltage at the AC ERROR OUTPUT. This circuit function has historically been called a “Control Transformer” as it was originally performed by an electromechanical device known by that name. The phase sensitive demodulator is effectively ideal and develops a mean dc output at the DEMODULATOR O/P pin of ±2 2 π × ( DEMODULATOR I / P rms voltage) for sinusoidal signals in phase or antiphase with the reference (for a square wave the DEMODULATOR O/P voltage will equal the DEMODULATOR I/P). This provides a signal at the DEMODULATOR O/P which is a dc level proportional to the positional error of the converter. The AC ERROR signal is given by A1 sin (θ – φ) sin ωt where ω = 2 π fREF DC Error Scaling = 160 mV/bit (10-bits resolution) fREF = reference frequency = 40 mV/bit (12-bits resolution) = 10 mV/bit (14-bits resolution) = 2.5 mV/bit (16-bits resolution) A1, the gain of the ratio multiplier stage is 14.5. So for 2 V rms inputs signals AC ERROR output in volts/(bit of error) When the tracking loop is closed, this error is nulled to zero unless the converter input angle is accelerating. 360 = 2 × sin n × A1 Integrator The integrator components (R4, C4, R5, C5) are external to the AD2S81A/AD2S82A to allow the user to determine the optimum dynamic characteristics for any given application. The Component Selection section explains how to select components for a chosen bandwidth. Where n = bits per rev = 1,024 for 10-bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits Since the output from the integrator is fed to the VCO INPUT, it is proportional to velocity (rate of change of output angle) and can be scaled by selection of R6, the VCO input resistor. This is explained in the Voltage Controlled Oscillator (VCO) section below. Giving an AC ERROR O/P = 178 mV/bit @ 10-bits resolution = 44.5 mV/bit @ 12 bits = 11.125 mV/bit @ 14 bits = 2.78 mV/bit @ 16 bits The ratio multiplier will work in exactly the same way whether the AD2S81A/AD2S82A is connected as a tracking converter or as a control transformer, where data is preset into the counters using the DATA LOAD pin. HF Filter The AC ERROR OUTPUT may be fed to the PSD via a simple ac coupling network (R2, C1) to remove any dc offset at this point. Note, however, that the PSD of the AD2S81A/AD2S82A is a wideband demodulator and is capable of aliasing HF noise down to within the loop bandwidth. This is most likely to happen where the resolver is situated in particularly noisy environments, and the user is advised to fit a simple HF filter R1, C2 prior to the phase sensitive demodulator. The attenuation and frequency response of a filter will affect the loop gain and must be taken into account in deriving the loop transfer function. The suggested filter (R1, C1, R2, C2) is shown in Figure 1 and gives an attenuation at the reference frequency (fREF) of 3 times at the input to the phase sensitive demodulator. Values of components used in the filter must be chosen to ensure that the phase shift at fREF is within the allowable signal to reference phase shift of the converter. REV. B To prevent the converter from “flickering” (i.e., continually toggling by ±1 bit when the quantized digital angle, φ, is not an exact representation of the input angle, θ), feedback is internally applied from the VCO to the integrator input to ensure that the VCO will only update the counter when the error is greater than or equal to 1 LSB. In order to ensure that this feedback “hysteresis” is set to 1 LSB the input current to the integrator must be scaled to be 100 nA/bit. Therefore, R4 = DC Error Scaling (mV /bit ) 100 (nA /bit ) Any offset at the input of the integrator will affect the accuracy of the conversion as it will be treated as an error signal and offset the digital output. One LSB of extra error will be added for each 100 nA of input bias current. The method of adjusting out this offset is given in the Component Selection section. Voltage Controlled Oscillator (VCO) The VCO is essentially a simple integrator feeding a pair of dc level comparators. Whenever the integrator output reaches one of the comparator threshold voltages, a fixed charge is injected into the integrator input to balance the input current. At the same time the counter is clocking either up or down, dependent on the polarity of the input current. In this way the counter is clocked at a rate proportional to the magnitude of the input current of the VCO. –11– AD2S81A/AD2S82A During the reset period the input continues to be integrated, the reset period is constant at 400 ns. The VCO rate is fixed for a given input current by the VCO scaling factor: = 7.9 kHz / µA The tracking rate in rps per µA of VCO input current can be found by dividing the VCO scaling factor by the number of LSB changes per rev (i.e., 4096 for 12-bit resolution). The input resistor R6 determines the scaling between the converter velocity signal voltage at the INTEGRATOR O/P pin and the VCO input current. Thus to achieve a 5 V output at 100 rps (6000 rpm) and 12-bit resolution the VCO input current must be: (100 × 4096) / (7900) = 51.8 µA Figure 5 illustrates how the VCO output compensates for instances where, due to hysteresis, there is no change in the digital count output for 1 LSB change in input angle. The sum of the digital count output and VCO output equals the actual input angle. Transfer Function By selecting components using the method outlined in the Component Selection section, the converter will have a critically damped time response and maximum phase margin. The Closed-Loop Transfer Function is given by: 14 (1+ sN ) θOUT = (sN + 2.4)(sN 2 + 3.4 sN + 5.8) θ IN where SN, the normalized frequency variable, is: Thus, R6 would be set to: 5/(51.8 × 10-–6) = 96 kΩ The velocity offset voltage depends on the VCO input resistor, R6, and the VCO bias current and is given by Velocity Offset Voltage = R6 × (VCO bias current ) SN = 2 s π f BW and fBW is the closed loop 3 dB bandwidth (selected by the choice of external components). The acceleration constant, KA, is given approximately by The temperature coefficient of this offset is given by 2 K A = 6 × ( f BW ) sec Velocity Offset Tempco = R6 × (VCO bias current tempco) where the VCO bias current tempco is typically –1.22 nA/°C. The maximum recommended rate for the VCO is 1.1 MHz which sets the maximum possible tracking rate. The normalized gain and phase diagrams are given in Figures 6 and 7. 12 Since the minimum voltage swing available at the integrator output is ± 8 V, this implies that the minimum value for R6 is 57 kΩ. As Min Value R6 = 1.1 × 10 9 6 6 7.9 × 10 3 = 139 µA GAIN PLOT Max Current = −2 8 = 57 kΩ 139 ×10 −6 3 0 –3 –6 VCO OUTPUT –9 In order to overcome the “freeplay” inherent in a servo system using digitized position feedback, an analog output voltage is available representing the resolver shaft position within the least significant bit of digital angle output. –12 0.02 0.04 0.1 0.2 0.4 0 2 FREQUENCY – fBW Figure 6. AD2S81A/AD2S82A Gain Plot The converter updates the output if the error is an LSB or greater and the VCO output gives the positional error smaller than 1 LSB. 180 135 90 PHASE PLOT DIGITAL COUNT OUTPUT INPUT ANGLE +LSB 45 0 –45 0 –90 –LSB –135 +3V –180 0.02 VCO OUTPUT –3V 0.04 0.1 0.2 0.4 FREQUENCY – fBW 0 2 Figure 7. AD2S81A/AD2S82A Phase Plot Figure 5. –12– REV. B AD2S81A/AD2S82A The small signal step response is shown in Figure 8. The time from the step to the first peak is t1 and the t2 is the time from the step until the converter is settled to 1 LSB. The times t1 and t2 are given approximately by t1 = t2 = 1 f BW Error in LSBs = = 100 [rev/sec2 ] × 212 = 0.15 LSBs or 47.5 seconds of arc 2.7 × 106 To determine the value of KA based on the passive components used to define the dynamics of the converter, the following should be used: 5 R × f BW 12 11 KA = where R = resolution, i.e., 10, 12, 14 or 16. OUTPUT POSITION Input Acceleration [LSB/sec2 ] K A[sec –2 ] t2 4.04 × 10 n 2 ⋅ R6 ⋅ R4 ⋅ (C4 + C5) Where n = resolution of the converter R4, R6 in ohms C5, C4 in farads SOURCES OF ERRORS Integrator Offset Additional inaccuracies in the conversion of the resolver signals will result from an offset at the input to the integrator as it will be treated as an error signal. This error will typically be 1 arc minute over the operating temperature range. TIME t1 A description of how to adjust from zero offset is given in the Component Selection section and the circuit required is shown in Figures 1a and 1b. Figure 8. AD2S81A/AD2S82A Small Step Response The large signal step response (for steps greater than 5 degrees) applies when the error voltage exceeds the linear range of the converter. Differential Phase Shift Phase shift between the sine and cosine signals from the resolver is known as differential phase shift and can cause static error. Some differential phase shift will be present on all resolvers as a result of coupling. A small resolver residual voltage (quadrature voltage) indicates a small differential phase shift. Additional phase shift can be introduced if the sine channel wires and the cosine channel wires are treated differently. For instance, different cable lengths or different loads could cause differential phase shift. Typically the converter will take three times longer to reach the first peak for a 179 degrees step. In response to a velocity step, the velocity output will exhibit the same time response characteristics as outlined above for the position output. ACCELERATION ERROR A tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant KA of the converter. KA = The additional error caused by differential phase shift on the input signals approximates to Error = 0.53 a × b arc minutes where a = differential phase shift (degrees). b = signal to reference phase shift (degrees). Input Acceleration Error in Output Angle The numerator and denominator must have consistent angular units. For example, if KA is in sec–2, then the input acceleration may be specified in degrees/sec2 and the error output in degrees. Angular measurement may also be specified using radians, minutes of arc, LSBs, etc. KA does not define maximum input acceleration, only the error due to it’s acceleration. The maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. Angular Accuracy × KA = degrees/sec2 KA can be used to predict the output position error for a given input acceleration. For example for an acceleration of 100 revs/ sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution. REV. B This error can be minimized by choosing a resolver with a small residual voltage, ensuring that the sine and cosine signals are handled identically and removing the reference phase shift (see Connecting the Resolver section). By taking these precautions the extra error can be made insignificant. Under static operating conditions phase shift between the reference and the signal lines alone will not theoretically affect the converter’s static accuracy. However, most resolvers exhibit a phase shift between the signal and the reference. This phase shift will give rise under dynamic conditions to an additional error defined by: –13– Shaft Speed (rps) × Phase Shift (Degrees ) Reference Frequency AD2S81A/AD2S82A Following the preceding precautions will allow the user to use the velocity signal in very noisy environments for example PWM motor drive applications. Resolver/converter error curves may exhibit apparent acceleration/deceleration at a constant velocity. This results in ripple on the velocity signal of frequency twice the input rotation. For example, for a phase shift of 20 degrees, a shaft rotation of 22 rps and a reference frequency of 5 kHz, the converter will exhibit an additional error of: 22 × 20 0.088 degrees 5000 This effect can be eliminated by putting a phase shift in the reference to the converter equivalent to the phase shift in the resolver (see Connecting the Resolver section). CONNECTING THE RESOLVER The recommended connection circuit is shown in Figure 9. Note: Capacitive and inductive crosstalk in the signal and reference leads and wiring can cause similar problems. OSCILLATOR (e. g. OSC1758) C3 VELOCITY ERRORS 1 REF I/P The signal at the INTEGRATOR O/P pin relative to the ANALOG GND pin is an analog voltage proportional to the rate of change of the input angle. This signal can be used to stabilize servo loops or in the place of a velocity transducer. Although the conversion loop of the AD2S81A/AD2S82A includes a digital section, there is an additional analog feedback loop around the velocity signal. This ensures against flicker in the digital positional output in both dynamic and static states. R3 AD2S82A 2 TWISTED PAIR SCREENED CABLE DIGITAL 31 GND 3 4 COS I/P 5 ANALOG GND S2 R1 S4 S3 R2 S1 6 SIGNAL GND 7 SIN I/P A better quality velocity signal will be achieved if the following points are considered: RESOLVER 1. Protection. The velocity signal should be buffered before use. POWER RETURN Figure 9. Connecting the AD2S82A to a Resolver 2. Reversion error* The reversion error can be nulled by varying one supply rail relative to the other. In cases where the reference phase relative to the input signals from the resolver requires adjustment, this can be easily achieved by varying the value of the resistor R2 of the HF filter (see Figures 1a and 1b). 3. Ripple and Noise. Noise on the input signals to the converter is the major cause of noise on the velocity signal. This can be reduced to a minimum if the following precautions are taken: Assuming that R1 = R2 = R and C1 = C2 = C 1 and Reference Frequency = 2 π RC The resolver is connected to the converter using separate twisted pair cable for the sine, cosine and reference signals. Care is taken to reduce the external noise wherever possible. An HF filter is fitted before the Phase-Sensitive Demodulator (as described in the section HF FILTER). by altering the value of R2, the phase of the reference relative to the input signals will change in an approximately linear manner for phase shifts of up to 10 degrees. A resolver is chosen that has low residual voltage, i.e., a small signal in quadrature with the reference. Increasing R2 by 10% introduces a phase lag of 2 degrees. Decreasing R2 by 10% introduces a phase lead of 2 degrees. Components are selected to operate the AD2S81A/AD2S82A with the lowest acceptable bandwidth. Feedthrough of the reference frequency should be removed by a filter on the velocity signal. R Maintenance of the input signal voltages at 2 V rms will prevent LSB flicker at the positional output. The analog feedback or hysteresis employed around the VCO and the integrator is a function of the input signal levels (see Integrator section). * 1 PHASE LEAD = ARC TAN 2 p fRC C PHASE LAG = ARC TAN 2 p fRC R C Figure 10. Phase Shift Circuits Reversion error, or side-to-side nonlinearity, is a result of differences in the up and down rates of the VCO. –14– REV. B AD2S81A/AD2S82A 1MV 100kV 100nF REFERENCE INPUT 100nF 22nF 15kV 4.7MV VELOCITY O/P 22nF 15kV 1.5nF 39kV COS HIGH RESOLVER REF LOW COS LOW SIGNAL SIN LOW 6 SIN HIGH 7 +12V 8 MSB DATA OUTPUT 5 4 3 2 110kV 180kV 68V 470pF 6.8nF 100nF 1 44 43 42 41 40 –12V 39 PIN 1 IDENTIFIER 38 RIPPLE CLK 9 37 DIRECTION 10 36 BUSY 11 AD2S82A 35 DATA LOAD 12 TOP VIEW (Not to scale) 34 COMPLEMENT 33 SC2 13 14 32 15 31 16 30 0V INHIBIT 29 17 18 19 20 21 22 23 24 25 26 27 28 LSB DATA OUTPUT +5V BYTE SELECT ENABLE Figure 11. Typical Circuit Configuration TYPICAL CIRCUIT CONFIGURATION Figure 11 shows a typical circuit configuration for the AD2S81A/ AD2S82A in a 12-bit resolution mode. Values of the external components have been chosen for a reference frequency of 5 kHz and a maximum tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the values for R4, R6, C4 and C5 in the equation for KA gives a value of 2.7 × 106. The resistors are 0.125 W, 5% tolerance preferred values. The capacitors are 100 V ceramic, 10% tolerance components. For signal and reference voltages greater than 2 V rms a simple voltage divider circuit of resistors can be used to generate the correct signal level at the converter. Care should be taken to ensure that the ratios of the resistors between the sine signal line and ground and the cosine signal line and ground are the same. Any difference will result in an additional position error. 360 315 ANGLE – Degrees 270 225 APPLICATIONS Control Transformer The ratio multiplier of the AD2S82A can be used independently of the loop integrators as a control transformer. In this mode the resolver inputs θ are multiplied by a digital angle φ, any difference between and φ and θ will be represented by the AC ERROR output as SIN ωt sin (θ–φ) or the DEMOD output as sin (θ–φ). To use the AD2S81A/AD2S82A in this mode refer to the “Control Transformer” application note. Dynamic Switching In applications where the user requires wide band response from the converter, for example 100 rpm to 6000 rpm, superior performance is achieved if the converters control characteristics are switched dynamically. This reduces velocity offset levels at low tracking rates. For more information on the technique refer to “Dynamic Resolution Switching Using the Variable Resolution Monolithic Resolver-to-Digital Converters.” OTHER PRODUCTS 180 135 90 45 0 0 4 8 12 TIME – ms 16 20 24 Figure 12. Large Step Response Curves for Typical Circuit Shown in Figure 11 REV. B For more information on resistive scaling of SIN, COS and REFERENCE converter inputs, refer to the application note “Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital Converters.” The AD2S80A is a monolithic resolver-to-digital converter offering 10–16 bits of resolution and user selectable dynamics. The AD2S80A is also available in 40-lead ceramic DIP, 44-lead LCC and is qualified to MIL-STD 883B Rev C. The AD2S46 is a highly integrated hybrid resolver/synchro to digital converter packaged in a 28-lead ceramic DIP. The part offers the user 1.3 arc minutes of accuracy over the full military temperature range. The AD2S34 is a dual channel 14-bit hybrid resolver-to-digital converter packaged in a 1 in2 32-lead flatpack. The 1740/41/42 are hybrid resolver/synchro to digital converters which incorporate pico-transformer isolated input signal conditioning. –15– AD2S81A/AD2S82A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.005 (0.13) MIN C1453b–2.5–11/98 Ceramic DIP (D) Package (D-28) 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 1.490 (37.85) MAX 0.060 (1.52) 0.015 (0.38) 0.225 (5.72) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.026 (0.66) 0.125 (3.18) 0.014 (0.36) 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) 0.110 (2.79) 0.070 (1.78) SEATING 0.090 (2.29) 0.030 (0.76) PLANE Plastic Leaded Chip Carrier (P) Package (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 7 0.025 (0.63) 0.015 (0.38) 40 39 PIN 1 IDENTIFIER 0.050 (1.27) 0.63 (16.00) BSC 0.59 (14.99) 0.021 (0.53) 0.013 (0.33) TOP VIEW (PINS DOWN) 17 29 28 18 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) 0.110 (2.79) 0.085 (2.16) PRINTED IN U.S.A. 0.020 (0.50) R 0.032 (0.81) 0.026 (0.66) –16– REV. B