LH5116S FEATURES CMOS 16K (2K × 8) Static RAM PIN CONNECTIONS • 2,048 × 8 bit organization • Access time: 1000 ns (MAX.) • Low-power consumption: Operating: 33 mW (MAX.) Standby: 3.3 µW (MAX.) • Fully-static operation • Three-state outputs • Single +3 V power supply • Package: 24-pin, 450-mil SOP DESCRIPTION The LH5116S is a static RAM organized as 2,048 × 8 bits. It is fabricated using silicon-gate CMOS process technology. It operates at a low supply voltage of 3 V ±10%. 24-PIN SOP TOP VIEW A7 1 24 VCC A6 2 23 A8 A5 3 22 A9 A4 4 21 WE A3 5 20 OE A10 A2 6 19 A1 7 18 CE A0 8 17 I/O8 I/O1 9 16 I/O7 I/O2 10 15 I/O6 I/O3 11 14 I/O5 GND 12 13 I/O4 5116S-1 Figure 1. Pin Connections for SOP Package 1 CMOS 16K (2K × 8) Static RAM ROW ADDRESS BUFFERS A0 8 A5 3 A6 2 ROW DECODERS LH5116S A7 1 A8 23 A9 22 A10 19 MEMORY CELL ARRAY (128 x128) 24 VCC 12 GND CE DATA CONTROL I/O1 9 I/O2 10 I/O3 11 I/O4 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17 COLUMN I/O CIRCUITS COLUMN DECODERS COLUMN ADDRESS BUFFERS CE CE 18 WE 21 OE 20 4 A4 5 A3 6 A2 7 A1 5116S-2 Figure 2. LH5116S Block Diagram PIN DESCRIPTION SIGNAL PIN NAME A0 - A10 SIGNAL Address input I/O1 - I/O8 PIN NAME Data input/output CE Chip Enable input VCC Power supply OE Output Enable input GND Ground WE Write Enable input TRUTH TABLE CE OE WE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE L X L Write DIN Operating (ICC) 1 L L H Read DOUT Operating (ICC) H X X Deselect High-Z Standby (ISB) 1 L H X Output disable High-Z Operating (ICC) 1 NOTE: 1. X = H or L 2 CMOS 16K (2K × 8) Static RAM LH5116S ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage VCC -0.3 to +7.0 V 1 Input voltage VIN -0.3 to VCC +0.3 V 1 Operating temperature Topr 0 to +50 °C Storage temperature Tstg -55 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +50°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 2.7 3.0 3.3 V Supply voltage Input voltage VIH 2.2 VCC + 0.3 V VIL -0.3 0.8 V DC CHARACTERISTICS (VCC = 3 V ±10%, TA = 0 to +50°C) PARAMETER SYMBOL CONDITIONS MIN. Output ‘LOW’ voltage VOL IOL = 2.1 mA Output ‘HIGH’ voltage VOH IOH = -1.0 mA VCC - 0.5 Input leakage current ILI VIN = 0 V to VCC -1.0 -1.0 Output leakage current Operating current Standby current TYP. MAX. 0.5 UNIT NOTE V V µA 1.0 ILO CE = VIH, VI/O = 0 V to VCC 1.0 µA ICC1 Outputs open (OE = VCC) 8 10 mA 1 ICC2 Outputs open (OE = VIH) 8 10 mA 2 ICCL CE ≥ VCC - 0.2 V All other input pins = 0 V to VCC 1.0 µA NOTES: 1. CE = 0 V; all other input pins = 0 V to VCC 2. CE = VIL; all other input pins = VIL to VIH AC CHARACTERISTICS (VCC = 3 V ±10%, TA = 0 to +50°C) (1) READ CYCLE PARAMETER Read cycle time SYMBOL MIN. tRC 1000 TYP. MAX. UNIT NOTE ns Address access time tAA 1000 ns Chip enable access time tACE 1000 ns Chip enable Low to output in Low-Z tCLZ Output enable access time tOE 100 ns Output enable Low to output in Low-Z tOLZ 10 10 ns 1 ns 1 Chip disable to output in High-Z tCHZ 0 40 ns 1 Output enable to output in High-Z tOHZ 0 40 ns 1 Output hold time tOH 10 ns NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. 3 CMOS 16K (2K × 8) Static RAM LH5116S (2) WRITE CYCLE (VCC = 3 V ±10%, TA = 0 to +50°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write cycle time tWC 1000 ns Chip enable to end of write tCW 100 ns Address valid time tAW 100 ns Address setup time tAS 0 ns Write pulse width tWP 100 ns Write recovery time tWR 20 ns WE Low to output in High-Z tWHZ Data valid to end of write tDW 50 ns Data hold time tDH 20 ns Output active from end of write tOW 10 Output enable to output in High-Z tOHZ 0 30 NOTE ns 40 1 ns 1 ns 1 NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude NOTE 0 to VCC Input rise/fall time 10 ns Timing reference level 1.5 V Output load conditions CL (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. DATA RETENTION CHARACTERISTICS (TA = 0 to +50°C) PARAMETER SYMBOL CONDITIONS MIN. Data retention voltage VCCDR CE ≥ VCCDR - 0.2 V 2.0 Data retention current ICCDR CE ≥ VCCDR - 0.2 V, VCCDR = 2.0 V Chip disable to data retention Recovery time TYP. MAX. UNIT V 1.0 µA 0.2 tCDR 0 ns tR tRC ns NOTES: 1. TA = 25°C 2. t RC = Read cycle time CAPACITANCE 1 (TA = 25°C, f = 1MHz) PARAMETER SYMBOL CONDITIONS TYP. MAX. UNIT Input capacitance CIN VIN = 0 V 7 pF Input/output capacitance CI/O VI/O = 0 V 10 pF NOTE: 1. This parameter is sampled and not production tested. 4 MIN. NOTE 1 2 CMOS 16K (2K × 8) Static RAM LH5116S tCDR tR DATA RETENTION MODE VCC 2.5 V 2.2 V VCCDR CE ≥ VCCDR -0.2 V CE 0V 5116S-6 Figure 3. Low Voltage Data Retention tRC A0 - A10 tAA tOH tACE CE tOE tCHZ OE tOLZ tOHZ tCLZ DOUT DATA VALID NOTE: WE = "HIGH" 5116S-3 Figure 4. Read Cycle 5 CMOS 16K (2K × 8) Static RAM LH5116S tWC A0 - A10 tWR (NOTE 3) tAW tCW CE tAS tWP (NOTE 2) WE tWHZ tOW (NOTE 4) (NOTE 5) DOUT tDW tDH (NOTE 6) DIN OE = 'LOW' NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied. 5116S-4 Figure 5. Write Cycle 1 (Note 1) tWC A0 - A10 tAW tWR (NOTE 3) OE tCW CE tAS tWP (NOTE 2) WE tOLZ tOHZ DOUT tOW (NOTE 5) tDW tDH (NOTE 4) (NOTE 6) DIN NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE and OE are LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied. Figure 6. Write Cycle 2 (Note 1) 6 5116S-5 CMOS 16K (2K × 8) Static RAM LH5116S PACKAGE DIAGRAM 24SOP (SOP024-P-0450B) 1.27 [0.050] TYP. 0.50 [0.120] 0.30 [0.012] 1.70 [0.067] 24 13 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457] 1 10.60 [0.417] 12 1.70 [0.067] 15.60 [0.614] 15.20 [0.598] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 24SOP 24-pin, 450-mil SOP ORDERING INFORMATION LH5116S Device Type N Package 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116SN (CMOS 16K (2K x 8) Static RAM, 450-mil SOP) 5116S-7 7