SHARP LH5164AV

LH5164AV
FEATURES
CMOS 64K (8K × 8) Static RAM
PIN CONNECTIONS
• 8,192 × 8 bit organization
• Access time: 200 ns (MAX.)
TOP VIEW
28-PIN SOP
• Supply current (MAX.):
Operating: 248 mW
55 mW (tRC, tWC = 1 µs)
Standby: 5.5 µW
Data retention:
0.6 µW (VCC = 3 V, tA = 25°C)
1
28
A12
2
27
WE
A7
3
26
CE2
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
NC
• Wide operating voltage range:
2.7 V to 5.5 V
VCC
A1
9
20
CE1
A0
10
19
I/O8
• Fully-static operation
I/O1
11
18
I/O7
I/O2
12
17
I/O6
• TTL compatible I/O
I/O3
13
16
I/O5
GND
14
15
I/O4
• Three-state outputs
5164AV-1
• Packages:
28-pin, 450-mil SOP
28-pin, 8 × 13 mm2 TSOP (Type I)
Figure 1. Pin Connections for SOP Package
28-PIN TSOP (Type I)
TOP VIEW
DESCRIPTION
The LH5164AV is a static RAM organized as 8,192 × 8
bits. It is fabricated using silicon-gate CMOS process
technology.
OE
1
28
A11
2
27
CE1
A9
3
26
I/O8
A8
4
25
I/O7
CE2
5
24
I/O6
WE
VCC
6
23
I/O5
7
22
I/O4
A10
NC
8
21
GND
A12
9
20
I/O3
A7
10
19
I/O2
A6
11
18
I/O1
A5
12
17
A0
A4
13
16
A1
A3
14
15
A2
5164AV-2
Figure 2. Pin Connections for TSOP Package
1
CMOS 64K (8K × 8) Static RAM
LH5164AV
A9 24
28 VCC
A8 25
A12 2
14 GND
A7 3
MEMORY
ARRAY
(256 x 256)
ROW
SELECT
A6 4
A5 5
A4 6
A3
7
I/O1 11
I/O2 12
I/O3 13
I/O4 15
COLUMN I/O
CIRCUITS
INPUT
DATA
CONTROL
I/O5 16
I/O6 17
I/O7 18
I/O8 19
COLUMN SELECT
WE 27
OE 22
CE2 26
CE1 20
8
A2
9
A1
10
A0
23
A11
21
A10
NOTE: Pin numbers apply to the 28-pin SOP.
5164AV-3
Figure 3. LH5164AV Block Diagram
PIN DESCRIPTION
SIGNAL
A0 - A12
2
PIN NAME
Address inputs
SIGNAL
I/O1 - I/O8
PIN NAME
Data inputs and outputs
CE1/CE2
Chip Enable input
VCC
Power supply
WE
Write Enable input
GND
Ground
OE
Output Enable input
NC
No connection
CMOS 64K (8K × 8) Static RAM
LH5164AV
TRUTH TABLE
CE1
CE2
WE
OE
H
X
X
X
X
L
X
X
MODE
I/O 1 - I/O 8
SUPPLY CURRENT
NOTE
Standby
High-Z
Standby (ISB)
1
1
L
H
L
X
Write
Data input
Operating (ICC)
L
H
H
L
Read
Data output
Operating (ICC)
L
H
H
H
Output disable
High-Z
Operating (ICC)
NOTE:
1. X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
VCC
–0.3 to +7.0
V
1
Input voltage
VIN
–0.3 to VCC +0.3
V
1, 2
Operating temperature
Topr
–10 to +70
°C
Storage temperature
Tstg
–65 to +150
°C
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. VIN (MIN.) = –3.0 V for pulse width ≤50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = –10°C to +70°C)
PARAMETER
SYMBOL
MIN.
Supply voltage
VCC
Input voltage
(VCC = 2.7 V to 3.6 V)
Input voltage
(VCC = 4.5 V to 5.5 V)
TYP.
MAX.
UNIT
2.7
5.5
V
VIH
VCC – 0.5
VCC + 0.3
V
VIL
–0.3
0.2
V
VIH
2.2
VCC + 0.3
V
VIL
–0.3
0.8
V
NOTE
1
1
NOTE:
1. VIL (MIN.) = –3.0 V for pulse width ≤50 ns.
3
CMOS 64K (8K × 8) Static RAM
LH5164AV
DC CHARACTERISTICS 1 (TA = –10°C to +70°C, VCC = 2.7 V to 5.5 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0
1.0
µA
Output leakage
current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = 0 to VCC
–1.0
1.0
µA
Operating supply
current
ICC
CE1 = 0.2 V, VIN = 0.2 V, or
VCC – 0.2 V
CE2 = VCC – 0.2 V,
Outputs open,
VCC = 2.7 V to 3.6 V
tCYCLE =
200 ns
20
tCYCLE =
1.0 µs
8
tCYCLE =
200 ns
45
tCYCLE =
1.0 µs
10
V CC = 2.7 V
to 3.6 V
0.6
V CC = 4.5 V
to 5.5 V
1.0
CE1 = VIL, VIN = VIL or VIH
CE2 = VIH, Outputs open,
VCC = 4.5 V to 5.5 V
Standby current
ISB
ISB1
VOL
Output voltage
VOH
CE2 ≤ 0.2 V or
CE1 ≥ VCC – 0.2 V
4
mA
µA
CE1 = VIH or CE2 = VIL
5
IOL = 500 µA, VCC = 2.7 V to 3.6 V
0.4
IOL = 2.1 mA, VCC = 4.5 V to 5.5 V
0.4
IOH = –500 µA, VCC = 2.7 V to 3.6 V
VCC –
0.5
IOH = –1.0 mA, VCC = 4.5 V to 5.5 V
2.4
NOTE:
1. CE2 should be ≥ VCC – 0.2 V or ≤0.2 V when CE1 ≥ VCC – 0.2 V.
NOTE
mA
V
V
1
CMOS 64K (8K × 8) Static RAM
LH5164AV
READ CYCLE (TA = –10°C to +70°C, VCC = 2.7 V to 5.5 V)
PARAMETER
Read cycle time
Address access time
SYMBOL
MIN.
tRC
200
MAX.
UNIT
ns
tAA
200
ns
CE 1 access time
tACE1
200
ns
CE 2 access time
tACE2
200
ns
Output enable access time
tOE
150
ns
Output hold time
tOH
10
ns
CE 1 Low to output in Low-Z
tLZ1
20
ns
CE 2 High to output in Low-Z
tLZ2
20
ns
OE Low to output in Low-Z
tOLZ
10
ns
CE 1 High to output in High-Z
tHZ1
0
60
ns
CE 2 Low to output in High-Z
tHZ2
0
60
ns
OE High to output in High-Z
tOHZ
0
40
ns
WRITE CYCLE (TA = –10°C to +70°C, VCC = 2.7 V to 5.5 V)
PARAMETER
SYMBOL
MIN.
tWC
200
ns
CE Low to end of write
tCW
180
ns
Address valid to end of write
tAW
180
ns
Address setup time
tAS
0
ns
Write pulse width
tWP
150
ns
Write recovery time
tWR
0
ns
Input data setup time
tDW
100
ns
Write cycle time
MAX.
UNIT
Input data hold time
tDH
0
ns
WE High to output in Low-Z
tOW
20
ns
WE Low to output in High-Z
tWZ
0
60
ns
OE High to output in High-Z
tOHZ
0
40
ns
TEST CONDITIONS
PARAMETER
MODE
Input pulse level
NOTE
0.2 V to VCC – 0.2 V
Input rise/fall time
10 ns
Input/output timing level
1.5 V
Output load
CL (100 pF)
1
NOTE:
1. Includes scope and jig capacitance.
CAPACITANCE 1 (TA = 25°C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
CIN
VIN = 0 V
7
pF
I/O capacitance
CI/O
VI/O = 0 V
10
pF
NOTE:
1. This parameter is sampled and not production tested.
5
CMOS 64K (8K × 8) Static RAM
LH5164AV
DATA RETENTION CHARACTERISTICS (TA = –10°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Data retention supply voltage
VCCDR
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
2.0
5.5
V
1
TA =
25°C
0.2
µA
TA =
40°C
0.4
µA
0.6
µA
VCCDR = 3 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
Data retention supply current
ICCDR
Chip disable to data retention
tCDR
0
ns
tR
tRC
ns
Recovery time
1
2
NOTES:
1. CE2 should be ≥ VCCDR – 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR – 0.2 V.
2. t RC = Read cycle time.
CE1 CONTROL (NOTE)
DATA RETENTION MODE
VCC
2.7 V
tCDR
tR
VCC - 0.5 V
VCCDR
CE1 ≥ VCCDR - 0.2 V
CE1
0V
CE2 CONTROL
DATA RETENTION MODE
VCC
2.7 V
CE2
tR
tCDR
VCCDR
0.2 V
0V
CE2 ≤ 0.2 V
NOTE: To control the data retention mode at CE1, fix the input level of CE2 between
VCCDR to VCCDR - 0.2 V or 0 V and 0.2 V during the data retention mode.
5164AV-7
Figure 4. Data Retention Characteristics
6
CMOS 64K (8K × 8) Static RAM
LH5164AV
tRC
A0 - A12
tAA
tACE1
CE1
tLZ1
tACE2
tHZ1
CE2
tLZ2
tHZ2
tOE
tOLZ
OE
tOHZ
DOUT
DATA VALID
tOH
NOTE: WE = 'HIGH.'
5164AV-4
Figure 5. Read Cycle
7
CMOS 64K (8K × 8) Static RAM
LH5164AV
tWC
A0 - A12
OE
tAW
tWR
tCW
(NOTE 1)
(NOTE 2)
tCW
tWR
CE1
CE2
tAS
tWP
(NOTE 3)
(NOTE 4)
tWR
WE
tOHZ
DOUT
tDW
DIN
(NOTE 5)
DATA VALID
NOTES:
1. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2
HIGH transition, to the time when the writing is finished.
2. tWR is defined as the time from writing finish to address change.
3. tAS is defined as the time from address change to writing start.
4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
Figure 6. Write Cycle (OE Controlled)
8
tDH
5164AV-5
CMOS 64K (8K × 8) Static RAM
LH5164AV
tWC
A0 - A12
tAW
tCW
tWR
(NOTE 1)
(NOTE 2)
tCW
tWR
CE1
CE2
tAS
tWP
(NOTE 3)
(NOTE 4)
tWR
WE
tWZ
tOW
(NOTE 6)
(NOTE 5)
DOUT
tDW
DIN
tDH
(NOTE 7)
DATA VALID
NOTES:
1. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
2. tWR is defined as the time from writing finish to address change.
3. tAS is defined as the time from address change to writing start.
4. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition,
the outputs will remain high-impedance.
7. When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164AV-6
Figure 7. Write Cycle (OE Low Fixed)
9
CMOS 64K (8K × 8) Static RAM
LH5164AV
PACKAGE DIAGRAMS
28SOP (SOP028-P-0450)
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
1.70 [0.067]
28
15
8.80 [0.346]
8.40 [0.331]
1
12.40 [0.488]
11.60 [0.457]
10.60 [0.417]
14
1.70 [0.067]
0.20 [0.008]
0.10 [0.004]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP
28-pin, 450-mil SOP
10
CMOS 64K (8K × 8) Static RAM
LH5164AV
28TSOP (TSOP028-P-0813)
0.28 [0.011]
0.12 [0.005]
0.55 [0.022]
TYP.
28
15
12.00 [0.472]
11.60 [0.457]
1
13.70 [0.539]
13.10 [0.516]
12.60 [0.496]
12.20 [0.480]
14
8.20 [0.323]
7.80 [0.307]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
DETAIL
1.10 [0.043]
0.90 [0.035]
1.20 [0.047]
MAX.
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
DIMENSIONS IN MM [INCHES]
0 - 10°
0.425 [0.017]
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.00 [0.000]
MAXIMUM LIMIT
MINIMUM LIMIT
28TSOP
28-pin, 8 × 13 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5164AV
Device Type
X
Package
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813)
CMOS 64K (8K x 8) Static RAM
Example: LH5164AVN (CMOS 64K (8K x 8) Static RAM, 28-pin, 450-mil SOP)
5164AV-8
11