LH5164ASH FEATURES CMOS 64K (8K × 8) Static RAM PIN CONNECTIONS • 8,192 × 8 bit organization • Access time: 500 ns (MAX.) TOP VIEW 28-PIN SOP • Power consumption: Operating: 60 mW (MAX.) @ 3 V Standby: 3 µW (MAX.) @ 70°C @ 3 V 9 µW (MAX.) @ 85°C @ 3 V • Fully-static operation • Three-state outputs • Wide operating voltage range: 2.5 V to 5.5 V • TTL compatible I/O • Wide temp. range tOPR: -40 to +85°C • Packages: 28-pin, 450-mil SOP 28-pin, 8 × 13 mm2 TSOP (Type I) DESCRIPTION The LH5164ASH is a static RAM organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology. It is designed for 2.5 to 5.5 V low voltage operation and wide temperature range from -40 to +85°C. NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 5164ASH-1 Figure 1. Pin Connections for SOP Package 28-PIN TSOP (Type I) TOP VIEW OE 1 28 A11 2 27 CE1 A9 3 26 I/O8 A10 A8 4 25 I/O7 CE2 5 24 I/O6 WE 6 23 I/O5 VCC 7 22 I/O4 NC 8 21 GND A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 5164ASH-8 Figure 2. Pin Connections for TSOP Package 1 CMOS 64K (8K × 8) Static RAM LH5164ASH ROW ADDRESS BUFFERS 7 A4 6 A5 5 A6 4 ROW DECODERS A3 A7 3 A8 25 A9 24 A12 2 I/O1 11 I/O2 12 I/O3 13 I/O4 15 28 VCC MEMORY ARRAY (256 x 256) 14 GND I/O CIRCUITS DATA CONTROL I/O5 16 I/O6 17 I/O7 18 I/O8 19 COLUMN DECODERS COLUMN ADDRESS BUFFERS WE 27 OE 22 CE2 26 CE1 20 10 A0 9 A1 8 A2 21 A10 23 A11 5164ASH-2 Figure 3. LH5164ASH Block Diagram PIN DESCRIPTION SIGNAL A0 - A12 2 PIN NAME Address inputs SIGNAL I/O1 - I/O8 PIN NAME Data inputs and outputs CE1 - CE2 Chip Enable input VCC Power supply WE Write Enable input GND Ground OE Output Enable input NC No connection CMOS 64K (8K × 8) Static RAM LH5164ASH TRUTH TABLE CE1 CE2 WE OE MODE I/O 1 - I/O8 SUPPLY CURRENT NOTE H X L L L X L H H H X X L H H X X X L H Deselect Deselect Write Read Output disable High-Z High-Z DIN DOUT High-Z Standby (ISB ) Standby (ISB ) Operating (ICC) Operating (ICC) Operating (ICC) 1 1 1 NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE VCC VIN Topr Tstg -0.3 to +7.0 -0.3 to V CC +0.3 -40 to +85 -65 to +150 V V °C °C 1 1, 2 Supply voltage Input voltage Operating temperature Storage temperature NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. RECOMMENDED OPERATING CONDITIONS (TA = -40 to +85°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE VCC VIH VIL VIH VIL 2.5 VCC - 0.5 -0.3 2.2 -0.3 3.0 5.5 VCC + 0.3 0.2 VCC + 0.3 0.8 V V V V V 1 Supply voltage Input voltage (VCC = 2.5 to 4.5 V) Input voltage (VCC = 4.5 to 5.5 V) NOTE: 1. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. DC CHARACTERISTICS (TA = -40 to +85°C, VCC = 2.5 to 5.5 V) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT Input leakage current ILI -1.0 1.0 µA Output leakage current ILO VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 to VCC CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V tCYCLE = CE2 = VCC - 0.2 V, 500 ns Output open CE1 = 0.2 V, VIN = 0.2 V or tCYCLE = VCC - 0.2 V CE2 = VCC - 0.2 V, 1.0 µs Output open CE1 = 0.2 V, VIN = 0.2 V or tCYCLE = VCC - 0.2 V CE2 = VCC - 0.2 V, 1.0 µs Output open, VCC = 3.3 V TA ≤ +70°C CE2 ≤ 0.2 V or CE1 ≥ VCC - 0.2 V TA ≤ +85°C CE1 = VIH or CE2 = VIL IOL = 500 µA IOH = -500 µA -1.0 1.0 µA Operating supply current ICC Standby current ISB Output Low voltage Output High voltage ISB1 VOL VOH NOTES: 1. CE2 should be ≥ VCC - 0.2 V or ≤ 0.2 V when CE1 ≥ VCC - 0.2 V. NOTE 20 10 mA 8 1.0 3.0 5 0.5 VCC - 0.5 µA 1 mA V V 2 2. VOH is 4.5 V (Min.) at VCC > 5 V. 3 CMOS 64K (8K × 8) Static RAM LH5164ASH AC CHARACTERISTICS (1) READ CYCLE (TA = -40 to +85°C, VCC = 2.5 to 5.5 V) PARAMETER SYMBOL MIN. Read cycle time tRC 500 Address access time tAA 500 ns (CE1) tACE1 500 ns (CE2) tACE2 500 ns 200 ns Chip enable access time MAX. UNIT ns Output enable access time tOE Output hold time tOH 10 ns tLZ1 tLZ2 20 20 ns ns tOLZ 10 tHZ1 0 60 ns tHZ2 0 60 ns tOHZ 0 40 ns Chip enable to output in Low-Z (CE1) (CE2) Output enable to output in Low-Z Chip enable to output in High-Z (CE1) (CE2) Output disable to output in High-Z ns (2) WRITE CYCLE (TA = -40 to +85°C, VCC = 2.5 to 5.5 V) PARAMETER SYMBOL MIN. MAX. UNIT Write cycle time tWC 500 ns Chip enable to end of write tCW 250 ns Address valid to end of write tAW 250 ns Address setup time tAS 100 ns Write pulse width tWP 150 ns Write recovery time tWR 50 ns Data valid to end of write tDW 100 ns Data hold time tDH 0 ns Output active from end of write tOW 20 WE to output in High-Z tWZ 0 60 ns OE to output in High-Z tOHZ 0 40 ns MIN. TYP. ns NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude NOTE 0 to VCC Input rise/fall time 10 ns Timing reference level 1.5 V Output load conditions CL (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. CAPACITANCE (TA = 25°C, f = 1MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT Input capacitance CIN VIN = 0 V 7 pF Input/output capacitance CI/O VI/O = 0 V 10 pF NOTE: This parameter is sampled and not production tested. 4 CMOS 64K (8K × 8) Static RAM LH5164ASH DATA RETENTION CHARACTERISTICS (TA = -40 to +85°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Data retention supply voltage VCCDR CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V 2.0 5.5 V 1 TA = 25°C 0.2 µA TA = 40°C 0.4 µA 0.6 µA VCCDR = 3 V, CE2 ≤ 0.2 V or CE1 ≥ VCCDR – 0.2 V Data retention supply current ICCDR Chip disable to data retention tCDR 0 ns tR tRC ns Recovery time 1 2 NOTES: 1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR - 0.2 V. 2. t RC = Read cycle time DATA RETENTION MODE CE1 CONTROL (NOTE) VCC tR tCDR 2.5 V VCC - 0.5 V VCCDR CE1 ≥ VCCDR - 0.2 V CE1 0V CE2 CONTROL DATA RETENTION MODE VCC 2.5 V tCDR CE2 tR VCCDR 0.2 V 0V CE2 ≥ 0.2 V NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data retention. 5164ASH-6 Figure 4. Low Voltage Data Retention 5 CMOS 64K (8K × 8) Static RAM LH5164ASH tRC A0 - A12 tAA tACE1 CE1 tLZ1 tHZ1 tACE2 CE2 tLZ2 tOE tHZ2 tOLZ OE tOHZ I/O1 - I/O8 DATA VALID tOH NOTE: WE = 'HIGH.' 5164ASH-3 Figure 5. Read Cycle 6 CMOS 64K (8K × 8) Static RAM LH5164ASH tWC A0 - A12 OE (NOTE 4) tAW tWR tCW (NOTE 2) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE tOHZ (NOTE 5) HIGH-Z DOUT tDW DIN tDH (NOTE 6) DATA VALID NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the output will remain high-impedance. 6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied. 5164ASH-4 Figure 6. Write Cycle 1 (OE Controlled) 7 CMOS 64K (8K × 8) Static RAM LH5164ASH tWC A0 - A12 tAW tWR tCW (NOTE 4) (NOTE 2) CE1 tWR tCW CE2 tWR tAS tWP (NOTE 3) (NOTE 1) WE (NOTE 5) tWZ tOW (NOTE 6) HIGH-Z DOUT tDW DIN (NOTE 7) tDH DATA VALID OE = 'LOW' NOTES: 1. The writing occurs during an overlapping of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the output will remain high-impedance. 6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the output will remain high-impedance. 7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied. 5164ASH-5 Figure 7. Write Cycle 2 (OE Low Fixed) 8 CMOS 64K (8K × 8) Static RAM LH5164ASH PACKAGE DIAGRAMS 28SOP (SOP028-P-0450) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP 9 CMOS 64K (8K × 8) Static RAM LH5164ASH 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 28 15 12.00 [0.472] 11.60 [0.457] 1 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 14 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] DETAIL 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] 0 - 10° 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP 28-pin, 8 × 13 mm2 TSOP (Type I) ORDERING INFORMATION LH5164ASH Device Type X Package N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 64K (8K x 8) Static RAM H = -40°C to +85°C Operation S = 3 V Operation Example: LH5164ASHN (CMOS 64K (8K x 8) Static RAM, 28-pin, 450-mil SOP) 10 5164ASH-7