ETC LH52256CN-70LL

LH52256C/CH
FEATURES
• 32,768 × 8 bit organization
• Access time: 70 ns (MAX.)
CMOS 256K (32K × 8) Static RAM
PIN CONNECTIONS
TOP VIEW
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
• Supply current:
Operating: 45 mA (MAX.)
10 mA (MAX.) (tRC, tWC = 1 µs)
Standby: 40 µA (MAX.)
• Data retention current: 1.0 µA (MAX.)
(VCCDR = 3 V, TA = 25°C)
• Wide operating voltage range:
4.5 V ± 5.5 V
• Operating temperature:
Commerical temperature 0°C to +70°C
Industrial temperature -40° to +85°C
A14
1
28
VCC
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O8
I/O7
I/O1
11
18
I/O2
12
17
I/O6
I/O3
13
16
I/O5
GND
14
15
I/O4
52256C-1
• Fully-static operation
Figure 1. Pin Connections
• Three-state outputs
• Not designed or rated as radiation
hardened
• Package:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8 × 3 mm2 TSOP (Type I)
• N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768 × 8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
28-PIN TSOP (Type I)
OE
1
28
A10
A11
2
27
CE
A9
3
26
I/O8
A8
4
25
I/O7
I/O6
A13
5
24
WE
VCC
6
23
I/O5
7
22
I/O4
A14
8
21
GND
A12
9
20
I/O3
A7
10
19
I/O2
A6
11
18
I/O1
A5
12
17
A0
A4
13
16
A1
A3
14
15
A2
NOTE: Reverse bend available on request.
52256C-8
Figure 2. TSOP (Type I) Pin Connections
1
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
A8 25
A14 1
A13 26
A12 2
A7
3
ROW
DECORDER
A6 4
MEMORY
ARRAY
(512 x 512)
28 VCC
14 GND
A5 5
A4
6
A3 7
11 I/O1
12 I/O2
COLUMN I/O
CIRCUIT
COLUMN
DECODER
8
13 I/O3
15 I/O4
OUTPUT
BUFFERS
8
16 I/O5
17 I/O6
18 I/O7
19 I/O8
INPUT
DATA
CONTROL
WE 27
OE 22
CE 20
10 9 8 21 24 23
A0 A1 A2 A10 A9 A11
52256C-2
Figure 3. LH52256C Block Diagram
PIN DESCRIPTION
SIGNAL
A0 - A14
2
PIN NAME
Address inputs
SIGNAL
I/O1 - I/O8
PIN NAME
Data inputs and outputs
CE
Chip enable
VCC
Power supply
WE
Write enable
GND
Ground
OE
Output enable
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
TRUTH TABLE
CE
WE
OE
MODE
I/O1 - I/O8
SUPPLY CURRENT
NOTE
H
X
X
Standby
High impedance
Standby (ISB )
1
L
H
L
Read
Data output
Active (ICC)
1
L
H
H
Output disable
High impedance
Active (ICC)
1
L
L
X
Write
Data input
Active (ICC)
1
NOTE:
1. X = Don’t care, L = Low, H = High
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
VCC
–0.5 to +7.0
V
1
Input voltage
VIN
–0.5 to VCC + 0.5
V
1, 2
Operating temperature
TOPR
0 to +70
°C

Storage temperature
TSTG
–65 to +150
°C

NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAMETER
Supply voltage
Input voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
VCC
4.5
5.0
5.5
V

VIH
2.2

VCC + 0.5
V

VIL
–0.5

0.8
V
1
NOTE:
1. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
3
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0

1.0
µA
Output leakage
current
ILO
CE = VIH or OE = VIH
VI/O = 0 V to VCC
–1.0

1.0
µA
ICC
Minimum cycle, VIN = VIL or VIH
II/O = 0 mA, CE = VIL

25
45.0
ICC1
tRC, tWC = 1 µs, VIN = VIL or VIH,
II/O = 0 mA, CE = VIL


10.0
ISB
CE ≥ VCC – 0.2 V

0.6
40.0
µA
ISB1
CE = VIH


3.0
mA
VOL
IOL = 2.1 mA


0.4
VOH
IOH = -1.0 mA
2.4


Operating supply
current
Standby current
Output voltage
mA
NOTE:
Typical values at VCC = 5.0 V, TA = 25°C
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
MODE
NOTE
0.6 V to 2.4 V

Input rise and fall time
10 ns

Input and output timing Ref. level
1.5 V

1 TTL + CL (100 pF)
1
Input pulse level
Output load
NOTE:
1. Including scope and jig capacitance.
READ CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
tRC
70

ns

Address access time
tAA

70
ns

CE access time
tACE

70
ns

Output enable to output valid
tOE

35
ns

Output hold from address change
tOH
10

ns

CE Low to output active
tLZ
10

ns
1
OE Low to output active
tOLZ
5

ns
1
CE High to output in High impedance
tHZ
0
30
ns
1
OE High to output in High impedance
tOHZ
0
30
ns
1
NOTES:
1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV
transition from steady state levels into the test load.
4
V
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
WRITE CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
tWC
70

ns

CE Low to end of write
tCW
45

ns

Address valid to end of write
tAW
45

ns

Address setup time
tAS
0

ns

Write pulse width
tWP
35

ns

Write recovery time
tWR
0

ns

Input data setup time
tDW
30

ns

Input data hold time
tDH
0

ns

WE High to output active
tOW
5

ns
1
WE Low to output in High
impedance
tWZ
0
30
ns
1
OE High to output in High
impedance
tOHZ
0
30
ns
1
NOTE:
1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV
transition from steady state levels into the test load.
CAPACITANCE (TA = 25°C, f = 1MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
CIN
VIN = 0 V


7
pF
1
I/O capacitance
CI/O
VI/O = 0 V


10
pF
1
NOTE:
1. This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (TA = 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Data retention supply voltage
VCCDR
CE ≥ VCCDR – 0.2 V
2.0

5.5
V

TA = 25°C

0.3
1.0
TA = 40°C


3.0
VCCDR = 3.0 V
Data retention supply current
ICCDR
CE ≥ VCCDR – 0.2 V
Chip enable setup time
Chip enable hold time

µA

15
tCDR

0


ns

tR

tRC


ns
1
NOTE:
1. t RC = Read cycle time.
2. Typical values at TA = 25°C
5
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
tRC
ADDRESS
tAA
tACE
CE
tLZ
tHZ
tOE
OE
tOLZ
tOHZ
tOH
DATA VALID
DOUT
NOTE: WE is HIGH for Read Cycle.
52256C-3
Figure 4. Read Cycle
6
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
tWC
ADDRESS
OE
tAW
tWR
(NOTE 4)
tWR
(NOTE 4)
tCW
(NOTE 2)
CE
tAS
tWP
(NOTE 3)
(NOTE 1)
WE
tOHZ
(NOTE 6)
DOUT
tDW
tDH
(NOTE 5)
DATA VALID
DIN
NOTES:
1. A write occurs during the overlap of a LOW CE, and a LOW WE.
A write begins at the latest transition among CE going LOW, and
WE going LOW. A write ends at the earliest transition among CE
going HIGH, and WE going HIGH. tWP is measured from the beginning
of write to the end of write.
2. tCW is measured from the later of CE going LOW to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
5. During this period, I/O pins are in the output state, therefore the input
signals of opposite phase to the outputs must not be applied.
6. If CE goes LOW simultaneously with WE going LOW or after WE going
LOW, the outputs remain in high impedance state.
7. If CE goes HIGH simulaneously with WE going HIGH or before WE
going HIGH, the outputs remain in high impedance state.
52256C-4
Figure 5. Write Cycle (OE Controlled)
7
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
tWC
ADDRESS
tAW
tWR
tCW
(NOTE 4)
(NOTE 2)
CE
tWR
tAS
tWP
(NOTE 3)
(NOTE 1)
(NOTE 4)
WE
tWZ
(NOTE 6)
tOW
(NOTE 7)
DOUT
tDW
(NOTE 5)
DIN
tDH
DATA VALID
NOTES:
1. A write occurs during the overlap of a LOW CE, and a LOW WE.
A write begins at the latest transition among CE going LOW, and
WE going LOW. A write ends at the earliest transition among CE
going HIGH, and WE going HIGH. tWP is measured from the beginning
of write to the end of write.
2. tCW is measured from the later of CE going LOW to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
5. During this period, I/O pins are in the output state, therefore the input
signals of opposite phase to the outputs must not be applied.
6. If CE goes LOW simultaneously with WE going LOW or after WE going
LOW, the outputs remain in high impedance state.
7. If CE goes HIGH simulaneously with WE going HIGH or before WE
going HIGH, the outputs remain in high impedance state.
52256C-5
Figure 6. Write Cycle (OE Low Fixed)
CE CONTROL
DATA RETENTION MODE
VCC
4.5 V
tCDR
tR
2.2 V
VCCDR
CE ≥ VCCDR - 0.2 V
CE
0V
52256C-6
Data Retention Timing Chart
CE Controlled
8
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
PACKAGE DIAGRAMS
28DIP (DIP028-P-0600)
28
15
DETAIL
13.45 [0.530]
12.95 [0.510]
1
0° TO 15°
14
0.30 [0.012]
0.20 [0.008]
36.30 [1.429]
35.70 [1.406]
15.24 [0.600]
TYP.
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
0.51 [0.020] MIN.
0.60 [0.024]
0.40 [0.016]
2.54 [0.100]
TYP.
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP-2
28SOP (SOP028-P-0450)
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
1.70 [0.067]
28
15
8.80 [0.346]
8.40 [0.331]
1
12.40 [0.488]
11.60 [0.457]
10.60 [0.417]
14
1.70 [0.067]
0.20 [0.008]
0.10 [0.004]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP
9
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
28SDIP (SDIP28-P-400)
DETAIL
28
15
8.80 [0.346]
8.40 [0.331]
1
0° TO 15°
14
0.30 [0.012]
0.20 [0.008]
25.75 [1.014]
25.25 [0.994]
10.16 [0.400]
TYP.
4.05 [0.159]
3.65 [0.144]
4.60 [0.181]
4.20 [0.205]
3.50 [0.138]
3.00 [0.118]
0.51 [0.020] MIN
1.78 [0.070]
TYP.
0.56 [0.022]
0.36 [0.014]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SDIP
28TSOP (TSOP028-P-0813)
0.28 [0.011]
0.12 [0.005]
0.55 [0.022]
TYP.
28
15
12.00 [0.472]
11.60 [0.457]
1
13.70 [0.539]
13.10 [0.516]
12.60 [0.496]
12.20 [0.480]
14
8.20 [0.323]
7.80 [0.307]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
DETAIL
1.10 [0.043]
0.90 [0.035]
1.20 [0.047]
MAX.
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
DIMENSIONS IN MM [INCHES]
10
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
0.425 [0.017]
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.00 [0.000]
28TSOP
CMOS 256K (32K × 8) Static RAM
LH52256C/CH
ORDERING INFORMATION
LL
- ##
X
LH52256C
X
Device Type Operating Package Speed Power
Temp
Low-Low-power standby
70 Access Time (ns)
Blank 28-pin, 600-mil DIP (DIP028-P-0600)
D 28-pin, 300-mil SK-DIP (DIP028-P-0300)
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813)
Blank 0° to +70°C
H -4° to +85°C
CMOS 32K x 8 Static RAM
Example: LH52256C-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 600-mil DIP)
52256C-7
11
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty
for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS
AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A
PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental
or consequential economic or property damage.
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of the Americas
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Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Fax: (360) 834-8903
http://www.sharpsma.com
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Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Fax: (49) 40 2376-2232
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SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: +81-743-65-1321
Fax: +81-743-65-1532
http://www.sharp.co.jp