BUK9006-55A TrenchMOS™ logic level FET Rev. 01 — 1 August 2003 Preliminary data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor available as a bare die using Philips General Purpose Automotive (GPA) TrenchMOS™ technology. Product availability: BUK9006-55A distributed as individual die on reel. 1.2 Features ■ 25 A testing of individual die ■ Inductive energy testing of individual die ■ Life-tested to Q101 at 175 °C ■ Automatic visual inspection. 1.3 Applications ■ Automotive systems ■ Motors, lamps and solenoids ■ 12 V and 24 V loads ■ General purpose power switching. 1.4 Quick reference data ■ EDS(AL)S ≤ 1.1 J ■ V(BR)DSS ≤ 55 V ■ Die size = 4.30 × 4.30 mm (typ) ■ RDSon(die) = 5 mΩ (typ) ■ VGS(th) = 1.5 V (typ) ■ Die thickness = 240 µm (typ). 2. Pinning information Table 1: Pinning - Bare die simplified outline and symbol Pin Description 1 gate 2 source - drain; connected to underside of die Simplified outline Symbol d 1 g 2 MBB076 03nn81 s BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage (DC) VDGR drain-gate voltage (DC) VGS gate-source voltage (DC) ID drain current (DC) Conditions RGS = 20 kΩ Min Max Unit - 55 V - 55 V - ±15 V Tmb = 25 °C; VGS = 5 V [1] - 125 A Tmb = 100 °C; VGS = 5 V [1] - 88 A - 503 A Tmb = 25 °C; pulsed; tp ≤ 10 µs IDM peak drain current Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C - 125 A Source-drain diode IDR reverse drain current (DC) Tmb = 25 °C IDRM peak reverse drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 503 A unclamped inductive load; ID = 25 A; VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω; starting Tj = 25 °C - 1.1 J [1] Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Calculated with Rth(j-mb) = 0.59 K/W. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data Rev. 01 — 1 August 2003 2 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 4. Characteristics Table 3: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 °C 55 - - V Tj = −55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 5 drain-source leakage current Tj = 25 °C 1 1.5 2 V Tj = 175 °C 0.5 - - V Tj = −55 °C - - 2.3 V Tj = 25 °C - 0.05 10 µA Tj = 175 °C - - 500 µA - 2 100 nA Tj = 25 °C - 5 6 mΩ Tj = 175 °C - - 12 mΩ - 92 - nC - 11 - nC - 43 - nC VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 8 - 4550 6020 pF - 760 900 pF - 500 690 pF VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω - 40 - nS - 175 - nS VDS = 55 V; VGS = 0 V IGSS gate-source leakage current VGS = ±15 V; VDS = 0 V RDSon(die) die drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 4 Dynamic characteristics Qg(tot) total gate charge VGS = 5 V; VDS = 44 V; ID = 25 A; Figure 10 Qgs gate-source charge Qgd gate-drain (Miller) charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 280 - nS tf fall time - 167 - nS - 0.85 1.2 V Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 11 trr reverse recovery time Qr recovered charge IS = 20 A; dIS/dt = −100 A/µs VGS = −10 V; VDS = 30 V 70 - ns 160 - nC © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data - Rev. 01 — 1 August 2003 3 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 03nn87 400 10 8 6 ID (A) 5 RDSon (mΩ) 4.8 300 03nn86 9 Label is VGS (V) 8 4.6 4.4 4.2 4 200 7 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 100 0 0 2 6 5 4 6 8 10 VDS (V) Tj = 25 °C; tp = 300 µs 0 VGS (V) 15 Fig 2. Drain-source on-state resistance as a function of gate-source voltage; typical values. 03nn88 20 Label is VGS (V) RDSon (mΩ) 15 10 Tj = 25 °C; ID = 25 A Fig 1. Output characteristics: drain current as a function of drain-source voltage; typical values. 3 3.2 3.4 3.6 3.8 5 03ne89 2 a 1.5 4 1 5 10 0.5 10 5 0 0 100 200 300 ID (A) 400 -60 0 60 120 180 Tj (°C) Tj = 25 °C; tp = 300 µs R DSon a = ---------------------------R DSon ( 25 °C ) Fig 3. Drain-source on-state resistance as a function of drain current; typical values. Fig 4. Normalized drain-source on-state resistance factor as a function of junction temperature. Remark: Figures 1, 2, and 3 measured on die assembled in SOT78 with 3 x 350 µm source bond wires. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data Rev. 01 — 1 August 2003 4 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 03aa33 2.5 max ID (A) 10-2 typ 10-3 VGS(th) (V) 2 1.5 03aa36 10-1 min min 1 10-5 0 10-6 0 60 max 10-4 0.5 -60 typ 120 Tj (°C) 180 0 1 2 3 VGS (V) Tj = 25 °C; VDS = VGS ID = 1 mA; VDS = VGS Fig 5. Gate-source threshold voltage as a function of junction temperature. 03nn84 120 Fig 6. Sub-threshold drain current as a function of gate-source voltage. 03nn89 12000 gfs (S) Ciss C (pF) Coss 80 8000 Crss 40 4000 0 0 20 40 60 80 0 10-2 10-1 ID (A) 102 10 VDS (V) Tj = 25 °C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 7. Forward transconductance as a function of drain current; typical values. Fig 8. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data 1 Rev. 01 — 1 August 2003 5 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 03nn85 100 03nn83 5 VGS (V) ID (A) 4 75 VDD = 14 V 3 VDD = 44 V 50 2 25 Tj = 175 °C 1 Tj = 25 °C 0 0 0 1 2 3 VGS (V) 4 0 25 50 75 QG (nC) 100 Tj = 25 °C; ID = 25 A VDS = 25 V Fig 9. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 10. Gate-source voltage as a function of gate charge; typical values. 03nn82 100 IS (A) 75 50 25 Tj = 175 °C Tj = 25 °C 0 0.0 0.3 0.6 0.9 1.2 VSD (V) VGS = 0 V Fig 11. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Remark: Figures 9, 10, and 11 measured on die assembled in SOT78 with 3 x 350 µm source bond wires. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data Rev. 01 — 1 August 2003 6 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 5. Bare die outline G H D L M P−P N Drain connection made to underside. A F 2 1 B E P P TYPICAL DIMENSIONS UNIT A B D E F G mm 4.30 4.30 3.36 3.62 0.54 0.4 H L 0.096 0.175 M 0.27 N 0.24 ± 0.025 03nn80 Fig 12. Bare die outline. Table 4: Bare die information Parameter Description Top-side metallization (gate and source bond pads) 5 µm Al + 1 % Si (sputtered) Back-side metallization (drain contact) 0.1 µm Ti / 0.3 µm Ni / 0.1 µm Ag (evaporated) Passivation layer 1 µm Si3N4 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data Rev. 01 — 1 August 2003 7 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 6. Revision history Table 5: Revision history Rev Date 01 20030801 CPCN Description - Preliminary data (9397 750 11571) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Preliminary data Rev. 01 — 1 August 2003 8 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET 7. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 8. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 10. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 9. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Preliminary data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 11571 Rev. 01 — 1 August 2003 9 of 10 BUK9006-55A Philips Semiconductors TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick reference data. . . . . . . . . . . . . . . . . . . . . Pinning information . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 2 3 7 8 9 9 9 9 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 1 August 2003 Document order number: 9397 750 11571