TI CDCM1802RGTR

CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
D Distributes One Differential Clock Input to
EN
S1
Vss
S0
16
15
14
13
11
Y0
IN
3
10
Y0
VBB
4
9
VDD0
8
2
Vdd1
IN
7
VDD0
Y1
D
D
12
6
D
1
Vss
D
D
VDDPECL
5
D
Vss
D
One LVPECL Differential Clock Output and
One LVCMOS Single-Ended Output
Programmable Output Divider for Both
LVPECL and LVCMOS Outputs
1.6-ns Output Skew Between LVCMOS and
LVPECL Transitions Minimizing Noise
3.3-V Power Supply (2.5-V Functional)
Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
Differential Input Stage for Wide
Common-Mode Range Also Provides VBB
Bias Voltage Output for Single-Ended Input
Signals
Receiver Input Threshold ±75 mV
16-Pin QFN Package (3 mm x 3 mm)
QFN PACKAGE
(TOP VIEW)
description
The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock
output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50-Ω
transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise
impact during signal transitions.
The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are
3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The
CDCM1802 is characterized for operation from −40°C to 85°C.
For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected
to the unused input as a common-mode voltage reference.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
functional block diagram
IN
IN
LVCMOS
Div 1
Div 2
Div 4
Div 8
Y1
Y0
LVPECL
Y0
VBB
Bias
Generator
VDD - 1.3 V
(imax < 1.5 mA)
Control
S1
S0
2
EN
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
Terminal Functions
TERMINAL
I/O
DESCRIPTION
16
I
(with 60-kΩ pullup)
ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three
different configurations: tie to GND (logic 0), external 60-kΩ pulldown resistor (pull to
VDD/2) or left floating (logic 1); EN = 1: outputs on according to S0 and S1 setting EN =
VDD/2: outputs on according to S0 and S1 setting EN = 0; outputs Y[1:0] off
(high-impedance) see Table 1 for details.
IN
IN
2
3
I
Differential input
Differential input clock. Input stage is sensitive and has a wide common mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,
CML, HSTL). Since the input is high-impedance, it is recommended to terminate the PCB
transmission line before the input (e.g. with 100-Ω across input). The input can also be
driven by a single-ended signal, if the complementary input is tied to a dc reference
voltage (e.g. VCC/2).
The inputs deploy an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through this inputs is
possible and must be prevented by limiting the input voltage < VDD
S0
S1
13
15
I
I
(with 60-kΩ pullup)
Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers
three different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull
to VDD/2) or left floating (logic 1); see Table 1 for details
Y1
7
O
LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock
IN based on the selected mode of operation: S0, S1, and EN. Also, this output can be
disabled by tying VDD1 to GND.
Y0
Y0
10
11
O
LVPECL
LVPECL clock output. This output provides a copy of IN or a divided down copy of clock
IN based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the
output can simply be left open to save power and minimize noise impact to Y1.
VBB
4
O
Output bias voltage used to bias unused complementary input IN for single-ended input
signals. The output voltage of VBB is VDD −1.3 V. When driving a load, the output current
drive is limited to about 1.5 mA.
NAME
NO.
EN
VSS
5, 6, 14
Supply
Device ground
VDDPECL
1
Supply
Supply voltage PECL input + internal logic
VDD0
9, 12
Supply
PECL output supply voltage for output Y0;
Y0 can be disabled by pulling VDD0 to GND.
Caution: In this mode no voltage from outside may be forced because internal diodes
could be forced in a forward direction. Thus, it is recommended to leave the output
disconnect
VDD1
8
Supply
Supply voltage CMOS output; The CMOS output can be disabled by pulling VDD1 to GND.
Caution: In this mode no voltage from outside may be forced, because internal diodes
could be forced in forward direction. Thus, it is recommended to leave Y1 unconnected,
tied to GND or terminated into GND
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3
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
control pin settings
The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings.
All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place
them into a high-z (or tristate) output state when pulled to GND.
Setting for Mode 4:
EN = VDD/2
S1 = 0
S0 = 1
CDCM1802
REN = 60 kΩ
EN
RS1 = 0
S1
RS0 = Open
S0
Figure 1. Control Pin Setting for Example
Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
VDD/2, the installed resistor needs a value of 60 kΩ with a tolerance better or equal to 10%.
Table 1. Selection Mode Table
LVPECL
LVCMOS
MODE
EN
S1
S0
Y0
Y1
0
0
X
X
Off (high-z)
Off (high-z)
1
VDD/2
0
VDD/2
÷1
÷1
2
VDD/2
VDD/2
1
÷1
÷2
3
1
0
0
÷1
÷4
4
VDD/2
0
1
÷2
÷2
5
1
0
1
÷2
÷4
6
VDD/2
0
0
÷4
÷4
7
VDD/2
1
0
÷4
÷8
8
VDD/2
VDD/2
VDD/2
÷8
÷1
9
1
1
0
÷8
÷4
10
1
1
1
Off (high-z)
÷4
NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused
LVPECL output Y0 unconnected, then the current consumption is minimized and
noise impact to remaining outputs is neglectable. Also, each output can be
individually disabled by connecting the corresponding VDD input to GND.
4
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
VDD
Supply voltage
VI
Input voltage
−0.2 V to (VDD +0.2 V)
−0.3 V to 3.8 V
VO
Output voltage
−0.2 V to (VDD +0.2 V)
Yn, Yn, IOSD
Differential short circuit current
ESD
Electrostatic discharge (HBM 1.5 kΩ, 100 pF)
Continuous
>2000 V
Moisture level 16-pin QFN package (solder reflow temperature of 235°C) MSL
†
Tstg
Storage temperature
TJ
Maximum junction temperature
1
−65°C to 150°C
125°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
TYP
MAX
3
3.3
3.6
V
2.375
3.6
V
−40
85
°C
Supply voltage, VDD
Supply voltage, VDD (only functionality)
Operating free-air temperature, TA
UNIT
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
LVPECL INPUT IN, IN
fclk
Input frequency
0
800
VCM
High-level input common mode
1
VDD−0.3
VIN
Input voltage swing between IN and IN,
See Note 1
500
1300
mV
VIN
Input voltage swing between IN and IN,
See Note 2
150
1300
mV
IIN
Input current
RIN
Input impedance
CI
Input capacitance at IN, IN
VI = VDD or 0 V
±10
300
V
µA
kΩ
1
pF
LVPECL OUTPUT DRIVER Y0, Y0
fclk
Output frequency, See Figure 4
0
800
VOH
High-level output voltage
Termination with 50 Ω to VDD−2 V
VDD−1.18
VDD–0.81
V
VOL
Low-level output voltage
Termination with 50 Ω to VDD−2 V
VDD−1.98
VDD–1.55
V
VO
Output voltage swing between Y and Y,
See Figure 4
Termination with 50 Ω to VDD−2 V
500
IOZL
Output 3-state
VDD = 3.6 V, VO = 0 V
IOZH
Output 3-state
VDD = 3.6 V, VO = VDD – 0.8 V
tr/tf
Rise and fall time
20% to 80% of VOUTPP, see Figure 9
tDuty
Output duty cycle distortion, See Note 3
Crossing point-to-crossing point distortion
tsk(pp)
Part-to-part skew
Any Y0, See Note A in Figure 8
CO
Output capacitance
VO = VDD or GND
LOAD
Expected output load
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MHz
mV
5
µA
10
µA
200
350
ps
−50
50
ps
50
ps
1
pF
50
Ω
5
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER
tpd(lh)
Propagation delay rising edge
VOX to VOX
320
600
ps
tpd(hl)
Propagation delay falling edge
VOX to VOX
320
600
ps
tsk(p)
LVPECL pulse skew, See Note B in Figure 8
VOX to VOX
100
ps
NOTES: 1. Is required to maintain ac specifications
2. Is required to maintain device functionality
3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.
LVCMOS OUTPUT PARAMETER, Y1
PARAMETER
TEST CONDITIONS
fclk
Output frequency, see Note 4 and
Figure 5
tskLVCMOS(o)
Output skew between the LVCMOS
output Y1 and LVPECL output Y0
VOX to VDD/2, See Figure 8
tsk(pp)
Part-to-part skew
Y1, See Note A in Figure 8
VOH
VOL
High-level
High
level output voltage
Low-level
Low
level output voltage
MIN
TYP
0
MAX
UNIT
200
MHz
1.6
ns
300
ps
VDD = min to max,
IOH = −100 µA
VDD–0.1
VDD = 3 V,
IOH = −6 mA
VDD = 3 V,
IOH = −12 mA
VDD = min to max,
IOL=100 µA
0.1
VDD = 3 V,
IOL = 6 mA
0.5
VDD = 3 V,
IOL = 12 mA
0.8
2.4
V
2
IOH
High-level output current
VDD = 3.3 V,
VO = 1.65 V
−29
IOL
Low-level output current
VDD = 3.3 V,
VO = 1.65 V
37
IOZ
High-impedance state output current
VDD = 3.6 V,
VO = VDD or 0 V
CO
Output capacitance
VDD = 3.3 V
Load
Expected output loading, see Figure 10
tDuty
Output duty cycle distortion, see Note 5
Measured at VDD/2
tpd(lh)
Propagation delay rising edge from IN
to Y1
tpd(hl)
V
mA
mA
±5
2
µA
pF
10
pF
−150
150
ps
VOX to VDD/2 load, see Figure 10
1.6
2.6
ns
Propagation delay falling edge from IN
to Y1
VOX to VDD/2 load, see Figure 10
1.6
2.6
ns
tr
Output rise slew rate
20% to 80% of swing, see Figure 10
1.4
2.3
V/ns
tf
Output fall slew rate
80% to 20% of swing, see Figure 10
1.4
2.3
V/ns
NOTES: 4. Operating the CDCM1802 LVCMOS output above the maximum frequency will not cause a malfunction to the device, but the Y1
output signal swing will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1802 can be operated
at higher frequencies, while the LVCMOS output Y1 becomes unusable.
5. For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.
6
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
jitter characteristics
PARAMETER
tjitterLVPECL
tjitterLVCMOS
TEST CONDITIONS
Additive phase jitter from input to
LVPECL output Y0,
Y0
See Figure 2
Additive phase jitter from input to
LVCMOS output Y1,
Y1
See Figure 3
−120
UNIT
0.25
12 kHz to 20 MHz, fout = 250 MHz,
divide by 1 mode
0.25
ps rms
50 kHz to 40 MHz, fout = 250 MHz,
divide by 1 mode
0.4
ps rms
ps rms
ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER − LVCMOS
−100
VDD = 3.3 V
TA = 25°C
f = 622 MHz
÷1 Mode
VDD = 3.3 V
TA = 25°C
f = 250 MHz
÷1 Mode
−105
−110
−125
−130
−135
−140
−145
−150
−155
−160
10
MAX
50 kHz to 40 MHz, fout = 250 MHz to 800 MHz,
divide by 1 mode
Additive Phase Noise − dBc/Hz
Additive Phase Noise − dBc/Hz
−115
TYP
0.15
ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER − LVPECL
−110
MIN
12 kHz to 20 MHz, fout = 250 MHz to 800 MHz,
divide by 1 mode
−115
−120
−125
−130
−135
−140
−145
−150
−155
100
1k
10k
100k
1M
10M
100M
f − Frequency Offset From Carrier − Hz
−160
10
100
1k
10k 100k
1M
10M
f − Frequency Offset From Carrier − Hz
Figure 2
100M
Figure 3
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7
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
jitter characteristics (continued)
AMPLITUDE CMOS PEAK-TO-PEAK
vs
FREQUENCY
AMPLITUDE PECL PEAK-TO-PEAK
vs
FREQUENCY
0.90
3.5
3.6 V
Amplitude CMOS Peak-to-Peak − V
Amplitude PECL Peak-to-Peak − V
0.85
3V
0.80
3.3 V
0.75
0.70
3.6 V
2.375 V
0.65
0.60
2.625 V
0.55
0.50
0.45
Mode = 1 (Divider: Y0 = 1, Y1 = 1 )
Input Swing = 500 mV
Load = See Figure 11
0.40
0.1
0.3
0.5
0.7
0.9
2.5 V
1.1
1.3
1.5
3.0
3.3 V
2.5
3V
2.0
2.625 V
1.5
2.5 V
1.0
Mode = 1 ( divider: Y0 = 1, Y1 = 1 )
Input Swing = 500 mV
Load = See Figure 10
0.5
0.0
50
2.375 V
100 150 200 250 300 350 400 450 500
f − Frequency − MHz
f − Frequency − GHz
Figure 4
Figure 5
supply current electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Full load
IDD
Supply current
No load
IDDZ
8
Supply current, 3-state
All outputs enabled and terminated with 50 Ω to
VDD − 2 V on LVPECL outputs and 10 pF on LVCMOS output,
f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS,
VDD = 3.3 V
MIN
TYP
MAX
100
mA
Outputs enabled, no output load, f = 800 MHz for LVPECL outputs
and 200 MHz for LVCMOS, VDD = 3.6 V
85
All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V
0.5
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UNITS
mA
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
SUPPLY CURRENT
vs
FREQUENCY
110
CMOS and PECL Running (Mode 3)
ICC − Supply Current − mA
100
90
80
70
CMOS Off, PECL Running
60
CMOS Running,
PECL Off (Mode 10)
CMOS and PECL
Running, No Load
50
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
f − Frequency − GHz
NOTE: Input swing = 500 mV
Figure 6
Package Thermal Resistance
PARAMETER
θJA
QFN−16 package thermal resistance
with thermal vias in PCB, See Note 1
TEST CONDITIONS
4-layer JEDEC test board (JESD51−7) with four
thermal vias of 22-mil diameter each,
airflow = 0 ft/min
MIN
TYP
MAX
40.8
UNIT
°C/W
NOTE 1: It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good
heat sink.
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax x Vmax = 85 mA x 3.6 V = 306 mW (max power consumption inside the package)
∆TJunction = θJA x Peffective = 40.8°C/W x 306 mW = 12.48°C
TJunction = ∆TJunction + TChassis = 12.48°C + 85°C = 97.48°C (the maximum junction temperature of Tdie−max
= 125°C is not violated)
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9
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
control input characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tsu
Setup time, S0, S1, and EN pin before clock IN
25
ns
th
Hold time, S0, S1, and EN pin after clock IN
t(disable)
Time between latching the EN low transition and when all
outputs are disabled (how much time is required until the
outputs turn off)
0
ns
10
ns
t(enable)
Time between latching the EN low-to-high transition and
when outputs are enabled based on control settings (how
much time passes before the outputs carry valid signals)
1
µs
Rpullup
Internal pullup resistor on S0, S1, and EN input
VIH(H)
Three level input high, S0, S1, and EN pin, see Note 1
0.9xVDD
VIM(M)
Three level input MID, S0, S1, and EN pin
0.3xVDD
VIL(L)
Three level low, S0, S1, and EN pin
IIH
Input current, S0, S1, and EN pin
VI = VDD
IIL
Input current, S0, S1, and EN pin
VI = GND
42
60
78
kΩ
V
0.7xVDD
V
0.1xVDD
V
−5
µA
85
µA
38
NOTES: 1. Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.
bias voltage VBB over recommended operating free-air temperature range
PARAMETER
VBB
TEST CONDITIONS
Output reference voltage
MIN
VDD = 3 V − 3.6 V, IBB = −0.2 mA
VDD − 1.4
OUTPUT REFERENCE VOLTAGE (VBB)
vs
LOAD
4.0
VDD = 3.3 V
VBB − Output Reference Voltage − V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−5
0
5
10
15
20
25
30
I − Load − mA
Figure 7
10
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35
TYP
MAX
VDD − 1.2
UNITS
V
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
IN
IN
Y0
Y0
tPHLO
0.5 X VDD1
Y1
tskLVCMOS(o)
NOTES: A. Part-to-part skew, tsk(pp), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n across multiple devices
− The difference between the fastest and the slowest tpd(HL)n across multiple devices
B. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high
(tpd(LH)) propagation delays when a single switching input causes Y0 to switch, tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew is sometimes
referred to as pulse width distortion or duty cycle skew.
Figure 8. Waveforms for Calculation of tsk(o) and tsk(pp)
Yn
VOH
Yn
VOL
80%
VOUT(pp)
0V
20%
|Yn*Yn|
tr
tf
Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
CDCM1802
VCC
1 kΩ
Y1
LVCMOS
10 pF
1 kΩ
Figure 10. LVCMOS Output Loading During Device Test
CDCM1802
(VDD − 2 V)
50 Ω
LVPECL
Y0, Y0
Figure 11. LVPECL Output Loading During Device Test
PCB design for thermal functionality
It is recommended to take special care of the PCB design for good thermal flow from the QFN−16 pin package
to the PCB. The current consumption of the CDCM1802 is fixed. JEDEC JESD51−7 specifies thermal
conductivity for standard PCB boards.
Modeling the CDCM1802 with a 4−layer JEDEC board (including four thermal vias) results into 37.5_C max
temperature with a θJA of 40.84_C for 25_C ambient temperature.
To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications.
12
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CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
Package Thermal Pad
(Underside)
Thermal Via
Dia 0.020 In.
Top Side
Island
Heat
Dissipation
VSS Copper Plane
VSS Copper Plane
Figure 12. Recommended Thermal Via Placement
See the SCBA017 and the SLUA271 application notes for further package related information.
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13
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
APPLICATION INFORMATION
LVPECL receiver input termination
The input of the CDCM1802 has high impedance and comes with a very large common mode voltage range.
For optimized noise performance it is recommended to properly terminate the PCB trace (transmission line).
Additional termination techniques can be found in the following application notes: SCAA062 and SCAA059.
http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa062
http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa059
CDCM1802
CAC
IN
50 Ω
LVPECL
50 Ω
150 Ω
50 Ω
CAC
IN
50 Ω
VBB
150 Ω
C
Figure 13. Recommended AC-Coupling LVPECL Receiver Input Termination
CDCM1802
130 Ω
50 Ω
LVPECL
83 Ω
130 Ω
50 Ω
83 Ω
Figure 14. Recommended DC-Coupling LVPECL Receiver Input Termination
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
APPLICATION INFORMATION
CDCM1802
CAC
IN
CLK
Rdc
IN
VBB
CCT
NOTE: CAC − AC-coupling capacitor (e.g., 10 nF)
CCT − Capacitor keeps voltage at IN constant (e.g., 10 nF)
Rdc − Load and correct duty cycle (e.g., 50 Ω)
VBB − Bias voltage output
Figure 15. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1802
device behavior during RESET and control pin switching
output behavior when enabling the device (EN = 0 % 1)
In disable mode (EN = 0), all output drivers are switched in high-Z mode. The bandgap, current references, the
amplifier, and the S0 and S1 control inputs are also switched off. In the same mode, all flip-flops will be reset.
The typical current consumption is likely below 500 µA (to be measured).
When the device will be enabled again it takes maximal 1 µs for the settling of the reference voltage and currents.
During this time the output Y0 and Y0 drive a high signal. Y1 is unknown (could be high or low). After the settle
time, the outputs go into the low state. Due to the synchronization of each output driver signal with the input
clock, the state of the waveforms after enabling the device look like those shown in Figure 16. The inverting input
and output signal is not included. The Y:/1 waveform is the undivided output driver state.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
APPLICATION INFORMATION
1 µs
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = Low)
1 µs
Undivided State is Valid After the First
Positive Transition of the Input Clock
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = High)
Figure 16. Waveforms
16
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• DALLAS, TEXAS 75265
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
APPLICATION INFORMATION
enabling a single output stage
If a single output stage becomes enabled:
1. Y0 will either be low or high (undefined).
2. Y0 will be the inverted signal of Y0.
With the first positive clock transition, the undivided output becomes the input clock state. If a divide mode is
used, the divided output states are equal to the actual internal divider. The internal divider does not get a reset
while enabling single output drivers.
ENABLE Yx:
Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
Figure 17. Signal State After an Output Driver Becomes Enabled While IN = 0
ENABLE Yx:
Disabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
Enabled
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
Figure 18. Signal State After an Output Driver Becomes Enabled While IN = 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
CDCM1802
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,
LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 − APRIL 2004
MECHANICAL DATA
Also see the following two application notes for further package related information.
http://focus.ti.com/lit/an/scba017c/scba017c.pdf
http://focus.ti.com/lit/an/slua271/slua271.pdf
1.55
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1) All linear dimensions are in millimeters
2) The pin 1 indentification mark is electrically connected to the center thermal pad
4206349-3/B 11/04
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCM1802RGTR
ACTIVE
QFN
RGT
16
3000
TBD
CU NIPDAU
Level-1-235C-UNLIM
CDCM1802RGTT
ACTIVE
QFN
RGT
16
250
TBD
CU NIPDAU
Level-1-235C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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