CGS2534V Commercial/CGS2534TV Industrial Quad 1 to 4 Clock Drivers General Description Features These Clock Generation and Support clock drivers are specifically designed for driving memory arrays requiring large fanouts while operating at high speeds, CGS2534 is a 4 to 16 inverting driver with TTL compatible I/Os. This device has skew specifications of 350 ps pin-topin as well as a 650 ps specification for part-to-part propagation delay variation. Y Y Y Y Y Y Y Y Y Guaranteed and tested: 350 ps pin-to-pin skew (tOSHL and tOSLH) 650 ps part-to-part variation on positive or negative transition Implemented on National’s ABT family process Symmetric output current drive: b36/36 mA IOH/IOL Industrial temperature of b40§ C to a 85§ C 28-pin PLCC for optimum skew performance Symmetric package orientation Large fanout for memory driving applications Guaranteed 2 kV ESD protection Connection Diagrams Pin Assignment for 28-Pin PLCC TL/F/11921 – 5 CGS2534 Truth Table Input Output ln(0 – 3) ABCD Out (0–3) TL/F/11921 – 1 C1995 National Semiconductor Corporation TL/F/11921 RRD-B30M115/Printed in U. S. A. CGS2534V Commercial/CGS2534TV Industrial Quad 1 to 4 Clock Drivers September 1995 Absolute Maximum Ratings (Note) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (VI) Input Current Current Applied to Output (High/Low) Operating Temperature Industrial Grade Commercial Grade Supply Voltage (VCC) b 40§ C to a 85§ C 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Airflow 0 LFM 225 LFM 500 LFM Typical iJA 62§ C/W 43§ C/W 34§ C/W 27§ C/W 900 LFM 4.5V to 5.5V Maximum Input Rise/Fall Time (0.8V to 2.0V) 5 ns Free Air Operating Temperature (TA) b 40§ C to a 85§ C Industrial Commercial 0§ C to a 70§ C Note: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. 7.0V 7.0V b 30 mA twice the rated IOH/IOL mA DC Electrical Characteristics Over recommended operating conditions unless otherwise specified. All typical values are measured at VCC e 5V, TA e 25§ C Symbol Parameter Conditions Min VIL Input Low Level Voltage VIH Input High Level Voltage VIK Input Clamp Voltage VCC e 4.5V, II e b18 mA VOH High Level Output Voltage (Note 5) IOH e b3 mA, VCC e 4.5V 2.4 IOH e b36 mA, VCC e 4.5V 2.0 VOL Input Current IIH Max Unit 0.8 V b 1.2 V 2.0 Low Level Output Voltage (Note 5) II Typ V VCC e 4.5V, IOL e 36 mA 0.4 0.5 VCC e 4.5V, IOL e 50 mA 0.1 0.1 V VCC e 5.5V, VIH e 7V 7 High Level Input Current VCC e 5.5V, VIH e 2.7V 5 IIL Low Level Input Current VCC e 5.5V, VIL e 0.4V IOS Output Drive Current VCC e 5.5V, VO e 0V IOLD Minimum Dynamic Output Current (Note 1) VCC e 5.5V, VOLD e 0.8V IOHD Minimum Dynamic Output Current (Note 1) VCC e 5.5V, VOHD e 2.0V ICCT Maximum ICC/Input VCC e 5.5V 3.6 mA ICC Supply Current ’2534 (Quiescent) VCC e 5.5V 235 mA CIN Input Capacitance VCC e 5V @ Max Input Voltage V Note 1: Maximum test duration 2.0 ms, one output loaded at a time. 2 b5 mA mA mA b 100 275 mA 70 mA b 90 mA 5 pF AC Electrical Characteristics Over recommended operating conditions unless otherwise specified. All typical values are measured at VCC e 5V, TA e 25§ C CGS2534 Symbol TA e a 25§ C CL e 50 pF RL e 500X Parameter Min Typ TA e b40§ C to a 85§ C CL e 50 pF RL e 500X Max Min Typ Unit Max fMAX Frequency Maximum tPLH Low-to-High Propagation Delay INn to OUTn 3.5 3.5 ns tPHL High-to-Low Propagation Delay INn to OUTn 3.5 3.5 ns tOSHL Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 350 300 350 ps Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 350 300 350 ps 1.5 ns tOSLH 125 MHz tRISE, tFALL Rise/Fall Time (from 0.8V/2.0V to 2.0V/0.8V) tHIGH tLOW Pulse Width Duration High Pulse Width Duration Low (Note 4) tPVLH Part-to-Part Variation of Low-to-High Transitions (Note 3) 650 650 ps tPVHL Part-to-Part Variation of High-to-Low Transitions (Note 3) 650 650 ps 1.5 4 4 4 4 ns Note 2: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Limits are guaranteed by design. Note 3: Part to Part transition variation is defined as the absolute difference between the propagation delay of any output on one device to any output on another device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tPVHL) or LOW to HIGH (tPVLH). Limits are guaranteed by design. Note 4: Time high is measured at 2.0V, time low is measured at 0.8V. Note 5: For increased drive, output pins may be connected together when the corresponding input pins are connected together. Timing Information TL/F/11921 – 2 3 CGS2534/35/36/37 Memory Array Driving Also this larger fan-out helps to save board space since for every one of these drivers, two conventional buffers were typically being used. Another feature associated with these clock drivers is a 350 ps pin-to-pin skew specification. The minimum skew specification allows high speed memory system designers to optimize the performance of their memory sub-system by operating at higher frequencies without having concerns about output-to-output (bank-to-bank) synchronization problem which are associated with driving high capacitive loads (Point B). The diagram below depicts a ‘‘2534/35/36/37’’ a memory subsystem operating at high speed with large memory capacity. The address bus is common to both the memory and the CPU and I/Os. These drivers can operate beyond 125 MHz, and are also available in 3V – 5V TTL/CMOS versions with large current drive . In order to minimize the total load on the address bus, quite often memory arrays are being driven by buffers while having the inputs of the buffers tied together. Although this practice was feasible in the conventional memory designs, in today’s high speed, large buswidth designs which require address fetching at higher speeds, this technique produces many undesired results such as cross-talk and over/undershoot. CGS2534/35/36/37 Quad 1 to 4 Clock Drivers were designed specifically to address these application issues on high speed, large memory arrays systems. These drivers are optimized to driver large loads, with 3.5 ns propagation delays. These drivers produce less noise while reducing the total capacitive loading on the address bus by having only four inputs tied together (see the diagram below, point A). This helps to minimize the overshoot and undershoot by having only four outputs being switched simultaneously. Device VCC I/O 2534 5 TTL Output Configuration 2535 3 or 5 CMOS Non-inverting quad 1–4 2536 3 or 5 CMOS Inverting, Non-inverting, d 2 2537 5 TTL Inverting quad 1–4 Inverting quad 1–4 with series 8X output resistors TL/F/11921 – 7 4 5 CGS2534V Commercial/CGS2534TV Industrial Quad 1 to 4 Clock Drivers Physical Dimensions inches (millimeters) 28 Lead Molded Plastic Leaded Chip Carrier Order Number CGS2534V, CGS2534TV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.