N CLC522 Wideband Variable-Gain Amplifier General Description Features The CLC522 variable gain amplifier (VGA) is a dc-coupled, twoquadrant multiplier with differential voltage inputs and a single-ended voltage output. Two input buffers and an output operational amplifer are integrated with the multiplier core to make the CLC522 a complete VGA system that does not require external buffering. ■ 330MHz signal bandwidth: Avmax = 2 165MHz gain-control bandwidth 0.3° to 60MHz linear phase deviation 0.04% (-68dB) signal-channel non-linearity >40dB gain-adjustment range Differential or single-end voltage inputs Single-ended voltage output ■ ■ ■ ■ ■ ■ The CLC522 provides the flexibility of externally setting the maximum gain with only two external resistors. Greater than 40dB gain control is easily achieved through a single high impedance voltage input. The CLC522 provides a linear (in Volts per Volt) relationship between the amplifier's gain and the gain-control input voltage. Applications Variable attenuators Pulse amplitude equalizers HF modulators Automatic gain control & leveling loops Video production switching Differential line receivers Voltage controlled filters ■ ■ ■ ■ The CLC522's maximum gain may be set anywhere over a nominal range of 2V/V to 100V/V. The gain control input then provides attenuation from the maximum setting. For example, set for a maximum gain of 100V/V, the CLC522 will provide a 100V/V to 1V/V gain control range by sweeping the gain control input voltage from +1 to -0.98V. ■ ■ ■ CLC522 Wideband Variable-Gain Amplifier June 1999 Gain vs. Gain Control Voltage (V g ) Set at a maximum gain of 10V/V, the CLC522 provides a 165MHz signal channel bandwidth and a 165MHz gain control bandwidth. Gain nonlinearity over a 40dB gain range is 0.5% and gain accuracy at A Vmax = 10V/V is typically ±0.3%. Gain (V/V) 10 0 -1.1 Gain Control Voltage, Vg (Volts) Typical Application 2nd Order Tuneable Bandpass Filter 1 = − Vin n s 2 + s Vo k = 185 . 1999 National Semiconductor Corporation Printed in the U.S.A. Rf Rg , Q= s 1.1 Pinout DIP & SOIC 1 CRb k 1 + 2 CRb C R y 2 k Rb Ry , ωo = k CR y http://www.national.com CLC522 Electrical Characteristics (V PARAMETERS Ambient Temperature CONDITIONS AJ FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 0.5Vpp Vout < 5.0Vpp gain control bandwidth Vout < 0.5Vpp gain flatness Vout < 0.5Vpp peaking DC to 30MHz rolloff DC to 30MHz linear phase deviation DC to 60MHz feedthrough 30MHz TIME DOMAIN RESPONSE rise and fall time 0.5V step 5.0V step settling time 2.0V step to 0.1% overshoot 0.5V step slew rate 4.0V step DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 2Vpp, 20MHz 3rd harmonic distortion 2Vpp, 20MHz equivalent input noise 1 to 200MHz noise floor 1 to 200MHz GAIN ACCURACY signal channel nonlinearity (SGNL) Vout = ±2Vpp gain control nonlinearity (GCNL) full range gain error (GACCU) AVmax=+10 Vg high low STATIC DC PERFORMANCE Vin voltage range common mode bias current average drift offset current average drift resistance capacitance Vg bias current average drift resistance capacitance output voltage range RL= ∞ current offset voltage AVmax=+10 average drift resistance IRgmax power supply sensitivity output referred common-mode rejection ratio input referred supply current RL= ∞ CC Ω ; Rg =182W; RL = 100Ω Ω ; Vg=+1.1V) = ±5V; AVmax = +10; Rf =1kΩ TYP +25 +25 165 150 165 120 100 120 115 95 115 110 90 110 MHz MHz MHz 3 0 0.05 0.3 - 62 0.1 0.25 1.0 - 57 0.1 0.25 1.1 - 57 0.1 0.4 1.2 -57 dB dB ° dB 4 3.2 5.0 18 15 1400 ns ns ns % V/µs 2.2 3.0 12 2 2000 MIN/MAX RATINGS 0 to +70 -40 to +85 2.9 5.0 18 15 1400 3.0 5.0 18 15 1400 UNITS °C - 50 - 65 5.8 - 152 - 44 - 58 6.2 - 150 - 44 - 56 6.5 - 149 -44 -54 6.8 - 149 dBc dBc nV/√Hz dBm1Hz 0.04 0.5 ± 0.0 + 990 - 975 0.1 2.0 ± 0.5 + 990±60 - 975±80 0.1 2.2 ± 0.5 + 990±60 - 975±80 0.1 3.0 ± 1.0 + 990±60 - 975±80 % % dB mV mV ± 2.2 9 65 0.2 5 1500 1.0 15 125 100 1.0 ± 4.0 ± 70 25 100 0.1 1.8 10 70 46 ± 1.2 21 --2.0 --650 2.0 38 --38 2.0 ± 3.7 ± 47 85 --0.2 1.37 40 59 61 ± 1.2 26 175 3.0 30 450 2.0 47 300 30 2.0 ± 3.6 ± 40 95 350 0.3 1.26 40 59 62 ± 1.4 45 275 4.0 40 175 2.0 82 600 15 2.0 ± 3.5 ± 25 120 400 0.6 1.15 40 59 63 V µA nA/°C µA nA/°C kΩ pF µA nA/°C kΩ pF V mA mV µV/°C Ω mA mV/V dB mA NOTES 1 2 2 2 2 2 2 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Ordering Information Absolute Maximum Ratings supply voltage short circuit current common-mode input voltage maximum junction temperature storage temperature lead temperature (soldering 10 sec) transistor count ±7V 80mA ±Vcc +150°C -65°C to+150°C +300°C Model 74 http://www.national.com -40°C -40°C -40°C -55°C to to to to +85°C +85°C +85°C +125°C Description 14-pin PDIP 14-pin SOIC dice dice, MIL-STD-883 Package Thermal Resistance Notes 1) AJE (SOIC) is tested/guaranteed with Rf=866Ω and Rg= 165Ω. 2) J-level, spec is 100% tested at +25°C. 3) Specified with Vin = 0.2V and Vg < 0.5Vpp. 4) Feedtrough is specified at max. attenuation (i.e Vg =-1.1V) Temperature Range CLC522AJP CLC522AJE CLC522ALC CLC522AMC Package Plastic (AJP) Surface Mount (AJE) CerDIP 2 θJC θ JA 55°C/W 35°C/W 40°C/W 100°C/W 105°C/W 95°C/W CLC522 Typical Performance (T A =+25°C, V cc =±5V, A v =+10, V g =1.1V, R L =100Ω; unless noted) Frequency Response (A V max =2) 0 -45 -90 A V =1 (V g =0V) 1 -135 -180 -270 500 Frequency (MHz) -90 A V =1 (V g =-0.8V) R g =182Ω R f = 1kΩ -135 -180 -270 200 Frequency (MHz) 40 -5 -90 R g =10.2Ω R f = 715Ω A V =1 (V g =-0.98V) -135 -180 -270 100 Frequency (MHz) 20 -65 10 -80 -95 10 6 10 7 Frequency (Hz) 10 8 SGNL vs. Vg , Gain 1 10 Frequency (MHz) 10 0 A v max = +2 R f = 2kΩ Magnitude 0.14 Gain (V/V) 0.12 0.10 0.08 0.06 A v max = +10 R f = 1kΩ -45 Phase -90 -135 -180 A v max = +100 R f = 806Ω Gain 0.02 Av max = +10 3 0 SGNL 0.04 30MHz -225 Vg =1.0V R f = 1kΩ 2 1 V o u t = 5V p p +.75 +.50 +.25 V out = 0.5V pp 0 0 -1 -.25 -2 -.50 -3 -.75 0 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 -0.9 Vg (Volts) Gain Control Settling Time & Delay A v max = + 10 Vout 2.5 V in = 0.25V DC Frequency (25MHz/div) 0 250 Ti m e ( 5 n s / d i v ) Gain Control Channel Feedthrough Short Term Settling Time .2 Vin = 0 +1V 0 100mV/div Vout (0.5V/div.) -1V V g = 1.0V Vg 0 Output 0.1 .05 0 -.05 -.1 -.2 Time (5ns/div) Time (5ns/div) -.10 -.15 -.20 -8 -7 -6 -5 -4 -3 -2 -1 0 9 10 10 10 10 10 10 10 10 10 10 Time (sec) 30 50Ω 182Ω Rs CLC522 1kΩ CL Rs 50 90 45 80 40 70 60 50 40 20 30 Ts 20 10 0 10 100 Load Capacitance, C L (pF) 3 10 0 1000 Settling Time to 0.1% (ns) 0 -.05 1kΩ 40 100 Rs (ohms) .05 Settling Time, TS, (ns), to 0.1% 2V output step V g = 1.0V A v max = +10 Vg=1.0Volt 0 100 Time (10ns/div) Settling Time vs. Gain Settling Time vs. Capacitive Load 50 A V max = + 10 2V output step V g = 1.0V -.15 V g = -1.0V Long Term Settling Time A V max = + 10 .15 Vg Input Settling Error (%) 0.9 V o = 1V pp R f = 2kΩ 35 A vmax = 5 30 25 A v max = 10 20 15 10 A v max = 20 5 0 0 2 4 6 8 10 12 Attenuation From Maximum Gain (dB) 14 http://www.national.com Small Signal (Volts) Magnitude (1dB/div) 0.16 Vo = 5Vpp V g = 1.1V Phase (deg) 0.18 Frequency (3MHz/div) Large & Small Signal Pulse Response Large Signal Frequency Response 10 Phase 0 Large signal (Volts) 10 5 V g =-1.1V -50 10 4 Rf=2kΩ -35 Rf=750Ω Rf=1kΩ A v max + 10 Vo = 2Vpp R f = 1k Vg = 1.1V Gain AVmax=+100 AVmax=+10 AVmax=+2 -20 30 0.20 Settling Error (%) -45 Magnitude (0.1dB/div) Gain (dB) 50 .10 0 Deviation from Linear Phase(0.1°/div) 10 PSRR 60 .15 Phase 1 V g =+1.1V Vo=2.5Vpp 25 70 .20 A V =A Vmax (V g =1.0V) Gain Flatness & Linear Phase Deviation 40 CMRR 80 PSRR/CMRR (dB) -45 Gain 55 90 Full Scale Non-linearity (%) 0 Feed-through Isolation PSRR and CMRR (Input Referred) 0.00 Phase 1 100 0 A V =A Vmax (V g =1.0V) Vin = 25mVpp Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) Phase Vout = 500m Vpp Gain Phase (45°/div) A V =A Vmax (V g =1.0V) Phase (45°/div) Phase (45°/div) Vout = 2Vpp Gain R g =2kΩ R f = 2.2kΩ Frequency Response (A V max =100) Frequency Response (A V max =10) CLC522 Typical Performance (T A =+25°C, V cc =±5V, A v =+10, V g =1.1V, R L =100Ω; unless noted) Differential Gain and Phase .10 .10 Gain Positive Sync .05 .05 .08 .06 .06 Phase, V g = 1.0V Gain, V g = 1.0V .04 .04 .02 .02 Voltage Noise (nV/√Hz) Differential Gain (%) .15 Phase Positive Sync Phase, V g = 0.0V .08 100 .10 4.43 MHz Positive Sync A v max = +2 DifferentialPhase (degrees) Phase Negative Sync .15 .20 .10 DifferentialPhase (degrees) Gain Negative Sync .20 Input Referred Voltage Noise vs A Vmax Differential Gain and Phase .25 4.43 MHz A v max = +10 V g = 1.0V Differential Gain (%) .25 10 Gain, V g = 0.0V 1 2 3 Number of 150Ω Loads 4 0 0 -35 -40 -40 -45 50MHz -50 -55 20MHz -60 -65 10MHz 50Ω -75 -80 -85 Vg 1.1V 5MHz -70 182Ω 522 50Ω -4 -2 0 2 4 6 Output Power (Pout, dBm) 2 3 Number of 150Ω Loads 4 1 0 3rd Harmonic Distortion vs. P out -35 Rf 1kΩ 50Ω Po 50Ω 20Ω 8 Distortion Level (dBc) Distortion Level (dBc) 2nd Harmonic Distortion vs. P out 1 Vg 1.1V 50Ω -45 -50 182Ω 522 Rf 20 50Ω 20Ω 50Ω 20MHz -55 -60 10MHz -65 -70 -75 5MHz -80 10 -85 -4 0 10 20 30 40 50 60 70 80 90 100 Maximum Gain Setting, AVmax (V/V) -1dB Compression at Maximum Gain Output Limited R f = 1.4kΩ 19 50MHz 1kΩ 50Ω Po -1dB Compression (dBm) 0 18 17 16 Input Limited R f = 900Ω 15 14 Pi 13 Rf 50 Ω 12 50 Ω 11 50 Ω Po Rg 522 20 Ω 50 Ω 10 -2 0 2 4 6 Output Power (Pout, dBm) 8 10 0 100 Frequency (MHz) Application Discussion Theory of Operation The CLC522 is a linear wideband variable-gain amplifier as illustrated in Fig 1. A voltage input signal may be applied differentially between the two inputs (+Vin, -Vin), or single-endedly by grounding one of the unused inputs. sin ce IR = Vinput g A v = 185 . ∗ Rg R f Vg + 1 ∗ Rg 2 Eq. 2 The gain of the CLC522 is therefore a function of three external variables; Rg, Rf and Vg as expressed in Eq. 2. The gain-control voltage (Vg) has a ideal input range of -1V ≤ Vg ≤ +1V. At Vg=+1V, the gain of the CLC522 is at its maximum as expressed in Eq. 3. AV max Rf = 185 . Rg Eq. 3 Notice also that Eq. 3 holds for both differential and single-ended operation. Fig. 1 Choosing Rf and Rg Rg is calculated from Eq.4. Vinput The CLC522 input buffers convert the input voltage to a current (IRg) that is a function of the differential input voltage (Vinput =+Vin - -Vin) and the value of the gainsetting resistor (Rg). This current (IRg) is then mirrored to a gain stage with a current gain of 1.85. The voltagecontrolled two-quadrant multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output amplifier is a current-feedback op amp configured as a transimpedance amplifier. It's transimpedance gain is the feedback resistor (Rf). The input signal, output, and gain control are all voltages. The output voltage can easily be calculated as seen in Eq. 1. Vg + 1 Vout = IR ∗185 . ∗ ∗R f g 2 http://www.national.com max Rg = Vinput IR is the maximum peak max gmax Eq. 4 input voltage (Vpk) determined by the application. IRgmax is the maximum allowable current through Rg and is typically 1.8mA. Once A Vmax is determined from the minimum input and desired output voltages, Rf is then determined using Eq. 5. These values of Rf and Rg are Rf = Eq. 1 4 1 ∗R g ∗ A V Eq. 5 max 185 . the minimum possible values that meet the input voltage and maximum gain constraints. Scaling the resistor values will decrease bandwidth and improve stability. terms are specified in the Electrical Characteristics table and are defined below and illustrated in Fig. 4. : error of A Vmax , expressed as ±dB. GCNL : deviation from theoretical expressed as ±%. Vg high : voltage on Vg producing A Vmax . Vg : voltage on Vg producing A V = 0V/V. low min ∆Vg , ∆Vg : error of Vg , Vg expresed as ±mV. GACCU low high high low AV AVmax ±GACCU ±GCNL Fig. 2 Fig. 2 illustrates the resulting CLC522 bandwidths as a function of the maximum and minimum input voltages when Vout is held constant at 1Vpp. AVmin ±∆Vglow Adjusting Offsets Treating the offsets introduced by the input and output stages of the CLC522 is easily accomplished with a two step process. The offset voltage of the output stage is treated by first applying -1.1Volts on Vg, which effectively ±∆Vghigh Vg Vghigh Vglow Fig. 4 Combining these error terms with Eq. 2 gives the "gain envelope" equation and is expressed in Eq. 7. From the Electrical Characteristics table, the nominal endpoint values of Vg are: Vghigh =+990mV and Vglow = -975mV. ± GACCU 10 20 Vg − Vg ± ∆Vg low low A V = A V max ± 1 − Vg 2 GCNL V ± ∆Vg − Vg ± ∆Vg high low low ghigh ( ( ) ( ) ) Eq . 7 Signal-Channel Nonlinearity Signal-channel nonlinearity, SGNL, also known as integral endpoint linearity, measures the non-linearity of an amplifier’s voltage transfer function. The CLC522's SGNL, as it is specified in the Electrical Characteristics table, is measured while the gain is set at its maximum (i.e. Vg=+1.1V). The Typical Performance Characteristics plot labled "SGNL & Gain vs Vg" illustrates the CLC522's SGNL as Vg is swept through its full range. As can be seen in this plot, when the gain as reduced from A Vmax , SGNL improves to < 0.02%(-74dB) at Vg=0 and then degrades somewhat at the lowest gains. Fig. 3 isolates the input stage and multiplier core from the output stage. As illustrated in Fig. 3, the trim pot located at R14 on the CLC522 Evaluation Board should then be adjusted in order to null the offset voltage seen at the CLC522's output (pin 10). Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated. The second step requires the absence of an input signal and matched source impedances on the two input pins in order to cancel the bias current errors. This done then +1.1Volts should be applied to Vg and the trim pot located at R10 adjusted in order to null the offset voltage seen at the CLC522's output. If a more limited gain range is anticipated, the above adjustments should be made at these operating points. Gain Errors The CLC522's gain equation as theoretically expressed in Eq. 2 must include the device's error terms in order to yield the actual gain equation. Each of the gain error Noise Fig. 5 describes the CLC522's input-refered spot noise density as a function of A Vmax . The plot includes all the noise contributing terms. At A Vmax = 10V/V, the CLC522 has a typical input-referred spot noise density (eni) of 5.8nV/√Hz. The input RMS voltage noise can be determined from the following single-pole model: VRMS = ein ∗ 157 . ∗ ( −3dB bandwidth) 5 Eq. 8 Further discussion and plots of noise and the noise model is provided in Application Note OA-23. Comlinear also provides SPICE models that model internal noise and other parameters for a typical part. http://www.national.com Voltage Noise (nV/√Hz) 100 Input Referred Voltage Noise vs A Vmax Component parasitics also influence high frequency results, therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. If socketing is necessary, it is recommended to use low impedance flush mount connector jacks such as Cambion (P/N 450-2598). 10 Application Circuits Four-Quadrant Multiplier Applications requiring multiplication, squaring or other non-linear functions can be implemented with four-quadrant multipliers. The CLC522 implements a four-quadrant multiplier as illustrated in figure 8. 1 0 10 20 30 40 50 60 70 80 Maximum Gain Setting, AVmax (V/V) 90 100 Fig. 5 Rm = Circuit Layout Considerations Please refer to the CLC522 Evaluation Board Literature for precise layout guidelines. Good high-frequency operation requires all of the de-coupling capcitors shown in Fig. 6 to be placed as close as possible to the power Rs 2Rg 1.85 Vcarrier 50Ω Vbaseband 3 Rf 2 4 RT 12 Rg RT = 50Ω CLC522 Vout 10 9 RmRs Rm-Rs 50Ω 5 6 25Ω R1 R1 = RT || Rm || Rs Fig. 8 Frequency Shaping Frequency shaping and bandwidth extension of the CLC522 can be accomplished using parallel networks connected across the Rg ports. The network shown in the Fig. 9 schematic will effectively extend the CLC522's bandwidth. Fig. 6 supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate ground plane and lowinductive power returns are also required of the layout. Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9, Fig. 7 10 and 12 as shown in Fig. 7 will assure best high frequency performance. Vref (pin 9) to ground should include a small resistor value of 25 ohms or greater to buffer the internal voltage follower. The parasitic inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or circuit oscillation. This should be treated with a small series resistor between output (pin 10) and CL (see the plot “Settling Time vs. Capacitive Load" for a recommended series resistance). http://www.national.com Fig. 9 2nd Order Tuneable Bandpass Filter The CLC522 Variable-Gain Amplifier placed into feedback loops provide signal processing functions such as 2nd order tuneable bandpass filters. The center frequency of the 2nd order bandpass illustrated on the front page is adjusted through the use of the CLC522's gaincontrol voltage, Vg. The integrators implemented with two CLC420s, provide the coefficients for the transfer function. 6 This page intentionally left blank. 7 http://www.national.com CLC522 Wideband Variable-Gain Amplifier Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 8