SONY CXA2019

CXA2019AQ
NTSC/PAL Chroma Decoder
Description
The CXA2019AQ is a bipolar IC which integrates
the luminance signal processing, chroma signal
processing, and sync signal processing functions for
NTSC/PAL system color TVs onto a single chip.
Features
• Sub picture bright and white balance can be
adjusted by using the main picture Y/C/J BGP
output as the timing pulse
• I2C BUS compatible; two bus lines (SCL, SDA)
allow various adjustments and user controls
• Countdown system eliminates need for H and V
oscillator frequency adjustment
• Non-adjusting Y system filters (chroma trap, delay
line)
• Automatic identification of color system (forced
control possible)
• Automatic identification of 50/60Hz vertical frequency
(forced control possible)
• Built-in delay line aperture correction
• Built-in dynamic picture (black expansion) function
• Combination with a non-adjusting SECAM chroma
decoder allows configuration of multiple systems
40 pin QFP (Plastic)
Applications
Color TVs
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings
(Ta = 25°C, SGND, JGND = 0V)
• Supply voltage
VCC
12
V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
1.67
W
Operating Conditions
Supply voltage
VCC
9 ± 0.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98320-PS
CLAMP
DC TRAN
23 24
33
26
27
CHROMA
DET.
AUTO
PEDESTAL
V2 PED
7
U2 PED
22 21
CLAMP
DET
SW
COLOR
U PED
U PED
V PED
V PED
NT/PAL
EXT COLOR
COLOR
Y DRIVE
Y DRIVE
Y2 DRIVE
ABL
9
ABLFILIN
Y OUT
20 V OUT
19 U OUT
18
17 SGND2
10 CP IN
∗ The sub picture bright and white balance
can be adjusted by receiving BGP or
SCP output from the main picture Y/C/J,
clamping the PINP PROC. output, and
varying the DC of the clamped portion.
13 V2 IN
12 U2 IN
11 Y2 IN
ABL CENT
Y2 DRIVE
U2 DRIVE
8
Y2 OUT
U2 DRIVE
U2 PED
V2 DRIVE
V2 DRIVE
V2 PED
28
X'TAL PIN
PHASE
SHIFT
DEM
AXIS
F.F
2fH
NT/PAL
6
29
4.43/3.58
SW
ID AXIS
PAL ID
NT/PAL
V COUNT
DOWN
14
C MODE 50/60
SHARPNESS
SHARPNESS
CHROMA
VCO
HUE
HUE
SUB HUE
DELAY
PRE OVER
40
V.SYNC
SEP
38
25
LPF
PHASE
DET.
15
SHP f0
H.DRIVE
16
30
KILLER
COLOR
KILLER
BST AMP
TOT ON
TRAP
TRAP ON
DELAY
2fH
1/32
AFC HLOCK
PHASE
DET.
32fH
VCO
1
SECAM REF
SECAM
DELAY
TOT
TRAP
AFC
2
CERA
SVCC
ACC
ACC
DET.
SUB COLOR
SUB
CONT
SECAM
H.SYNC
SEP
J Vcc
3
SCP
APC
VIDEO
SW
J GND
5
H TIM
X 443/358
S GND 31
ADRS
SUB CONT
IREF
H SYNC
39
V SYNC
X 358
CV/YC
IREF
4
V HOLD
X NTSC
CIN 32
37
V TIM
A PED
CVBS/Y IN 34
36
SDA
I2C BUS
DECORDER
SCL
35
V2 OUT
– (B_Y) OUT
– (R_Y) OUT
U2 OUT
– (B_Y) IN
–2–
– (R_Y) IN
Block Diagram
CXA2019AQ
CXA2019AQ
SECAM REF
APC
X 443/358
X 358
X NTSC
SVCC
– (R_Y) OUT
– (B_Y) OUT
– (B_Y) IN
– (R_Y) IN
Pin Configuration
30
29
28
27
26
25
24
23
22
21
S GND 31
20 V OUT
CIN 32
19
U OUT
18 Y OUT
A PED 33
CVBS/Y IN 34
17 SGND2
ADRS 35
16
SCP
SCL 36
15
H TIM
SDA 37
14
V TIM
5
6
7
8
9
10
CP IN
4
ABLFILIN
3
Y2 OUT
2
U2 OUT
1
V2 OUT
11 Y2 IN
J GND
V HOLD 40
IREF
12
JVCC
H SYNC 39
AFC
13 V2 IN
CERA
V SYNC 38
–3–
U2 IN
CXA2019AQ
Pin Description
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc Vcc
Vcc
1
CERA
10k
28k
—
1
Vcc
Vcc
2
AFC
—
3
JVCC
9.0V
Vcc
2
1.2k
32fH (500 or 503.5kHz) ceramic
oscillator connection.
46k
CR connection for AFC lag-lead filter.
Power supply.
Vcc
4
IREF
20k
1.8V
4
150
5
J GND
Connect a 10kΩ resistor between this
pin and GND.
14.4k
Jungle system (H/V) GND.
—
Vcc
200
6
7
V2 OUT
U2 OUT
Vcc
Reinput system outputs.
3V
6
20k
7
8.6k
Vcc Vcc
200
4k
Vcc
8
Y2 OUT
Reinput system output.
3V
8
8k
–4–
CXA2019AQ
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Vcc
Vcc
9
ABLFILIN
—
9
Description
ABLFIL voltage input.
Input the main picture Y/C/J ABLFIL
voltage.
37k
90k
90k
Vcc
15k
Vcc
10
CP IN
Reinput system clamp pulse input.
Input the main picture BGP (SCP).
Vth: 2.5V
—
10
1.2k
Vcc
11
11
12
13
Y2 IN
U2 IN
V2 IN
4V
12
Reinput system inputs.
Input via a capacitor.
1.2k
70k
13
Vcc
Vcc
1k
14
V TIM
—
V timing pulse output.
Outputs a 0 to 5V positive polarity
pulse.
14
20k
1k
Vcc
Vcc
1k
15
H TIM
—
H timing pulse output.
Outputs a 0 to 5V positive polarity
pulse.
15
20k
1k
–5–
CXA2019AQ
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Vcc
SCP
Vcc
1.2k
Vcc
16
Description
Outputs BGP and HBLK as SCP
(sand castle pulse).
The typ. waveform is as follows.
—
5.0V
16
BGP
2.0V
500µA
HBLK
0.3V
17
SGND2
GND.
—
Vcc
200
Vcc
18
Y OUT
Y (luminance signal) output.
Standard output level: 1.1Vp-p
3V
20k
18
6k
Vcc
200
U/V (color difference signal) outputs.
Output level: U = V = 1.2Vp-p
(In case of setting data as shown in
"I2C BUS Register Initial Settings.")
Vcc
19
20
U OUT
V OUT
3V
19
20k
20
8.6k
Vcc
21
Vcc
1.2k
Color difference signal inputs. Input
as negative polarity via a capacitor.
22
21
22
– (R_Y) IN
– (B_Y) IN
5.6V
70k
BGP
100µA
–6–
Standard input levels:
B-Y: 1.33Vp-p
R-Y: 1.05Vp-p
CXA2019AQ
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Vcc Vcc
Description
Vcc
Color difference signal outputs.
Output as negative polarity.
23
23
24
– (B_Y) OUT
– (R_Y) OUT
24
5.6V
Standard output levels:
B-Y: 0.665Vp-p
R-Y: 0.525Vp-p
1.2k
25
SVCC
9.0V
Power supply.
Vcc
Crystal oscillator connections.
Connect the PALN and 4.43MHz
crystal to Pin 28.
Connect the PALM crystal to Pin 27,
and the NTSC crystal to Pin 26.
4k
26
27
28
X NTSC
X 358
X443/358
Vcc
—
26
500
27
28
Vcc
Vcc
29
APC
—
1.2k
29
1.2k
Vcc
Vcc
Vcc
6k 10p
30
SECAM REF
1.5V
30
40k
31
S GND
25k
CR connection for APC lag-lead filter.
When the IC is set to SECAM
identification mode, the 4.43MHz VCO
oscillator waveform is output from this
pin centering on DC 1.5V.
If a 150µA current is led from this pin
during this identification mode, the IC
is set to SECAM mode. In SECAM
mode, the 4.43MHz VCO oscillator
waveform is output centering on
DC = 5V only during the VBLK
interval.
GND.
—
–7–
CXA2019AQ
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
10p
30k
Chroma signal input.
32
32
C IN
—
30k
Vcc
Vcc
Standard input level (burst level)
: 570mVp-p
Vcc
Vcc
33
A PED
—
Black peak hold for auto pedestal (black
expansion). Connect a capacitor.
20k
16k
33
20k
1.2k
Vcc
Vcc
1.2k
1.2k
34
70k
Y signal input. Input via a capacitor.
34
CVBS/Y IN
—
Standard input level: 2Vp-p
1.2k
Vcc
35
ADRS
—
35
77k
30k
–8–
This pin is used to switch the slave
address.
Vcc: 9AH
GND: 9EH
Vth = 2.5 V
CXA2019AQ
Pin
No.
Symbol
Pin
voltage
Description
Equivalent circuit
Vcc
36
37
SCL
SDA
—
36
I2C BUS SCL (Serial Clock) and SDA
(Serial Data).
Vilmax = 1.5V
Vihmin = 3V
Volmax = 0.4V
4k
37
4k
15k
Vcc
38
V SYNC
3.5V
24k
150
38
33k
V sync separation input. Input a 2Vp-p
video signal via a capacitor and
resistor.
20µA
14k
Vcc
39
H SYNC
2.5V
24k
150
39
20k
H sync separation input. Input a 2Vp-p
video signal via a capacitor and
resistor.
10µA
55k
Vcc
40
V HOLD
—
150
Peak hold for V sync separation.
Connect a capacitor.
1k
40
50k
–9–
Current consumption
1
SCP BGR: 1
SCP BGF: 1
AFC: 0
SYNCIN: SIG-H3/SIG-H4
AFC: 1
SYNCIN: SIG-H3/SIG-H4
AFC: 2
SYNCIN: SIG-H3/SIG-H4
SBLK-W
SBGP-W
∆t1
∆t2
∆t3
SCP BLK output pulse
width
SCP BGP output pulse
width
AFC gain 1
AFC gain 2
AFC gain 3
7
8
9
10
11
HTIM-H
HTIM output high level
5
HTIM-L
HTIM-W
HTIM output pulse
width
4
AFC: 0
HTIM output low level
∆fH
Horizontal sync pull-in
range
3
SVCC = JVCC = 9V
Measurement conditions
6
fH
Horizontal free-running
frequency
ICC
Symbol
2
H system items
Item
No.
– 10 –
15
16
15
15
15
3, 25
Measurement pins
∆t = t (SIG-H3) – t (SIG-H4)
t
SBGP-W
SBLK-W
HTIM-W
HTIM-L
SIG-H3, H4
HTIM-H
–400
Confirm that I2C bus register HLOCK is 1
(the pull-in range when fH is shifted from
15.734kHz).
3.2
9.6
0.0
4.5
9.3
15.50
46
Min.
HTIM output frequency
Measure the pin inflow current.
Measurement contents
Electrical Characteristics
Setting conditions • Ta = 25°C, SVCC = JVCC = 9V
• Measures the following after setting the I2C bus register as shown in "I2C BUS Register Initial Settings".
1.2
0.6
0.4
3.8
10.5
0.1
4.85
9.9
15.65
68
Typ.
4.3
11.2
0.5
5.1
10.4
400
15.85
94
Max.
µs
µs
µs
µs
µs
V
V
µs
Hz
kHz
mA
Unit
CXA2019AQ
Item
VTIM-H
VTIM-L
fV2
VTIM output high level
VTIM output low level
Vertical free-running
frequency 2
13
14
15
Y2 IN: SIG-Y1
Y2 DRIVE: 0
U2/V2 IN: SIG-Y1
U2 DRIVE: 1F
V2 DRIVE: 1F
U2/V2 IN: SIG-Y1
U2 DRIVE: 0
V2 DRIVE: 0
Vped1
Vped2
Vrc1amp
Vrped1
Vrped2
Gy2dr1
Gy2dr2
Grdr1
Grdr2
U/VOUT pedestal
variation 1
U/VOUT pedestal
variation 2
U2/V2OUT clamp
U2/V2OUT pedestal
variation 1
U2/V2OUT pedestal
variation 2
Y2 DRIVE variable
range 1
Y2 DRIVE variable
range 2
U2/V2 DRIVE variation 1
U2/V2 DRIVE variation 2
17
18
19
– 11 –
20
21
22
23
24
25
Y2 IN: SIG-Y1
Y2 DRIVE: 1F
U2 PED: 0
V2 PED: 0
U2 PED: 1F
V2 PED: 1F
CP IN: SIG-H5 (Normally input
when reinput system is measured)
U PED: 0
V PED: 0
Vc1amp
U/VOUT clamp
U PED: 1F
V PED: 1F
VFREQ: 1
VFREQ: 0
Measurement conditions
16
YUV system items
fV1
Vertical free-running
frequency 1
Symbol
12
V system items
No.
6
7
8
6
7
20
19
14
14
14
14
Measurement pins
VTIM-L
Grdr = 20 log
Gy2dr = 20 log
Vrped. 1, 2
Vrclamp
Vped. 1, 2
Vclamp
Vx (U2/V2 DRIVE: 1F/0)
Vx (U2/V2 DRIVE: F)
Vx
Vx (Y2 DRIVE: 1F/0)
Vx (Y2 DRIVE: F)
Vx
U2/V2OUT
SIG-H5
U/V OUT
HTIM
VTIM output frequency (for 50Hz mode)
VTIM-H
VTIM output frequency (for 60Hz mode)
Measurement contents
–8.0
2.8
–4.9
2.3
–41
32
2.7
–15
5
2.7
45
–6.3
3.6
–4.0
2.8
–27
45
3.0
–8
10
3.0
50
0.2
5.0
4.7
0.0
60
Typ.
55
Min.
–4.5
4.4
–3.3
3.3
–13
57
3.2
–4
16
3.2
55
0.5
5.3
65
Max.
dB
dB
dB
dB
mV
mV
V
mV
mV
V
Hz
V
V
Hz
Unit
CXA2019AQ
Item
Y IN: SIG-Y2
Y DRIVE: 0
Y IN: SIG-Y3
SHARPNESS: 7
Gydr1
Gydr2
Gshr
Gshr1
Gshr2
Gsc1
Gsc2
fyout
C-trap1
C-trap2
Y DRIVE variable
range 1
Y DRIVE variable
range 2
SHARPNESS center
SHARPNESS variable
range 1
SHARPNESS variable
range 2
SUB CONT variable
range 1
SUB CONT variable
range 2
Y OUT frequency
response
C-TRAP attenuation
358
C-TRAP attenuation
443
27
28
29
30
31
32
33
– 12 –
34
35
36
18
18
18
Y IN: SIG-Y5
TRAP SW: 0/1
CTRAPADJ: adjustment value
Y IN: SIG-Y6
TRAP SW: 0/1
CTRAPADJ: adjustment value
18
18
18
Measurement pin
Y IN: SIG-Y4
Y IN: SIG-Y2
SUB CONT: 0
Y IN: SIG-Y2
SUB CONT: F
Y IN: SIG-Y3
SHARPNESS: 0
Y IN: SIG-Y3
SHARPNESS: F
Y IN: SIG-Y2
Y DRIVE: 1F
Vyout
Y IN: SIG-Y2
Y DRIVE: F
Measurement conditions
Y OUT output
amplitude
Symbol
26
Y system items
No.
C-trap = 20 log
fyout = 20 log
Vx (TRAP SW: 1)
Vx (TRAP SW: 0)
Vx
Vx (f = 8MHz)
Vx (f = 100kHz)
Vx
Vx (SUB CONT: F/0)
Vx (SUB CONT: 7)
AAA
AAA
AAA
AAA
Gsc1, 2 = 20 log
Vx (f = 3MHz)
Vx (f = 100kHz)
Vx
Gshr1, 2 = 20 log
Vx
AAA
Vyout = Vx (Y DRIVE: F)
Vx (Y DRIVE: 1F/0)
Gydr1, 2 = 20 log
Vx (Y DRIVE: F)
Vx
Measurement contents
–3.0
–3.5
1.9
–6.3
6.8
2.8
–6.9
2.8
0.9
Min.
–35
–35
–0.5
–3.1
2.4
–5.2
7.6
3.5
–6.3
3.5
1.1
Typ.
–25
–25
2.2
–2.7
2.9
–4.1
8.3
4.2
–5.7
4.2
1.3
Max.
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
Unit
CXA2019AQ
Item
C IN: SIG-C2 (No.37 to 42)
Vvout
Gcol1
Gcol2
Gscol1
Gscol2
φoffset
KP
∆fAPC
VOUT output amplitude
COLOR variable range 1
COLOR variable range 2
SUB COLOR variable
range 1
SUB COLOR variable
range 2
HUE center offset
Killer point
APC pull-in range
38
39
40
41
42
43
44
45
CVBS: burst only
During NTSC input
SUB COLOR: 0
SUB COLOR: F
COLOR: 0
COLOR: 3F
C IN: SIG-C1 (No.37 to 42)
Measurement conditions
UOUT output amplitude Vuout
Symbol
37
C system items
No.
– 13 –
—
—
—
19
20
19
20
20
19
Measurement pin
Vx (COLOR: 3F/0)
Vx (COLOR: 1F)
Confirm that the burst frequency is pulled in
at 3.58MHz ± 400Hz.
Vx (SUB COLOR: F/0)
Gscol1, 2 = 20 log
Vx (SUB COLOR: 7)
Gcol1, 2 = 20 log
Vx
Vx
Measurement contents
–400
–11
–5.0
2.1
5.8
0.9
0.9
Min.
–33
–3
–3.6
2.7
6.3
1.2
1.2
Typ.
400
5
–2.3
3.3
10
6.8
1.5
1.5
Max.
Hz
dB
deg
dB
dB
mV
dB
V
V
Unit
CXA2019AQ
CXA2019AQ
I2C BUS System Items
Symbol
Min.
Typ.
Max.
Unit
46 High level input voltage
Vih
3.0
—
5.0
V
47 Low level input voltage
Vil
0
—
1.5
V
48 High level input current
lih
—
—
10
µA
49 Low level input current
lil
—
—
10
µA
Low level output voltage
50 During current inflow of 3 mA to SDA
(Pin 37)
Vol
0
—
0.4
V
51 SDA inflow current
lol
3
—
—
mA
52 Input capacitance
Ci
—
—
10
pF
53 Clock frequency
fscl
0
—
100
kHz
54 Minimum waiting time for data change
tbuf
4.7
—
—
µs
55 Waiting time for data transfer start
thd;sta
4.0
—
—
µs
56 Low level clock pulse width
tlow
4.7
—
—
µs
57 High level clock pulse width
thigh
4.0
—
—
µs
58 Waiting time for start preparation
tsu;sta
4.7
—
—
µs
59 Data hold time
thd;dat
0
—
—
µs
60 Data preparation time
tsu;dat
250
—
—
ns
61 Rise time
tr
—
—
300
ns
62 Fall time
tf
—
—
300
ns
63 Waiting time for stop preparation
tsu;sto
4.7
—
—
µs
No.
Item
– 14 –
CXA2019AQ
Electrical Characteristics Measurement Circuit
9V
PAL PAL/M NTSC
0.47µ
47µ
15p
15p
0.01µ
15p
470
1.5k
1.5k
15k
Composite
video input
27
26
25
24
23
22
X NTSC
SVCC
– (R_Y) OUT
– (B_Y) OUT
– (B_Y) IN
1µ
21
– (R_Y) IN
28
X 358
CIN
29
X 443/358
31 S GND
SECAM REF
30
1µ
APC
470p
V OUT 20
32 CIN
U OUT 19
33 A PED
Y OUT 18
4.7µ
YIN
V output
U output
Y output
SGND2 17
34 CVBS/Y IN
0.47µ
35 ADRS
SCP 16
9V or 0V
I2C bus
input/output
36 SCL
H TIM 15
37 SDA
V TIM 14
38 V SYNC
V2 IN 13
100
100
H TIM output
V TIM output
1µ V2 IN
U2 IN 12
39 H SYNC
220 4700p
0.47µ
40 V HOLD
IREF
J GND
V2 OUT
U2 OUT
Y2 OUT
ABLFILIN
CP IN
330k
JVCC
100p
1µ U2 IN
AFC
3.3k
SYNCIN
100 1µ
CERA
2.2k
SCP output
2
3
4
5
6
7
8
9
10
1
Y2 IN 11
1µ Y2 IN
0.01µ
330
500kHz
ceramic
oscillator
10k
CPIN
8.2k
1µ
V2
U2
Y2
output output output
47µ
0.01µ
9V
– 15 –
ABL
voltage
CXA2019AQ
Application Circuit
*1: 470Ω when 4.43MHz crystal is used.
47µ
PAL/N
or PAL PAL/M NTSC
15p
15k
*1
1.5k
28
27
26
25
24
23
22
X NTSC
SVCC
– (R_Y) OUT
– (B_Y) OUT
– (B_Y) IN
1µ
X 358
1.5k
X 443/358
31 S GND
1.5k
0.01µ
29
SECAM REF
30
15p
APC
470p
15p
1µ
21
– (R_Y) IN
0.47µ
Color difference Color difference
output to 1H
input from1H
delay line
delay line
V OUT 20
32 CIN
U OUT 19
33 A PED
Y OUT 18
V output
U output
Y output
4.7µ
Composite
video input
SGND2 17
34 CVBS/Y IN
0.47µ
35 ADRS
I2C bus
input/output
SCP 16
36 SCL
H TIM 15
37 SDA
V TIM 14
38 V SYNC
V2 IN 13
39 H SYNC
220 4700p
0.47µ
40 V HOLD
U2 IN 12
100
100
2.2k
V2 OUT
U2 OUT
Y2 OUT
ABLFILIN
CP IN
1
J GND
330k
IREF
CERA
100p
JVCC
3.3k
AFC
100 1µ
2
3
4
5
6
7
8
9
10
Y2 IN 11
SCP output
H TIM output
V TIM output
1µ V2 input
1µ U2 input
1µ Y2 input
0.01µ
330
500kHz
ceramic
oscillator
10k
8.2k
1µ
47µ
V2
U2
Y2
output output otuput
0.01µ
+9V
ABL
input
CPIN
A2025
ABLFIL voltage input.
Connect to VCC when
not used.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 16 –
CXA2019AQ
Signals Used for Measurements
63.556µs
SIG-H1
4.7µs
fH = 15.734kHz
NTSC
0.57V
64.0µs
SIG-H2
4.7µs
fH = 15.625kHz
PAL
0.57V
62.563µs
SIG-H3
4.63µs
fH + 250Hz
0.57V
64.583µs
SIG-H4
4.78µs
fH – 250Hz
0.57V
3µs
SIG-H5
3V
63.556µs
SIG-Y1
1.0V
1.43V
SIG-Y2
4.8µs
0.57V
– 17 –
CXA2019AQ
SIG-Y3
SIG-Y4
SIG-Y5
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AA
AAAAAAAA
AAAAAAAAAA
0.7V
0.7V
0.7V
f = 3.0MHz or
100kHz
f = 8.0MHz or
100kHz
f = 3.58MHz
burst = 3.58MHz
0.57Vp-p
SIG-Y6: f = 4.43MHz, burst = 4.43MHz for SIG-Y5 signal
SIG-C1
AA
AA
AA
AA
0.57V
180°
SIG-C2
0.57V
180°
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
168°
104°
– 18 –
0.48Vp-p
f = 3.58MHz
burst = 3.58MHz
0.68Vp-p
f = 3.58MHz
burst = 3.58MHz
348°
274°
CXA2019AQ
Description of Operation
1. Sync System
The video signals (standard input level: 2Vp-p) input to Pins 38 and 39 are sync separated by the horizontal
and vertical sync separation circuits.
The resulting horizontal sync signal and the signal obtained by frequency dividing the 32fH-VCO output
using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phase compared, the AFC loop is
constructed, and an H pulse (HTIM) synchronized with the H sync is output from Pin 15.
The vertical sync signal is sent to the V countdown block where the most appropriate window processing is
performed to obtain V sync timing information which resets the counter. A V pulse (VTIM) synchronized
with the V sync is output from Pin 14. In addition, BGP, HBLK and VBLK are output from Pin 16 as SCP
(sand castle pulse).
2. Y System
There are two input systems.
Composite video input (2Vp-p) → 1 system
Y/C separation input (2Vp-p) → 1 system
The Y signal (specified input level: 2Vp-p) input to Pin 34 passes through the subcontrast control, chroma
trap, delay line, sharpness control, clamp and auto pedestal circuits, is gain adjusted by the YDRIVE circuit
and is then output.
The CXA2019AQ has a built-in chroma trap, enabling the video signal to be input directly. The trap
frequency is automatically adjusted inside the IC. However, the trap frequency is affected by variations
among the ICs, so fine adjustment through the I2C bus may be required.
Because the f0 of the filter is not specified when the color killer function is operating, turn the trap OFF if
there are any difficulties.
The Y signal delay time can be varied in approximately 60ns increments through the I2C bus register
(DELAY). In addition, when the C system TOT is ON, the Y signal delay time is increased by approximately
140ns to cope with the increase in the C system delay time caused by the TOT filter.
The sharpness control is a delay line type and the sharpness f0 can be switched to 1.5MHz or 3MHz.
3. C System
The CVBS or chroma signal (specified input level: burst level of 570mVp-p) selected by the internal video
switch passes through the ACC, TOT, chroma amplifier and demodulation circuits, is demodulated into the
R-Y and B-Y color difference signals, and is then inversed and output from Pins 23 and 24. However,
during NTSC the signals are 6dB amplified by the internal DET switch and gain adjusted by the COLOR
circuit. During PAL the signals are 6dB amplified by the 1H delay line, input to Pins 21 and 22, and gain
adjusted by the COLOR circuit. Signals that have passed through the 1H delay line can also be input to the
COLOR circuit during NTSC by using the I2C bus register (EXT COLOR). This provides comb filter effects.
In addition, the color system (NTSC/PAL) and the subcarrier frequency (3.58MHz/4.43MHz) are
automatically identified according to the input chroma signal, and the internal VCO and demodulation
circuit, etc., are adjusted automatically. Furthermore, SECAM signals can also be automatically identified
by connecting an external SECAM decoder to Pin 30. In this case, Pins 23 and 24 and the SECAM decoder
color difference output are linked together directly, and one side goes to high impedance and the other side
goes to low impedance according to the input chroma signal, and then they are input to the external 1H
delay line.
System identification can be set to automatic or forced mode by the I2C bus register. The color system is
output to the status register.
The pedestal levels of the U and V color difference signals are clamped by UPED and VPED, respectively,
and then these signals are output. However, the DC of the video portion can be controlled by the I2C bus
register, allowing the offset to be adjusted at the PINP processor input.
– 19 –
CXA2019AQ
4. YUV Reinput System
The U and V color difference signals (output from the PINP processor) input to Pins 12 and 13 are clamped
according to the pulse input to Pin 10, gain controlled by the U2 and V2 drive circuits, the DC of their video
portion is controlled by the U2PED and V2PED circuits, and then these signals are output from Pins 6 and 7.
This function allows adjustment of the white balance and black level of the PINP sub picture.
In addition, the Y signal input to Pin 11 is clamped in the same manner, gain controlled by the Y2 drive
circuit, and output from Pin 8. At this time, bright ABL with a polarity opposite that of the main picture ABL
can be applied by inputting the main picture Y/C/J IC ABLFIL voltage to Pin 9. This allows fluctuation of the
black level of the sub picture caused by the main picture ABL to be suppressed. This reverse polarity ABL
can be turned ON and OFF and the gain and control curve center values can be set by the I2C bus register.
Notes on Operation
• The CXA2019AQ does not perform the initial settings during power ON. This initial data should be input from
a microcomputer.
• Because the YUV signal output from the CXA2019AQ are DC direct connected, the board pattern must be
designed consideration given to minimizing interference from around the power supply and GND.
Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the
bypass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also,
locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire
signal lines near this pin.
• Use lead type (HC-49/U type) for each XTAL oscillator. Confirm that there is no problem for capture range
color response and others at resistors and capacitors as shown in Application Circuit.
• Murata's Ceralock is recommended for ceramic oscillator. When using only for NTSC, 503.5kHz Ceralock; for
NTSC/PAL, 500kHz Ceralock is recommended.
• Use a resistor (such as a metal film resistor) with an error of less than 1% for the IREF pin.
• For unused pins, leave them open.
– 20 –
CXA2019AQ
Definition of I2C BUS Registers
Slave Addresses
Slave Receiver
9AH: ADRS = "High"
9EH: ADRS = "Low"
Slave Transmitter
9BH: ADRS = "High"
9FH: ADRS = "Low"
Register Table
×: Don't care, ∗: Undefined
Control Register
Sub Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×××× 0000
HUE
DPIC OFF
CV/YC
×××× 0001
COLOR
HMASK
CANAL
×××× 0010
SHARPNESS
SUB CONT
×××× 0011
SUB HUE
SUB COLOR
×××× 0100
CTRAPADJ
×××× 0101
AFC
Y DRIVE
TRAP ON TOT ON
SHP-f0
FSC OUT CD MODE2
×××× 0110
U PED
V PED
×××× 0111
U2 PED
V2 PED
×××× 1000
Y2 DRIVE
×××× 1001
U2 DRIVE
PRE OVER
ABL OFF
×××× 1010
V2 DRIVE
ABL CENT
ABL
DC TRAN
×××× 1011
COL SYSTEM
X'TAL PIN
V FREQ
×××× 1100
COL LOOP
SCP BGF
SCP BGR
DELAY
EXT COLOR
1
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H LOCK
KILLER
NT/PAL
50/60
SECAM
VCO-F
∗
∗
– 21 –
CXA2019AQ
Description of I2C BUS Registers
Sub Address
0000
HUE (6): Hue control
0 = Flesh color appears red.
63 = Flesh color appears green.
DPIC OFF (1): Y black expansion ON/OFF switch
0 = ON
1 = OFF
CV/YC (1): Input selector switch
0 = CVBS input
1 = Y/C input
Sub Address
0001
COLOR (6): Color control
0 = Minimum
63 = Maximum
HMASK (1): Macrovision measures
0 = OFF
1 = ON
CANAL (1): When this register is set to "1", the first and last 3H of the video are replaced by DC
during YUV output.
0 = No video portion DC replacement
1 = DC replacement
Sub Address
0010
SHARPNESS (4): Sharpness control
0 = Minimum
15 = Maximum
SUB CONT (4): Sub contrast adjustment
0 = Minimum
15 = Maximum
Sub Address
0011
SUB HUE (4): Hue center adjustment
0 = Flesh color appears red.
15 = Flesh color appears green.
SUB COLOR (4): Color center adjustment
0 = Minimum
15 = Maximum
Sub Address
0100
C-TRAP ADJ (4): Chroma trap f0 adjustment
0 = High
7 = Center
15 = Low
AFC (2): AFC loop gain selector
0 = AFC loop gain high
1 = AFC loop gain medium
2 = AFC loop gain low
3 = AFC loop open, free-running mode
– 22 –
CXA2019AQ
TRAP ON (1): Y system chroma trap ON/OFF
0 = OFF
1 = ON
TOT ON (1): Chroma TOT filter ON/OFF
0 = OFF
1 = ON
Sub Address
0101
Y DRIVE (5): Y output gain control
0 = –6.3dB
31 = +3.5dB
SHP-f0 (1): Sharpness f0 selector
0 = 3MHz
1 = 1.5MHz
FSC OUT (1): When this register os set to "1", the subcarrier frequency is output constantly
from Pin 30.
0 = Output only during the VBLK interval in SECAM mode
1 = Constantly output
CD MODE2 (1): V sync signal pull-in speed selector
0 = Standard
1 = High speed
Sub Address
0110
U PED (4): DC control of pedestal portion of U output (for video)
0 = –8mV
7 = Center
15 = +10mV
V PED (4): DC control of pedestal portion of V output (for video)
0 = –8mV
7 = Center
15 = +10mV
Sub Address
0111
U2 PED (4): DC control of pedestal portion of U2 output reinput from PinP processor (for video)
0 = –35mV
7 = Center
15 = +40mV
V2 PED (4): DC control of pedestal portion of V2 output reinput from PinP processor (for video)
0 = –35mV
7 = Center
15 = +40mV
– 23 –
CXA2019AQ
Sub Address
1000
Y2 DRIVE (5): Y2 output gain control
0 = –4dB
31 = +2.8dB
DC TRAN (3): DC transmission ratio setting
0 = Maximum (100%)
7 = Minimum (78%)
Sub Address
1001
U2 DRIVE (5): U2 output gain control
0 = –6.3dB
31 = +3.6dB
PRE OVER (2): Sharpness preshoot/overshoot ratio setting
0 = 1:2 (PRE:OVER)
3 = 2:1
ABL OFF (1): ON/OFF for ABL applied to Y2 OUT
0 = ON
1 = OFF
Sub Address
1010
V2 DRIVE (5): V2 output gain control
0 = –6.3dB
31 = +3.6dB
ABL CENT (2): ABL center voltage control
0 = Minimum
3 = Maximum
ABL (1): ABL gain control
0 = Standard
1 = Low
Sub Address
1011
COL SYSTEM (2): Selects the color system identification method.
0 = Fixed to NTSC
1 = Fixed to PAL
2 = Fixed to SECAM
3 = Automatic identification
X'TAL PIN (2): Selects the crystal.
0 = Fixed to Pin 26 (XNTSC)
1 = Fixed to Pin 27 (X358)
2 = Fixed to Pin 28 (X443/358)
3 = Automatic identification
V FREQ (2): Inputs the V frequency during no signal.
0 = Force to 60Hz
1 = Force to 50Hz
2 = Automatic (previous status maintained)
– 24 –
CXA2019AQ
DELAY (2): Allows the following delay times to be added to the Y signal.
0 = 0ns
1 = 60ns
2 = 120ns
3 = 180ns
Sub Address
1100
COL LOOP (2): Specifies the identified color system when COL SYSTEM is set to automatic
identification.
0 = PALM/PALN/NTSC
(Pin 28 = PALN crystal, Pin 27 = PALM crystal, Pin 26 = NTSC crystal)
1 = PAL/SECAM/4.43NTSC/NTSC
(Pin 28 = 4.43MHz crystal, Pin 27 = open, Pin 26 = NTSC crystal)
2 = PAL/SECAM (Pin 28 = 4.43MHz crystal, Pin 27 = open, Pin 26 = open)
3 = PALM/NTSC (Pin 28 = open, Pin 27 = PALM crystal, Pin 26 = NTSC crystal)
SCP BGF (2): Controls the phase of the falling edge of the BGP in the SCP output.
(0.4µs per step)
0 = +0.4µs
1 = Center
3 = –0.8µs
SCP BGR (2): Controls the phase of the rising edge of the BGP in the SCP output.
(0.4µs per step)
0 = +0.4µs
1 = Center
3 = –0.8µs
EXT COLOR (1): Forcibly switches the DET switch input to external input (R-Y IN, B-Y IN).
0 = Switched by the NTSC/PAL identification results
1 = External input
H LOCK (1): Returns whether or not the IC's H oscillator and the signal input to H SYNC are locked.
0 = Not locked
1 = Locked
KILLER (1): Returns the color killer ON/OFF status.
0 = OFF
1 = ON
NT/PAL (1): Identifies whether the input signal is NTSC or PAL and returns the results.
0 = NTSC
1 = PAL
50/60 (1): Returns the 50/60Hz identification results.
0 = 60Hz
1 = 50Hz
SECAM (1): Identifies whether or not the input signal is SECAM and returns the results.
0 = Not SECAM
1 = SECAM
VCO-F (1): Detects the input signal burst frequency and returns the results.
0 = 3.58MHz
1 = 4.43MHz
– 25 –
CXA2019AQ
I2C BUS Register Initial Settings
No.
of bits
Initial
setting
HUE
6
1FH
DPIC OFF
1
CV/YC
Register
name
Register
name
Description
No.
of bits
Initial
setting
Description
Center value
U2 PED
4
7H
Center value
0H
DPIC ON
V2 PED
4
7H
Center value
1
1H
Y/C input selection
Y2 DRIVE
5
FH
Center value
COLOR
6
1FH
Center value
DC TRAN
3
0H
Minimum value
HMASK
1
0H
Macrovision
measures OFF
U2 DRIVE
5
FH
Center value
PRE OVER
2
0H
Minimum value
CANAL
1
0H
CANAL OFF
ABL OFF
1
1H
ABL OFF
SHARPNESS
4
7H
Center value
V2 DRIVE
5
FH
Center value
SUB CONT
4
7H
Center value
ABL CENT
2
0H
Minimum value
SUB HUE
4
7H
Center value
ABL
1
0H
Standard
SUB COLOR
4
7H
Center value
COL SYSTEM
2
0H
NTSC
CTRAP ADJ
4
7H
Center value
X'TAL PIN
2
0H
Pin 26 selection
AFC
2
1H
Center value
VFREQ
2
0H
60Hz fixed
TRAP ON
1
0H
TRAP OFF
DELAY
2
0H
Minimum value
TOT ON
1
0H
TOT OFF
COL LOOP
2
0H
PAL M/N/NTSC
Y DRIVE
5
FH
Center value
SCP BGF
2
1H
Center value
SHP-f0
1
0H
SHP = 3MHz
SCP BGR
2
1H
Center value
FSC OUT
1
0H
FSC OUT OFF
CD MODE2
1
0H
Standard
EXT COLOR
1
0H
Automatic
identification
U PED
4
7H
Center value
V PED
4
7H
Center value
– 26 –
CXA2019AQ
SUBCONT characteristics
YDRIVE characteristics
Difference from SUBCONT = 7 [dB]
Outpt amplitude (black to white) [Vp-p]
Example of Representative Characteristics
1.8
1.6
1.4
1.2
Input: YIN
1.4Vp-p (black to white)
Output: YOUT
SUBCONT = 7
DCTRAN = 0
SHARPNESS = 7
1.0
0.8
0.6
0.4
3
7
B
F
Data
13
17
1B
1F
3
2
1
0
Input: YIN
1.4Vp-p (black to white)
Output: YOUT
YDRIVE = F
DCTRAN = 0
SHARPNESS = 7
–1
–2
–3
–4
1
3
5
7
Data
9
B
D
F
TRAP attenuation
SHARPNESS characteristics
8
SHARPNESS = 0
SHARPNESS = 7
SHARPNESS = F
Gain [dB]
4
Input: YIN
SWEEP
Output: YOUT
SUBCONT = 7
YDRIVE = F
DCTRAN = 0
2
0
–2
–4
–6
1
0
2
3
4
5
Frequency [MHz]
6
7
8
Attenuation [dB]
0
SHPSW = 0
6
–10
–20
–30
0
DCTRAN characteristics
Black sink level [mV]
0
1
2 3 4 5
Frequency [MHz]
TRAPSW = 1
TRAPSW = 0
CTRAP ADJ = 9
Transmission rate
98.9%
–50
Transmission rate = (S – black sink level) /S
S = 1.0Vp-p
–100
–200
–250
87.1%
Input: YIN 2Vp-p
Output: YOUT
SUBCONT = 7,
YDRIVE = A
SHARPNESS = 7
–150
0
20
40
60
Input amplitude [IRE]
78.4%
80
100
– 27 –
DCTRAN = 0
DCTRAN = 3
DCTRAN = 7
6
7
CXA2019AQ
COLOR control characteristics
2.5
Output amplitude [Vp-p]
Output amplitude (black to white) [IRE]
AUTOPED characteristics
100
80
60
40
Input: YIN FLAT Signal
Outout: YOUT 100 IRE = 1.1Vp-p
DCTRAN = 0, TRAP = 0
20
0
0
20
40
60
80
Input amplitude (black to white) [IRE]
Input: CVBS/YIN
75% COLORBAR 2Vp-p
2.0 Output: UOUT (YELLOW – BLUE)
SUBCOLR = 7, SUBHUE = 7
1.5 HUE = 1F, TOT = 0
1.0
0.5
0
100
7
0
Attenuation [dB]
0
–2
Input: CVBS/YIN
75% COLORBAR 2Vp-p
Output: UOUT (YELLOW – BLUE)
–4
27
2F
37
3F
1
3
5
7
Data
9
B
D
TOT = OFF
–2
–4
TOT = ON
–6
–8
–10
–12
F
–1
–0.5
0
Difference from 3.579545MHz [MHz]
0.5
R2/V2DRIVE control characteristics
UPED/VPED control characteristics
10
1.6
Output amplitude [Vp-p]
Difference from SUBCOLOR = 7 [dB]
Difference from video blac level for output [mV]
1F
Data
2
2
0
Input: No signal
Output: UOUT/VOUT
SUBCOLOR = 7
COLOR = 1F
–10
17
TOT characteristics
SUBCOLOR control characteristics
4
–6
F
1
3
5
7
Data
9
B
D
1.2
1.0
0.8
– 28 –
Input: U2IN/V2IN
1Vp-p PULSE positive polarity
Output: U2OUT/V2OUT
0.6
0.4
F
U2DRIVE
V2DRIVE
1.4
3
7
B
F
Data
13
17
1B
1F
R2/V2PED control characteristics
Output amplitude (black to white) [Vp-p]
Difference from video black level for output [mV]
CXA2019AQ
60
U2PED
V2PED
40
20
0
–20
Input: No signal
Output: U2OUT/V2OUT
–40
1
3
5
7
Data
9
B
D
F
ABL control characteristics
Output DC variation [mV]
300
Input: Y2IN no signal
Output: Y2OUT
RYDRIVE = F
250
200
150
100
50
ABL = 1/ABLCENT = 3
ABL = 0/ABLCENT = 0
ABL = 0/ABLCENT = 3
0
–50
0
1
2
3
4
5
6
7
ABLFILIN voltage [V]
8
9
– 29 –
Y2DRIVE control characteristics
1.1
1.0
0.9
0.8
0.7
Input: Y2IN
1Vp-p PULSE (positive polarity)
Output: Y2OUT
ABLOFF = 1
0.6
0.5
0.4
3
7
B
F
Data
13
17
1B
1F
CXA2019AQ
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
9.0 ± 0.4
+ 0.4
7.0 – 0.1
0.1
21
30
20
31
A
11
40
1
+ 0.15
0.3 – 0.1
0.65
10
± 0.12 M
0.5 ± 0.2
(8.0)
+ 0.15
0.1 – 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-40P-L01
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
QFP040-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 30 –