CXA2025AS Y/C/RGB/Sync/Deflection for Color TV Description The CXA2025AS is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC system color TVs onto a single chip. The following functions have been added to the same function IC, CXA2025S. 1) Vertical sync pull-in speed switching function 2) YUV SW Y signal switching function 48 pin SDIP (Plastic) Features • I2C bus compatible • Sync signal processing uses a countdown system with non-adjusting H/V oscillator frequencies • Built-in deflection compensation circuit capable of supporting various wide modes • Non-adjusting Y/C block filter • Built-in AKB • Video signal I/Os: Y/C separation input, Y/color difference input, analog RGB input and RGB output • YUV SW Y signal switching function allows picture quality adjustment for the Y signal in the same manner as for the normal Y signal even when Y/color difference input is selected Absolute Maximum Ratings (Ta = 25°C, SGND, JGND = 0V) • Supply voltage SVCC, JVCC –0.3 to +12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.5 W • Voltages at each pin –0.3 to SVCC, JVCC + 0.3 V Operating Conditions Supply voltage SVCC JVCC 9.0 ± 0.5 9.0 ± 0.5 V V Applications Color TVs (4:3, 16:9) NC BGP VM HSIN VSIN VSFIL IREF JGND CERA AFCFIL L2FIL AFCPIN/HOFF HDRIVE JVCC SAWOSC VAGCSH EWDRIVE VDRIVE+ /VPROT VDRIVE– /VPROT VTIM (SCP) ABLFIL ABLIN/VCOMP IKIN 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 APCFIL BLHOLD YIN CIN SVCC SCL SDA YUV SW EYIN ERYIN EBYIN SGND YM YS RIN GIN BIN RSH ROUT GSH GOUT BSH Pin Configuration BOUT NC 48 XTAL Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96413-ST 7 SDA VSFIL HSYNC SEP. 44 HSIN JGND D-COL GAMMA 25 20 22 24 23 21 19 18 17 16 15 14 13 12 11 10 EYIN 9 YUVSW 6 SVCC 1 XTAL 2 APCFIL 5 CIN BLHOLD VM YIN BLANKING BUFFER AKB/CUTOFF/IK DRIVE BRIGHT 27 ERYIN CLAMP V ZOOMING 26 EBYIN ABL 28 SGND RGB CLAMP YS SW REF-P SW PICTURE 29 V SAW GEN. 30 YM YM ATT. Y/C MIX WIDE MODE V PARA GEN. 31 YS YUV CLAMP AMP YUV SW 32 V SAW OSC/AGC 33 SAWOSC RIN CHROMA VCO CHROMA DEMOD. AXIS H PHASE SHIFTER H DRIVE 34 HDRIVE 35 VAGCSH GIN 3 HUE 36 L2FIL H PHASE DETECTOR AFCPIN /HOFF 37 EWDRIVE BIN CHROMA APC KILLER DETECTOR 32fH VCO 39 VDRIVE+ RSH 45 COLOR 1/32 DIVIDER PHASE DETECTOR CERA 40 VDRIVE– /VPROT GSH 4 ACC AMP AFCFIL 38 VTIM BSH TOT CLAMP DC-TRAN D-PIC NC 48 47 NC TIMING PULSE GEN. V COUNT DOWN VSYNC SEP. 42 ABLIN /VCOMP BOUT VM AMP SHARPNESS VSIN 43 ABLFIL GOUT SUBCONT 41 BGP IREF IREF 46 IKIN ROUT –2– C-TRAP Y DELAY D/A I2C BUS DECODER SCL 8 JVCC Block Diagram CXA2025AS CXA2025AS Pin Description Pin No. Symbol Equivalent circuit Description SVCC 1 350 XTAL Connect a 3.579545MHz crystal oscillator. 1 200µ SVCC 1.2k 2 APCFIL 1.2k CR connection for the chroma APC lag-lead filter. 2 50µ 50µ SVCC 9µ 20k 3 BLHOLD 3 4k 20k Capacitor connection for black peak hold of the dynamic picture (black expansion). 1.2k 25µ SVCC Y signal input. Input a 2Vp-p (including sync, 100% white) Y signal via a capacitor. The pedestal level of the input signal is clamped to 4.2V. 1.2k 4 YIN 4 100µ SVCC Chroma signal input. Provide a bias of about VCC/2 and input a C signal (including sync, 100% white, 2Vp-p CV signal) with a 570mVp-p burst level. 10p 5 CIN 5 30k 35µ 6 SVCC Power supply for the video block. JVCC 50µ 4k 7 SCL I2C bus protocol SCL (Serial Clock) input. VILMAX = 1.5V VIHMIN = 3.5V 7 10k –3– CXA2025AS Pin No. Symbol Equivalent circuit Description JVCC 50µ 8 SDA I2C bus protocol SDA (Serial Data) I/O. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V 8 SVCC 100µ 9 YUV SW 147 9 40k 10 External Y signal input. Input a 0.7Vp-p (100 IRE) Y signal via a capacitor. The signal is clamped to 6.5V at the burst timing of the signal input to the sync input pin (Pin 44). EYIN SVCC 2k 1k 11 ERYIN Switch control for the external YUV signal input. When YUV SW is high, the external YUV signal is selected; when YUV SW is low, the Y/C block signal is selected. However, when the EY-SW register is 1, the YIN (Pin 4) input is selected for the Y signal even if YUV SW is high. VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V 10 11 40k 12 External R-Y signal input. Input a 0.78Vp-p (color difference signal obtained by detecting a 100 IRE, 0.7Vp-p, 100% color bar chroma signal at the orthogonal axis) + (R-Y) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input pin (Pin 44). 12 EBYIN External B-Y signal input. Input a 1.0Vp-p (color difference signal obtained by detecting a 100 IRE, 0.7Vp-p, 100% color bar chroma signal at the orthogonal axis) + (BY) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input pin (Pin 44). 13 SGND GND for the video block. SVCC YM switch control input. When YM is high, the Y/C block signal is attennated by 6dB. VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V 100µ 14 YM 147 14 40k –4– CXA2025AS Pin No. Symbol Equivalent circuit Description SVCC 100µ 15 YS 147 15 40k YS switch control input. When YS is high, the RGB block signal is selected; when YS is low, the Y/C block is selected. VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V SVCC 200 16 17 18 RIN GIN BIN Analog R, G and B signal input. Input a 0.7Vp-p (no sync, 100 IRE) signal via a capacitor. The signal is clamped to 5.1V at the burst timing of the signal input to the sync input pin (Pin 44). 16 17 30k 18 SVCC Sample-and-hold for R, G and B AKB. Connect to GND via a capacitor. When not using AKB (manual cut-off mode), R, G and B cut-off voltage can be controlled by applying a control voltage to each pin. The control voltage is 4.2 ± 2V. 1k 19 21 23 RSH GSH BSH 19 21 23 50µ SVCC 200 20 22 24 ROUT GOUT BOUT R, G and B signal output. 2.4Vp-p is output during 100% white input. 12k 20 1100µ SVCC 1k 25 IKIN 25 50µ ABL control signal input and VSAW high voltage fluctuation compensation signal input. High voltage compensation has linear control characteristics for the pin voltage range of about 3V to 1V. ABL does not operate when the pin voltage is 9 [V], and operates with increasing strength as the voltage becomes lower than 9 [V]. SVCC 26 ABLIN /VCOMP Input the signal converted from the CRT beam current (cathode current IK) to a voltage via a capacitor. The V blanking part is clamped to 2.7V at the V retrace timing. The input for this pin is the reference pulse return, and the loop operates so that the Rch is 1Vp-p and the G and Bch are 0.83Vp-p. The G and Bch can be varied by ±0.5V by the bus CUTOFF control. When not using AKB, this pin should not be connected. 147 26 –5– CXA2025AS Pin No. Symbol Equivalent circuit Description SVCC 10k 27 ABLFIL Connect a capacitor to form the LPF of the ABL control signal. 27 1.2k JVCC 1k 28 VTIM (SCP) 28 10k 1k V timing pulse output. Outputs the timing pulse from V sync identification to the end of V blanking. Pulses are positive polarity from 0 to 6 [V]. During zoom mode, the V blanking pulse which has been expanded before and after the V sync is superimposed and output as the 0 to 3 [V] pulse. JVCC 720 29 VDRIVE– /VPROT V sawtooth wave output and Vprotect signal input. When a large current (3mA) is led from this pin, the RGB outputs are all blanked and the status is returned to the I2C bus. 30k 29 400µ 24k JVCC 720 30 VDRIVE+ /VPROT Outputs a V sawtooth wave of the opposite polarity as VDRIVE–. The Vprotect function can also be operated by this pin. 30k 30 24k 400µ JVCC 1.4k 25µ 31 EWDRIVE V parabola wave output. 15k 31 78k 800µ JVCC 32 Sample-and-hold for AGC which maintains the V sawtooth wave at a constant amplitude. Connect to GND via a capacitor. 1.2k VAGCSH 32 –6– CXA2025AS Pin No. Symbol Equivalent circuit Description JVCC 33 100 SAWOSC Connect a capacitor to generate the V sawtooth wave. 100 33 100µ 34 Power supply for the deflection block. JVCC JVCC H drive signal output. This signal is output with the open collector. This pin goes high (OFF) during hold-down. ∗ For the CXA2025S, this pin is low (ON) during hold-down. 147 35 35 HDRIVE 20k JVCC 36 AFCPIN /HOFF 147 10k 4.2V 60k 36 50µ 50µ 10k JVCC 37 L2FIL 100 37 25µ H deflection pulse input for H AFC. Input an about 5Vp-p pulse via a capacitor. Set the pulse width to 10 to 12µs. This pin is also used as the hold-down signal input for the HD output, and if this pin is 1 [V] or less for a 7V cycle or longer, the hold-down function operates and the HD output goes to high (OFF). In addition, the RGB outputs are all blanked and the status is returned to the I2C bus. Filter for H AFC. Connect to GND via a capacitor. The H phase can also be controlled from this pin by leading current in and out of this capacitor. As the pin voltage rises, the picture shifts to the left; as the pin voltage drops, the picture shifts to the right. JVCC 38 AFCFIL 1.2k 46k CR connection for the AFC lag-lead filter. 38 50µ 50µ JVCC 10k 39 CERA 39 Connect the 32fH VCO ceramic oscillator. 400µ 50µ 40 GND for the deflection block. JGND –7– CXA2025AS Pin No. Symbol Equivalent circuit Description JVCC 41 IREF Internal reference current setting. Connect to GND via a 15kΩ resistor. 20k 147 41 JVCC 42 VSFIL Filter for V sync separation. Connect to GND via a capacitor. 42 1k JVCC 43 VSIN 147 Sync signal input for V sync separation. Input a 2Vp-p Y signal. 43 20µ JVCC 44 HSIN 147 Sync signal input for H sync separation. Input a 2Vp-p Y signal. 44 10µ SVCC 45 VM Outputs the differential waveform of the VM (Velocity Modulation) Y signal. (7.1VDC, 2.0Vp-p) The signal delayed for 250ns from YIN is output. The delay time from YIN and the differential coefficient of the output signal vary according to sharpness f0 control. 45 400µ 1k 46 BGP Burst gate pulse output. This pulse is a 0 to 3V positive polarity pulse. While this pulse is gated near V-Sync for the CXA2025S, it is constantly output for the CXA2025AS. 46 15k 1k 47 48 Not connected. Normally connected to GND to prevent interference with other pins. GND GND –8– –9– ∆fHR VBGPh VSpp VSdc Horizontal sync pull-in range HD output pulse width BGP output pulse width VDRIVE output amplitude VDRIVE output center potential 4 5 6 7 8 HDw fHFR Horizontal free-running frequency Item 3 No. Symbol JICC Sync block current consumption 2 Sync deflection block items SICC Symbol Signal block current consumption Item 1 No. SYNC IN: composite sync SYNC IN: composite sync SYNC IN: composite sync AFC MODE = 0H 29, 30 29, 30 46 35 — 35 Measurement pin 34 JVCC = 9.0V, Bus data = center Measurement conditions 6 Measurement pin SVCC = 9.0V, Bus data = center Measurement conditions 24.5 Measure the pulse width for the section where the HDRIVE output is high. 43: VSIN in VDRIVE+ 8.97ms VSdc VSpp Measure the VDRIVE output Vp-p. 2.9 0.8 3.1 –400 Measure the pulse width for the section where the BGP output is high. Typ. 45 65 Typ. 3.0 0.95 4.0 25.5 — mA mA 3.15 1.1 4.9 26.5 400 V V µs µs Hz kHz Max. Unit 60 90 Max. Unit 15.55 15.734 15.9 Min. 25 40 Min. Confirm that I2C status register HLOCK is 1 (the pull-in range when fH is shifted from 15.734kHz). HDRIVE output frequency Measurement contents Measure the pin inflow current. Measure the pin inflow current. Measurement contents Setting conditions • Ta = 25°C, SVCC = JVCC = 9V, SGND = JGND = 0V • Measures the following after setting the I2C bus register as shown in “I2C bus register initial settings”. Electrical Characteristics CXA2025AS – 10 – Lin R, G and B output linearity C-TRAP attenuation 12 13 C-Trap VRout1 R, G and B output amplitude Item 11 No. Symbol VEWdc EWDRIVE output center potential 10 Signal block items VEWpp Symbol EWDRIVE output amplitude Item 9 No. C-TRAP = 0/1 CTRAP-ADJ = 7H 100 IRE 50 IRE 1.4Vp-p/100 IRE YIN: fsc, 50 IRE YIN: YIN: Measurement conditions SYNC IN: composite sync Measurement conditions 20 20, 22, 24 V1 Lin = V1 × 100 V2 × 2 f = 3.58MHz Input fsc to YIN. Ratio of the fsc component of the Rout amplitude when CTRAP=1 against the Rout amplitude when CTRAP=0. V2 Output amplitude when a video signal with an amplitude of 1.4Vp-p/100 IRE is input 20, 22, 24 8.97ms Measurement contents 43: VSIN in VEWpp Measure the EWDRIVE output Vp-p. Measurement contents Measurement pin 31 31 Measurement pin — 95 2.1 Min. 3.7 0.5 Min. –37.5 100 2.4 Typ. 4.0 0.65 Typ. V V — 105 2.7 dB % V Max. Unit 4.2 0.8 Max. Unit CXA2025AS – 11 – 24 20, 22, 24 ∆GdcolB ∆GYM Dynamic color operation B output YM gain 20 21 D-COL = 0/1 SUBCONT = F YIN: 100 IRE ∆GdcolR Dynamic color operation R output 19 20 ∆fAPC APC pull-in range 18 — — YIN = GND CIN: Burst only KP Killer point 17 — HUE = 1F, SUB-HUE = 7 φoffset Hue center offset 16 24 Color gain 15 Vcol Vvm YIN: GND CIN: burst +180°, 500mVp-p COLOR = 1F Measurement pin 45 Measurement conditions YIN: 3MHz, 50 IRE VM = 1 Symbol VM output Item 14 No. 0° Vpp 500mVp-p 50 IRE Vpp (DCOL = 1) × 100 Vpp (DCOL = 0) ∆GdcolB = Output amplitude ratio when the R, G and BOUT YM = 1 Vpp (DCOL = 1) × 100 Vpp (DCOL = 0) Vpp ∆GdcolR = ROUT, BOUT Confirm that the burst frequency is pulled in at 3.58MHz ±400Hz. Confirm that status register KILLER is 1 when the burst level is –31dB assuming burst 570mVp-p to be 0dB. BOUT CIN 180° Vvm f = 3MHz Measurement contents –7.1 104 94 –400 — –8.5 0.75 1.5 Min. –6.1 106 96 — –31 0 0.98 2.2 Typ. –5.1 108 98 400 — 8.5 1.2 2.4 dB % % Hz dB deg V V Max. Unit CXA2025AS IK level G IK level B 29 30 27 – 12 – VIKB VIKG GCUTOFF = 0 BCUTOFF = 0 25 25 25 24 YS: 1V RGBIN: 0.7V B output amplitude during VLBout external B input 26 SYNC IN: composite sync 22 YS: 1V RGBIN: 0.7V G output amplitude during VLGout external G input 25 VIKR 20 YS: 1V RGBIN: 0.7V R output amplitude during VLRout external R input 24 IK level R 24 YUVSW: 2V EBYIN: 0.4V B output amplitude during VBout1 external B-Y input 28 20 YUVSW: 2V ERYIN: 0.4V R output amplitude during VRout3 external R-Y input 23 Measurement pin 20 Measurement conditions YUVSW: 2V EYIN: 0.7V Symbol R output amplitude during VRout2 external EY input Item 22 No. R, G, B out EYIN ERYIN EBYIN RGBIN VIKR VIKG VIKG Vout Vin Measurement contents VBout = Vout VGout = Vout VRout = Vout VBout1 = Vout VRout3 = Vout VRout2 = Vout 0.24 0.24 0.8 1.9 1.9 1.9 1.34 1.75 2.05 Min. 0.42 0.42 0.98 2.23 2.23 2.23 1.64 2.2 2.4 Typ. 0.6 0.6 1.16 2.55 2.55 2.55 1.94 2.65 2.75 V V V V V V V V V Max. Unit CXA2025AS CXA2025AS Electrical Characteristics Measurement Conditions “I2C bus register initial settings” PICTURE VM DC-TRAN COLOR AXIS D-COL SHARPNESS SHP-F0 CTRAP-ADJ SUB-HUE GAMMA AGING1 B-DRIVE B-CUTOFF CD-MODE2 GON PICON FHHI AKBOFF V-COMP AFC-MODE V-LIN REF-POSI VBLKW PIN-PHASE LO-CPIN AFC-ANGLE ZOOMSW V-SCROLL UP-VLIN LEFT-BLK = 3F Hex =0 =0 = 1F Hex =0 =0 = 7 Hex =2 = 7 Hex = 7 Hex =0 =0 = 2A Hex =0 =0 =1 =1 =0 =0 =0 =1 = 7 Hex =3 =0 = 7 Hex =0 = 7 Hex =0 = 1F Hex = 0 Hex = 7 Hex C-TRAP HUE D-PIC TOT BRIGHT ABL PRE-OVER SUB-CONT SUB-COLOR SUB-BRIGHT G-DRIVE AGING2 G-CUTOFF EY-SW RON BON VOFF CD-MODE V-SIZE V-POSITION S-CORR H-SIZE PIN-COMP H-POSITION UP-CPIN AFC-BOW V-ASPECT HBLKSW JMPSW LO-VLIN RIGHT-BLK – 13 – =0 = 1F Hex =0 =0 = 1F Hex =0 =3 = 7 Hex = 7 Hex = 1F Hex = 2A Hex =0 =0 =0 =1 =1 =0 =0 = 1F Hex = 1F Hex =0 = 1F Hex = 1F Hex = 7 Hex =0 = 7 Hex = 0 Hex =0 =0 = 0 Hex = 7 Hex 1.5k 3.579545 MHz 15p XTAL 1 2 YIN 4 5 220 12 0.1µ 0.1µ 0.1µ 11 ERYIN YS YM/YS signal input 220 15 16 0.1µ 100 20 Analog RGB input 17 1k 10µ 26 25 0.47µ 100 24 0.1µ 23 RGB output 100 22 0.1µ 21 GSH Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. PINP Y/color difference I2C bus input/output signal input 220 6 220 10 9 8 7 SVCC C signal input 0.47µ Y signal input 3 19 NC 18 NC APCFIL 0.47µ 14 BGP BLHOLD 15k SCL 47µ CIN 0.01µ 13 27 28 29 30 31 32 33 34 35 36 37 38 39 40 10µ 100 41 100 42 100 43 220 100 10k VM ABL/Vertical high voltage fluctuation compensation signal input IK input 44 15k 390 503k 2.7k HD output V sawtooth V parabola wave output wave output V timing pulse output V protect signal input HSIN 45 470p VSIN 46 4.7µ VSFIL 47 0.47µ IREF 48 330k JGND SDA 3.5k 1µ 100 8.2k CERA YUV SW 100p 220 0.0047µ 10k 0.01µ AFCFIL EYIN 1k 1µ Hold-down input 0.0027µ L2FIL EBYIN AFCPIN/HOFF 0.1µ HDRIVE SGND JVCC 0.01µ SAWOSC YM VAGCSH GOUT +9V 47µ 0.01µ HP input 0.01µ BGP output 0.01µ Signal output for VM 0.1µ EWDRIVE RIN ABLIN/VCOMP 0.1µ VDRIVE+ /VPROT GIN VDRIVE– /VPROT BIN VTIM RSH ABLFIL ROUT – 14 – BSH IKIN BOUT Application Circuit CXA2025AS SYNCIN 1.5k 3.579545 MHz 15p 10k 48 1 46 47 2 3 4.7µ 45 4 YIN 44 220 5 1µ 100 CIN 9V I2CBUS 220 220 9 8 7 6 220 40 41 42 39 390 43 15k 503kHz width 10µs delay 12µs VSIN SVCC 330p 1k AFCPIN 0.47µ VSFIL SCL BGP VM 0.0047µ 0.47µ HDRIVE 38 10k 37 CXA2025AS 11 12 YM 220 YS 220 15 14 13 0.1µ 0.1µ 0.1µ 10 34 35 2.7k 9V HDRIVE 36 HOFF 33 16 4538 4 RGBIN ROUT 100 100 22 GOUT 0.1µ 21 24 BOUT 0.1µ 23 10k 20k P1 51k D1 D2 D3 IKIN 100 1µ 0.001µ 100 20 19 18 0.1µ 25 26 27 ABL 28 10µ 100 29 100 VTIM 10k VPROT 8 30 100 9 7 10 6 11 5 12 5.1k 31 100 32 17 3 13 VDRIVE– E/W VDRIVE+ 10k 14 2 15 10k 1 16 2000p AFCPIN/HOFF SGND 0.01µ 47µ HDRIVE YM 5.1k EWDRIVE BIN 9V XTAL NC 470p NC APCFIL 0.47µ VM YIN BGP BLHOLD 15k EYIN HSIN CIN 0.01µ JVCC YS 2000p 0.01µ 330k IREF SDA 47µ JGND YUV SW YUVSW CERA 8.2k EYIN RSH 1µ AFCFIL ERYIN ERYIN VDRIVE+ /VPROT 0.1µ L2FIL EBYIN EBYIN ROUT 0.1µ VDD 1T1 SAWOSC RIN 2CD 1A VDRIVE– /VPROT 47µ 0.01µ 2A 1B VTIM GSH 0.01µ 2T1 1T2 VAGCSH GIN 2B 1Q ABLFIL GOUT 0.1µ 2T2 1CD 0.01µ 2Q 1Q ABLIN/VCOMP BSH 0.1µ 2Q VSS IKIN – 15 – BOUT 9V 9V CXA2025AS Electrical Characteristics Measurement Circuit Signal sources are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics. ABL is 9V unless otherwise specified. CXA2025AS Definition of I2C Bus Registers Slave Addresses 88H: Slave receiver 89H: Slave transmitter Control Register Sub Address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ∗ ∗ ∗ 0 0 0 0 0 00 H PICTURE C-TRAP VM ∗ ∗ ∗ 0 0 0 0 1 01 H HUE DC-TRAN D-PIC ∗ ∗ ∗ 0 0 0 1 0 02 H COLOR TOT AXIS ∗ ∗ ∗ 0 0 0 1 1 03 H BRIGHT D-COL ABL ∗ ∗ ∗ 0 0 1 0 0 04 H SHARPNESS ∗ ∗ ∗ 0 0 1 0 1 05 H SUB-CONT CTRAP-ADJ ∗ ∗ ∗ 0 0 1 1 0 06 H SUB-COLOR SUB-HUE PRE-OVER SHP-F0 ∗ ∗ ∗ 0 0 1 1 1 07 H SUB-BRIGHT ∗ ∗ ∗ 0 1 0 0 0 08 H G-DRIVE AGING1 AGING2 ∗ ∗ ∗ 0 1 0 0 1 09 H B-DRIVE EY-SW CD-MODE2 ∗ ∗ ∗ 0 1 0 1 0 0A H ∗ ∗ ∗ 0 1 0 1 1 0B H GAMMA B-CUTOFF G-CUTOFF RON GON BON PICON VOFF FHHI CD-MODE AKBOFF ∗ ∗ ∗ 0 1 1 0 0 0C H V-SIZE V-COMP ∗ ∗ ∗ 0 1 1 0 1 0D H V-POSITION AFC-MODE ∗ ∗ ∗ 0 1 1 1 0 0E H V-LIN S-CORR ∗ ∗ ∗ 0 1 1 1 1 0F H H-SIZE REF-POSI ∗ ∗ ∗ 1 0 0 0 0 10 H PIN-COMP VBLKW ∗ ∗ ∗ 1 0 0 0 1 11 H H-POSITION PIN-PHASE ∗ ∗ ∗ 1 0 0 1 0 12 H UP-CPIN LO-CPIN ∗ ∗ ∗ 1 0 0 1 1 13 H AFC-BOW AFC-ANGLE ∗ ∗ ∗ 1 0 1 0 0 14 H V-ASPECT ∗ ∗ ∗ 1 0 1 0 1 15 H V-SCROLL ZOOMSW HBLKSW JMPSW ∗ ∗ ∗ 1 0 1 1 0 16 H UP-VLIN LO-VLIN ∗ ∗ ∗ 1 0 1 1 1 17 H LEFT-BLK RIGHT-BLK 0 Status Register BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 HLOCK IKR VNG HNG KILLER 0 1 0 Note) EY-SW and CD-MODE2 have been added to the CXA2025S. – 16 – CXA2025AS Description of Registers Register name No. of bits Function PICTURE (6) : Picture gain control (RGB gain control) 0H = –15dB 3FH = 0dB RGB output: 2.4Vp-p (I/O gain: +4.7dB, 1.4Vp-p input) C-TRAP (1) : Y block chroma trap ON/OFF switch 0 = Trap OFF 1 = Trap ON (Y signal delay time adjusted when C-TRAP turned ON or OFF.) VM (1) : Y signal differential output ON/OFF switch for VM 0: Output OFF 1: Output ON (2.0Vp-p) HUE (6) : Hue control (Chroma demodulation axis control when SUB-HUE is 8H) 0H = +35° Flesh color appears red. 1FH = 0° 3FH = –35° Flesh color appears green DC-TRAN (1) : Y DC transmission ratio selector switch 0 = 100% 1 = 82% DPIC (1) : Y black expansion ON/OFF switch 0 = OFF 1 = ON Point of inflection: 30 IRE COLOR (6) : (Color gain control) 0H = Color OFF (–40dB or less) 1FH = 0dB B output: 1.1Vp-p (I/O gain: +5.7dB, 0.57Vp-p input) 3FH = +5.4dB TOT (1) : Chroma TOT filter band selector switch 0 = TOT-TRAP OFF 1 = TOT-TRAP ON (TRAP f0 2.0MHz) AXIS (1) : R-Y, G-Y axis selector switch 0 = Japan axis R-Y: 95° × 0.78, G-Y: 240° × 0.3 1 = US axis R-Y: 112° × 0.83, G-Y: 252° × 0.3 (B-Y: 0° × 1) – 17 – CXA2025AS BRIGHT (6) : Bright level control (RGB DC bias control) 0H = –300mV 1FH = 0mV –300mV from REF-P level 3FH = +300mV D-COL (1) : Dynamic color ON/OFF switch 0 = Dynamic color OFF 1 = Dynamic color ON (R, Bch level control) ABL (1) : ABL mode selector switch 0 = Picture ABL mode 1 = Picture/bright ABL mode SHARPNESS (4) : Sharpness gain control (Y aperture correction gain control) 0H = –8dB 7H = 1dB FH = +5.1dB PRE-OVER (2) : Sharpness preshoot/overshoot ratio control 0H = 1:1 (PRE:OVER) 3H = 5:1 SHP-F0 (2) : Sharpness f0 control (Delay line current control for aperture correction) 0H = 2.5MHz 3H = 4.0MHz SUB-CONT (4) : Contrast gain control (Y gain control) 0H = –3.0dB 7H = 0dB FH = +2.5dB CTRAP-ADJ (4) : Chroma trap f0 adjustment (Y block chroma trap current control) 0H = +300kHz 7H = 0kHz FH = –300kHz fsc adjustable to –30dB or less (SHP-F0 min.); adjustment value: 3 to 4 SUB-COLOR (4) : Color gain control (ACC reference level control) 0H = –4.0dB 7H = 0dB FH = +2.1dB – 18 – CXA2025AS SUB-HUE (4) : Hue control (Phase control for chroma demodulation axis when HUE is 1FH) 0H = +10° 7H = 0 FH = –10° B-Y axis adjustable to 0° SUB-BRIGHT (6) : Bright level control (RGB DC bias control) 0H = –300mV 1FH = 0mV –300mV from REF-P level 3FH = +300mV GAMMA (2) : Gamma control (RGB gamma correction amount control) 0H = Gamma OFF 3H = Gamma peak (40 IRE) +400mV G-DRIVE (6) : Gch drive gain adjustment (Gch gain control) 0H = G/R –3.8dB 2AH = G/R 0dB 3FH = G/R +2.5dB AGING1 (1) : White output aging mode ON/OFF switch (Has priority over RGBON and PICON control, set to OFF mode at poweron.) 0 = Aging mode OFF 1 = Aging mode ON 60 IRE flat signal output from Y block when input signal present. AGING2 (1) : Black output aging mode ON/OFF switch (Has priority over AGING1, set to OFF mode at power-on.) 0 = Aging mode OFF 1 = Aging mode ON Black level output. B-DRIVE (6) : Bch drive gain adjustment (Bch gain control) 0H = B/R –3.8dB 2AH = B/R 0dB 3FH = B/R +2.5dB EY-SW (1) : Internal Y signal fixed mode ON/OFF switch 0 = YUV SW (Pin 9) standard operation. (EYIN, ERYIN and EBYIN input selected when Pin 9 = high.) 1 = EYIN (Pin 10) input only invalid. (Internal Y, ERYIN and EBYIN input selected when Pin 9 = high.) CD-MODE2 (1) : Vertical sync pull-in speed switch 0 = Standard (equivalent to CXA2025S) 1 = High speed – 19 – CXA2025AS G-CUTOFF (4) : Gch cut-off adjustment (Gch reference pulse value control of IKIN pin input) 0H = –45% 7H = 83% (G/R) FH = +133% B-CUTOFF (4) : Bch cut-off adjustment (Bch reference pulse value control of IKIN pin input) 0H = –45% 7H = 83% (B/R) FH = +133% RON (1) : ON/OFF switch for Rch video output without a reference pulse (Operates when PICON = 1, set to OFF mode at power-on.) 0 = Rch video output OFF (Blanked status, reference pulse only output) 1 = Rch video output ON GON (1) : ON/OFF switch for Gch video output without a reference pulse (Operates when PICON = 1, set to OFF mode at power-on.) 0 = Gch video output OFF (Blanked status, reference pulse only output) 1 = Gch video output ON BON (1) : ON/OFF switch for Bch video output without a reference pulse (Operates when PICON = 1, set to OFF mode at power-on.) 0 = Bch video output OFF (Blanked status, reference pulse only output) 1 = Bch video output ON PICON (1) : ON/OFF switch for RGB output with a reference pulse (Set to OFF mode at power-on.) 0 = RGB output OFF (All blanked status) 1 = RGB output ON VOFF (1) : V sawtooth wave oscillation stop ON/OFF switch (Set to ON mode at power-on.) 0 = Oscillation stop OFF (VDRIVE– and VDRIVE+: normal output) 1 = Oscillation stop ON (VDRIVE– and VDRIVE+: DC output and DC value vary according to V-POSITION.) FHHI (1) : H oscillator frequency fixation ON/OFF switch (Set to ON mode at power-on.) 0 = H oscillator frequency fixation OFF AFC normal mode 1 = H oscillator frequency fixation ON Oscillator frequency fixed to maximum value (16.252kHz). CD-MODE (1) : V countdown system mode selector switch (Set to automatic selection mode during power-on.) 0 = Non-standard signal mode, standard signal mode and no signal mode automatically selected 1 = Fixed to non-standard signal mode (V oscillator frequency is 55Hz during no signal mode (free run).) – 20 – CXA2025AS AKBOFF (1) : AKB ON/OFF switch (Set to ON mode at power-on.) 0 = AKB ON 1 = AKB OFF IK clamp, IK S/H and reference pulse fixed to OFF. R, G and B cut-off adjustment at AKB OFF performed by voltage applied to Pins 19 (RSH), 21 (GSH) and 23 (BSH), respectively. V-SIZE (6) : Vertical amplitude adjustment (V sawtooth wave gain control: Func.) 0H = –14% Vertical picture size decreases. 1FH = 0% Amplitude: 1.15Vp-p, center potential: DC 3V when V-ASPECT is 1FH 3FH = +14% Vertical picture size increases. V-COMP (2) : Compensation amount setting for vertical high voltage fluctuation (V sawtooth wave gain control: Func.) 0H = 0% V sawtooth wave amplitude compensation amount when VCOMP (Pin 26) is 1V 3H = –5% V sawtooth wave amplitude compensation amount when VCOMP (Pin 26) is 1V V-POSITION (6) : Vertical position adjustment (V sawtooth wave DC bias control: Func.) 0H = –0.09V Picture position drops, VDRIVE+ output DC Down. 1FH = 0V Center DC: 3V 2FH = +0.09V Picture position rises, VDRIVE+ output DC Up. AFC MODE (2) : AFC loop gain control (PLL between Hsync and Hvco) 0H = H free run mode 1H = Small gain 2H = Medium gain 3H = Large gain S-CORR (4) : Vertical S correction amount adjustment (V sawtooth wave secondary component gain control: Func.) 0H = Secondary component amplitude by adding sawtooth and other signals = 0 FH = Secondary component amplitude by adding sawtooth and other signals = Maximum V-LIN (4) : Vertical linearity adjustment (Gain control for V sawtooth wave secondary component: Func.) 0H = 85% (Bottom/top of picture) Top of picture expanded; bottom of picture compressed. 7H = 100% (Bottom/top of picture) FH = 115% (Bottom/top of picture) Top of picture compressed; bottom of picture expanded. H-SIZE (6) : Horizontal amplitude adjustment (V parabola wave DC bias control: Func.) 0H = –0.5V Horizontal picture size decreases, EWDRIVE output DC Down. 1FH = 0V Amplitude: 0.58Vp-p, center: DC 4V when V-ASPECT is 2FH 3FH = +0.5V Horizontal picture size increases, EWDRIVE output DC Up. REF-POSI (2) : Reference pulse timing setting 0H = (From VTIM rise) Rch: 22H, Gch: 23H, Bch: 24H 1H = (From VTIM rise) Rch: 20H, Gch: 21H, Bch: 22H 2H = (From VTIM rise) Rch: 18H, Gch: 19H, Bch: 20H 3H = (From VTIM rise) Rch: 16H, Gch: 17H, Bch: 18H – 21 – CXA2025AS PIN-COMP (6) : Horizontal pin distortion compensation amount adjustment (V parabola wave gain control: Func.) 0H = 0.11Vp-p Compensation amount minimum 1FH = 0.47Vp-p Center potential: DC 4V when V-ASPECT is 2FH 3FH = 0.84Vp-p Compensation amount maximum VBLKW (2) : VBLK width control (Blanked pulses after reference pulse. Operates when JMPSW = 1; blanked pulses after reference pulse fixed to 1H when JMPSW = 0.) 0H = 12H from Bch REF-P 1H = 11H from Bch REF-P 2H = 10H from Bch REF-P 3H = 9H from Bch REF-P H-POSITION (4) : Horizontal position adjustment (HAFC phase control) 0H = 1µs delay Picture position shifts to right. Video delayed with respect to HD. 7H = 0µs FH = 1µs advance Picture position shifts to left. Video advanced with respect to HD. PIN-PHASE (4) : Horizontal trapezoidal distortion compensation adjustment (V parabola wave center timing control: Func.) 0H = 1.5ms advance Horizontal size for top of picture increases; horizontal size for bottom of picture decreases. 7H = 0ms 8.9ms from 4VDC VTIM FH = 1.5ms delay Horizontal size for top of picture decreases; horizontal size for bottom of picture increases. UP-CPIN (4) : Horizontal pin distortion compensation amount adjustment for top of picture (V parabola wave gain control: Func.) 0H = +0.2V Horizontal size for top of picture increases (Compensation amount minimum). 7H = 0V (0.7Vp-p, 4:3 mode) FH = –0.2V Horizontal size for top of picture decreases (Compensation amount maximum). LO-CPIN (4) : Horizontal pin distortion compensation amount adjustment for bottom of picture (V parabola wave gain control: Func.) 0H = +0.2V Horizontal size for bottom of picture increases (Compensation amount minimum). 7H = 0V (0.7Vp-p, 4:3 mode) FH = –0.2V Horizontal size for bottom of picture decreases (Compensation amount maximum). AFC-BOW (4) : Vertical bow line compensation amount adjustment (Phase control according to HAFC parabola wave) 0H = Top and bottom of picture delayed 500ns with respect to picture center. 7H = 0ns FH = Top and bottom of picture advanced 500ns with respect to picture center. AFC-ANGLE (4) : Vertical line slope compensation amount adjustment (Phase control according to HAFC sawtooth wave) 0H = Top of picture delayed 500ns, bottom of picture advanced 500ns with respect to picture center. 7H = 0ns FH = Top of picture advanced 500ns, bottom of picture delayed 500ns with respect to picture center. – 22 – CXA2025AS V-ASPECT (6) : Aspect ratio control (Gain control for sawtooth wave input to Func.: Mode) 0H = 75% 16:9 CRT full 2FH = 100% 4:3 CRT full, amplitude: 1.23Vp-p 3FH = 112% ZOOMSW (1) : Zoom mode ON/OFF switch for 16:9 CRT (Top and bottom of sawtooth wave input to Func. squeezed and 25% of video cut: Mode) 0 = Zoom OFF Sawtooth wave amplitude: 1.23Vp-p 1 = Zoom ON Sawtooth wave amplitude: 70% HBLKSW (1) : HBLK width control ON/OFF switch during 4:3 software full display mode on a 16:9 CRT 0 = Control OFF HBLK pulse generated from HPIN. 1 = Control ON HBLK pulse generated as pulse generated from HPIN or as pulse generated from HVCO and width adjusted. Width adjustment is performed by the LEFT-BLK and RIGHTBLK registers. V-SCROLL (6) : Vertical picture scroll control during zoom mode on a 16:9 CRT (DC component added to sawtooth wave AGC output to control ZOOMSW cut timing.: Mode) 0H = –0.25V Scrolled toward top of screen by 32H and top of picture zoomed. 1FH = 0V 3FH = +0.25V Scrolled toward bottom of screen by 32H and bottom of picture zoomed. JUMPSW (1) : Reference pulse jump mode ON/OFF switch (In addition to V-ASPECT control, sawtooth wave gain control performed for 100% of VBLK interval and 67% of picture interval: Mode) 0 = Jump mode OFF 1 = Jump mode ON On a 4:3 CRT, jump mode expands the sawtooth wave amplitude to 112% with V-ASPECT; on a 16:9 CRT, jump mode compresses the sawtooth wave amplitude to 75% with V-ASPECT. The V blanking width is expanded at both the top and bottom of the picture. Blanking for the bottom of the picture starts 251H after VTIM, and blanking for the top of the picture can be varied as the blanking width after the reference pulse from the VBLKW register. UP-VLIN (4) : Vertical linearity adjustment for top of picture (Secondary component gain control for sawtooth wave added to sawtooth wave AGC output: Mode) 0H = 100% (Bottom/top of picture) FH = 115% (Bottom/top of picture) Top of picture compressed. LO-VLIN (4) : Vertical linearity adjustment for bottom of picture (Tertiary component gain control for sawtooth wave added to sawtooth wave AGC output: Mode) 0H = 100% (Bottom/top of picture) FH = 85% (Bottom/top of picture) Bottom of picture compressed. – 23 – CXA2025AS LEFT-BLK (4) : HBLK width control for left side of picture when HBLKSW = 1 (Phase control for timing pulse generated from HVCO) 0H = +1.3µs HBLK width maximum 7H = 0µs Center HBLK: 13µs FH = –1.3µs HBLK width minimum RIGHT-BLK (4) : HBLK width control for the right side of picture when HBLKSW = 1 (Phase control for timing pulse generated from HVCO) 0H = +1.3µs HBLK width maximum 7H = 0µs Center HBLK: 13µs FH = –1.3µs HBLK width minimum HLOCK (1) : Lock status between Hsync and HVCO 0 = HVCO free run status 1 = Locked to Hsync IKR (1) : AKB operation status 0 = REF-P return small and AKB loop unstable. 1 = REF-P return sufficient and AKB loop stable. VNG (1) : Signal input status to VPROT pin 0 = No VPROT input 1 = VPROT input HNG (1) : Signal input status to HOFF pin 0 = No HOFF input 1 = HOFF input KILLER (1) : Color killer status 0 = Killer OFF status 1 = Killer ON status Note) The following have been added to the CXA2025S. EY-SW: Sub Add 09H, Bit 1 CD-MODE2: Sub Add 09H, Bit 0 – 24 – CXA2025AS Description of Operation 1. Power-on sequence The CXA2025AS does not have an internal power-on sequence. Therefore, all IC operations are controlled by the set microcomputer (I2C bus controller). 1) Power-on The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized to the input signal. Output of vertical signal VTIM starts, but Vdrive is DC output. Bus registers which are set by power-on reset are as follows. AGING1 = 0: All white output aging mode OFF AGING2 = 0: All black output aging mode OFF RON = 0: Rch video blanking ON GON = 0: Gch video blanking ON BON = 0: Bch video blanking ON PICON = 0: RGB all blanking ON VOFF = 1: VDRIVE output stopped mode FHHI = 1: H oscillator maximum frequency mode CD-MODE = 0: Automatic selector mode of the countdown mode AKBOFF = 0: AKB mode 2) Bus register data transfer The register setting sequence differs according to the set sequence. Register settings for the following sequence are shown as an example. Set sequence Power-on ↓ Degauss ↓ VDRIVE oscillation ↓ AKB operation start ↓ AKB loop stable ↓ Video output CXA2025AS register settings Reset status in 1) above. ↓ Reset status in 1) above. The CRT is degaussed in the completely darkened condition. ↓ The IC is set to the power-on initial settings. (See the following page.) A sawtooth wave is output to VDRIVE and the IC waits for the vertical deflection to stabilize. The HDRIVE oscillator frequency goes to the standard frequency (around 15.734kHz). ↓ PICON is set to 1 and a reference pulse is output from Rout,Gout and Bout. Then, the IC waits for the cathode to warm up and the beam current to start flowing. ↓ Status register IKR is monitored. IKR = 0: No cathode current IKR = 1: Cathode current Note that the time until IKR returns to 1 differs according to the initial status of the cathode. ↓ RON, GON and BON are set to 1 and the video signal is output from Rout,Gout and Bout. – 25 – CXA2025AS 3) Power-on initial settings The initial settings listed here are reference values, and initial settings may be determined freely according to the set usage conditions. PICTURE = 3F Hex Max (User Cont.) C-TRAP =0 Chroma Trap OFF VM =1 VM out ON HUE = 1F Hex Center (User Cont.) DC-TRAN =0 Y DC transmission ratio 100% D-PIC =1 Y black expansion ON COLOR = 1F Hex Center (User Cont.) TOT =0 Chroma low frequency increased AXIS =0 R-Y, G-Y Japan axis BRIGHT = 1F Hex Center (User Cont.) D-COL =1 Dynamic Color ON ABL =1 Picture/bright ABL mode SHARPNESS = 7 Hex Center (User Cont.) PRE-OVER =0 Sharpness pre/over ratio 2:1 SHP-F0 =1 Sharpness f0 3MHz SUB-CONT = 7 Hex Center (Adjust) CTRAP-ADJ = 7 Hex Center (Adjust) SUB-COLOR = 7 Hex Center (Adjust) SUB-HUE = 7 Hex Center (Adjust) SUB-BRIGHT = 1F Hex Center (Adjust) GAMMA =0 Gamma OFF G-DRIVE = 1F Hex Center (Adjust) AGING1 =0 Aging Mode OFF AGING2 =0 Aging Mode OFF B-DRIVE = 1F Hex Center (Adjust) G-CUTOFF = 7 Hex Center (Adjust) B-CUTOFF = 7 Hex Center (Adjust) EY-SW =0 Standard CD-MODE2 = 0 Standard RON =0 Rch video output OFF GON =0 Gch video output OFF BON =0 Bch video output OFF PICON =0 RGB all blanked VOFF =0 Vdrive oscillation stopped FHHI =0 Horizontal oscillator frequency standard CD-MODE =0 V countdown auto mode AKBOFF =0 AKB ON V-SIZE = 1F Hex Center (Adjust) V-COMP =3 Vertical high voltage fluctuation compensation amount max. V-POSITION = 1F Hex Center (Adjust) AFC-MODE = 2 Center S-CORR = 7 Hex Center (Adjust) V-LIN = 7 Hex Center (Adjust) H-SIZE = 1F Hex Center (Adjust) REF-POSI =0 PIN-COMP = 1F Hex Center (Adjust) VBLKW =0 – 26 – CXA2025AS (Power-on initial settings cont.) H-POSITION PIN-PHASE UP-CPIN LO-CPIN AFC-BOW AFC-ANGLE V-ASPECT ZOOMSW HBLKSW V-SCROLL JMPSW UP-VLIN LO-VLIN LEFT-BLK RIGHT-BLK = 7 Hex = 7 Hex = 7 Hex = 7 Hex = 7 Hex = 7 Hex = 0 Hex =1 =1 = 1F Hex =0 = 7 Hex = 7 Hex = F Hex = F Hex Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) 16:9 CRT Full Mode 16:9 CRT Hblk width adjust ON Center (User) 16:9 CRT Full Mode 16:9 CRT Full Mode 16:9 CRT Full Mode Hblk width min. Hblk width min. 2. Various mode settings The CXA2025AS contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once deflection adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. • VDRIVE signal picture distortion adjustment registers V-SIZE, V-POSITION, S-CORR, V-LIN • E/WDRIVE signal picture distortion adjustment registers H-SIZE, PIN-COMP, PIN-PHASE, UP-CPIN, LO-CPIN • Wide mode setting registers V-ASPECT, ZOOMSW, HBLKSW, V-SCROLL, JMPSW, UP-VLIN, LO-VLIN, LEFT-BLK, RIGHT-BLK Examples of various modes are listed below. These modes are described using 480 lines as the essential number of display scanning lines. Wide mode setting register data is also listed, but settings may differ slightly due to IC variation. The standard setting data differs for 16:9 CRTs and 4:3 CRTs. Register 16:9 CRT 4:3 CRT V-ASPECT V-SCROLL ZOOMSW UP-VLIN LO-VLIN JMPSW HBLKSW LEFT-BLK RIGHT-BLK 0H 1F H 1 0H 0H 0 0 7H 7H 2F H 1F H 0 0H 0H 0 0 7H 7H – 27 – CXA2025AS 1) 16:9 CRT full mode This mode reproduces the full 480 lines on a 16:9 CRT. 4:3 images are reproduced by stretching the picture to the left and right. Normal images are compressed vertically, but 16:9 images can be reproduced in their original 16:9 aspect ratio with a video source which compresses (squeezes) 16:9 images to 4:3 images. The register settings are the 16:9 CRT standard values. 2) 16:9 CRT normal mode In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2025AS also has a register (H-SIZE) which controls the H size, but the control width is not sufficient for 25% compression. Therefore, external measures must be taken such as switching the H deflection coil, etc. Full mode should be used when performing memory processing and attaching a black border to the video signal. H blanking of the image normally uses the flyback pulse input to AFCPIN (Pin 36). However, the blanking width can be varied according to the control register setting when blanking is insufficient for the right and left black borders. The following three settings are added to the 16:9 CRT standard values for the register settings. HBLKSW = 1 LEFT-BLK = Adjustment value RIGHT-BLK = Adjustment value The H angle of deflection also decreases, causing it to differ from the PIN compensation amount during H size full status. Therefore, in addition to the wide mode registers, PIN-COMP must also be readjusted only for this mode. 3) 16:9 CRT zoom mode In this mode, 4:3 images are reproduced by enlarging the picture without other modification. The top and bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video software, etc. which already has black borders at the top and bottom. The enlargement ratio can be controlled by the V-ASPECT register, and enlarging the picture by 33% compared to full mode allows zooming to be performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 360 lines compared to 480 lines for full mode. The zooming position can be shifted vertically by the V-SCROLL register. V blanking of the image normally begins from V sync and continues for 2H after the AKB reference pulse, and the top and bottom parts are also blanked during this mode. Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings. V-ASPECT = 2FH V-SCROLL = 1FH or user control 4) 16:9 CRT subtitle-in mode When Cinema Scope size images which have black borders at the top and bottom of the picture are merely enlarged with the zoom mode in 3) above, subtitles present in the black borders may be lost. Therefore, this mode is used to super-compress only the subtitle part and reproduce it on the display. Add the LO-VLIN adjustment to the zoom mode settings for the register settings. V-ASPECT = 2FH V-SCROLL = 1FH or user control LO-VLIN = Adjustment value The LO-VLIN register causes only the linearity at the bottom of the picture to deteriorate. Therefore, UP-VLIN should also be adjusted if the top and bottom of the picture are to be made symmetrical. Since the picture is compressed vertically, the number of scanning lines exceeds 360 lines. – 28 – CXA2025AS 5) 16:9 CRT V compression mode This mode is used to reproduce two 4:3 video displays such as for PandP. The V size must be compressed to 67% in order to reproduce two displays on a 16:9 CRT without distortion using 480 scanning lines, and this can be set by JMPSW. Compression is performed after the AKB reference pulse, so the reference pulse remains in the overscan position. The V blanking width after the reference pulse becomes larger than normal and can be varied by the VBLKW register. During this mode, the bottom V blanking width is also expanded to 10H wider than normal so that the bottom of the picture is not overscanned. 16:9 CRT standard values are used with only the JMPSW setting changed for the register settings. JMPSW = 1 6) 16:9 CRT Sony type wide zoom mode This mode reproduces 4:3 video software naturally on wide displays by enlarging 4:3 images without other modification and compressing the parts of the image which protrude from the picture into the top and bottom parts of the picture. The display enlargement ratio is controlled by V-ASPECT, and the compression ratios at the top and bottom of the picture are controlled by UP-VLIN and LO-VLIN. Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings. V-ASPECT = Adjustment value UP-VLIN = Adjustment value LO-VLIN = Adjustment value 7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are the 4:3 CRT standard values. 8) 4:3 CRT V compression mode This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to a 4:3 aspect ratio and other squeezed signals without distortion on a 4:3 CRT. The V size must be compressed to 75% in order to reproduce 4:3 images in a 16:9 aspect ratio. Compressing the V size with the JMPSW register used in mode 5) above, compresses the V size to 67%. Therefore, V-ASPECT is set to enlarge the V size by 8%. AKB reference pulse handling and V blanking are the same as for mode 5) above. 4:3 CRT standard values are used with the V-ASPECT and JMPSW settings changed for the register settings. V-ASPECT = 3FH JMPSW = 1 3. Signal processing The CXA2025AS is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus. 1) Sync signal processing The Y signals input to Pins 43 and 44 are sync separated by the horizontal and vertical sync separation circuits. The resulting horizontal sync signal and the signal obtained by frequency dividing the 32 FH-VCO output using the ceramic oscillator (frequency 503.5kHz) by 32 are phase-compared, the AFC loop is constructed, and an H pulse synchronized with the H sync is generated inside the IC. Adjustment of the H oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output to the status register (HLOCK) and that can be used to detect the presence of the video signal. The vertical sync signal is sent to the V countdown block where the most appropriate window processing is performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then generated from this reset timing. – 29 – CXA2025AS 2) H deflection signal processing The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin 36 to control the phase of the HDRIVE output and the horizontal position of the image projected on the CRT. In addition, the compensation signal generated from the V sawtooth wave changes the phase of HDRIVE.As a result,the vertical picture distortion is compensated. The H deflection pulse is used to H blank the video signal. When the pulse input from Pin 36 has a narrow width, the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse. (HBLKSW) Pin 36 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output goes to high level (DC) and 1 is output to the status register (HNG). To release this status, turn the power off and then on again. 3) V deflection signal processing The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals. 4) Y signal processing The Y signal input to Pin 4 (specified input level: level at which a 100% white (including sync, 140 IRE) signal with a gain of 6dB with respect to the video signal standard becomes a 2Vp-p signal) passes through the subcontrast control, trap for eliminating the chroma signal, sharpness control, clamp and black expansion circuits, and is then input to the switching circuit (YUV SW) for the external Y/color difference signal. The differential waveform of the Y signal delayed for approximately 200ns from the Y input is output from Pin 45 as the signal for VM. The VM signal is not output in the following cases. When EY-SW = 0 and YUV SW (Pin 9) or YS (Pin 15) = high When EY-SW = 1 and YS (Pin 15) = high The f0 of the built-in filter is automatically adjusted inside the IC, but the trap f0 may require fine adjustment by the I2C bus (CTRAP-ADJ) if it is affected by variation. When inputting a signal which has been Y/C separated by a comb filter, etc., the trap should be turned OFF. 5) C signal processing The chroma signal input to Pin 5 (specified input level: level at which a 40 IRE burst level signal with a gain of 6dB with respect to the video signal standard becomes a 570mVp-p signal) passes through the ACC, TOT (secondary HPF), color control and demodulation circuits. The signal then becomes the R-Y and B-Y color difference signal and is input to the YUV SW circuit. When the burst level goes to –31dB or less with respect to the specified input level, the color killer operates and the color difference signal is not output. The external Y, color difference signals input to Pins 10, 11 and 12 passes through the clamp and amplifier circuits and are input to the YUV SW circuit. The YUV SW circuit is controlled by the YUV SW (Pin 9). However, its operation differs depending on the data in the I2C bus register (EY-SW). In other words, the YUV SW circuit output is as follows. When EY-SW = 0: Internal Y/color difference signal when YUV SW = low, external Y/color difference signal (Pins 9, 10 and 11) when YUV SW = high When EY-SW = 1: Internal Y/color difference signal when YUV SW = low, internal Y/external color difference signal when YUV SW = high When external Y/color difference signal is selected , the picture quality can be adjusted in the same manner as with the normal internal Y signal by setting EY-SW to 1 and then inputting the external Y signal to YIN (Pin 4). However, in this case the relative time difference between the Y and color difference signals must be realigned. The specified input level for the external Y signal is the level at which a normal video signal standard, 100 IRE, 100% white signal becomes a 0.7Vp-p signal. The specified input level for the external color difference signal is the level at which a normal video signal standard, 40 IRE burst level demodulates a 258mVp-p chroma signal at orthogonal coordinates to become a 0.8 times signal (R-Y is demodulated by the 90° axis to become a 1.14 times signal, B-Y is demodulated by the 0° axis to become a 2.03 times signal). – 30 – CXA2025AS The G-Y signal is generated as the base of Y, color difference signals at the axis adjustment circuit.The Y signal is added to R-Y, G-Y, and B-Y respectively and these signals become R, G, and B signals.And they are input to the RGB block. 6) RGB signal processing The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the switch circuit for the external RGB signal (YS SW), the picture control, dynamic color, gamma compensation, clamp, brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are output to Pins 20, 22 and 24. The RGB signals input to Pins 16, 17 and 18 are the level at which a normal video standard, 100 IRE, 100% white signal becomes a 0.7Vp-p signal. The voltage applied to Pin 26 (ABLIN) is compared with the internal reference voltage, integrated by the capacitor which is connected to Pin 27, and performs picture control and brightness control. In order to adjust the white balance (black balance), this IC has a drive control function which adjusts the gain between the RGB outputs and a cut-off control function which adjusts the DC level between the RGB outputs. Both drive control and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch variable. An auto cut-off function (AKB) which forms a loop between the IC and CRT and performs adjustment automatically has also been added. This function can compensate for changes in the CRT with time. Auto cut-off operation is as follows. • R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and is output from each R, G and B output pin. • The cathode current (IK) of each R, G and B output is converted to a voltage and input to Pin 25. • The voltage input to Pin 25 is compared with the reference voltage in the IC, and the current generated by the resulting error voltage charges the capacitors connected to Pins 19, 21 and 23 for the reference pulse interval and is held during all other interval. • The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin voltage so that the Pin 25 voltage matches the reference voltage in the IC. The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus. During G/B-CUTOFF center status, the loop functions so that the Rch for the reference pulse input to Pin 25 is 1Vp-p and the G and Bch are 0.83Vp-p. The reference pulse timing can be varied by the I2C bus. When AKB is not used, the IC can be set to manual cut-off adjustment mode with I2C bus settings. In this case, the DC level of the R, G and B outputs can be varied by applying voltages independently to Pins 19, 21 and 23. 4. Notes on operation When designing the board pattern for the CXA2025AS, interference from around the power supply and GND should be considered as the RGB and deflection signals output from the CXA2025AS are DC direct connected. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the bypass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire signal lines near this pin. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low impedance, as these signals are clamped when they are input using the capacitor connected to the input pin. The built-in capacitor receives the chroma signal, so apply a DC bias of about VCC/2 externally and input the chroma signal at a sufficiently low impedance. – 31 – CXA2025AS Curve Data I2C bus data conforms to the “I2C bus register initial settings” of the Electrical Characteristics Measurement Conditions (P. 13). V-POSITION 3.6 3.4 3.4 3.2 3.2 V [V] V [V] V-SIZE 3.6 3.0 2.8 3.0 2.8 VSIZE = 0 VSIZE = 1F VSIZE = 3F 2.6 V-POSITION = 0 V-POSITION = 1F V-POSITION = 3F 2.6 2.4 2.4 0 5 10 15 20 0 5 Time [ms] S-CORR 15 20 V-LIN 3.6 3.6 3.4 3.4 3.2 3.2 V [V] V [V] 10 Time [ms] 3.0 3.0 2.8 2.8 SCORR = 0 SCORR = 7 SCORR = F 2.6 VLIN = 0 VLIN = 7 VLIN = F 2.6 2.4 2.4 0 5 10 15 20 0 5 Time [ms] 10 15 20 Time [ms] V-ASPECT V-SCROLL 3.8 3.8 3.6 3.6 3.4 3.4 V [V] V [V] 3.2 3.0 3.2 3.0 2.8 2.8 2.6 VASPECT = 0 VASPECT = 1F VASPECT = 3F 2.4 VSCROLL = 0 VSCROLL = 1F VSCROLL = 3F 2.6 2.2 2.4 0 5 10 15 20 0 Time [ms] 5 10 Time [ms] – 32 – 15 20 CXA2025AS LO-VLIN 3.6 3.4 3.4 3.2 3.2 V [V] V [V] UP-VLIN 3.6 3.0 2.8 3.0 2.8 DATA-0 DATA-7 DATA-F 2.6 LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = F 2.6 2.4 2.4 0 5 10 15 20 0 5 Time [ms] 10 15 20 Time [ms] PIN-COMP PIN-PHASE 4.1 4.2 4.0 4.0 3.9 3.8 V [V] V [V] 3.8 3.6 3.7 3.6 3.4 3.5 PIN-COMP = 0 PIN-COMP = 1F PIN-COMP = 3F 3.2 PIN PHASE = 0 PIN PHASE = 7 PIN PHASE = F 3.4 3.0 3.3 0 5 10 15 20 0 5 Time [ms] 10 15 20 Time [ms] LO-CPIN UP-CPIN 4.1 4.1 4.0 4.0 3.9 3.9 V [V] V [V] 3.8 3.8 3.7 3.7 3.6 3.6 3.5 LO-CPIN = 0 LO-CPIN = 7 LO-CPIN = F 3.5 UP-CPIN = 0 UP-CPIN = 7 UP-CPIN = F 3.4 3.4 3.3 0 5 10 15 20 0 Time [ms] 5 10 Time [ms] – 33 – 15 20 CXA2025AS H-SIZE H POSITION 4.6 3.0 4.4 2.5 4.2 2.0 Time [µs] V [V] 4.0 3.8 3.6 1.5 SYNC center 44 HSIN 1.0 t [µs] 3.4 36 AFCPIN 0.5 HSIZE = 0 HSIZE = 1F HSIZE = 3F 3.2 6µ s 12µs 3.0 0 0 5 10 15 20 0 2 4 6 10 8 12 14 16 12 14 16 DATA Time [ms] CTRAP-ADJ SHARPNESS 5 10 0 5 –5 0 Gain [dB] Gain [dB] –10 –15 –5 –20 –10 –25 SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = F –15 –30 CTRAP = 0 CTRAP = 1 –35 –20 0 1 2 3 4 5 6 7 0 2 4 Frequency [MHz] 6 10 8 Frequency [MHz] PICTURE COLOR 5 10 5 0 Gain [dB] Gain [dB] 0 –5 –5 –10 –10 ∗ COLOR OFF when DATA = 0 (–40dB or less) –15 –15 –20 0 10 20 30 40 50 60 70 0 DATA 10 20 30 40 DATA – 34 – 50 60 70 CXA2025AS SUB CONT 3 2 2 1 1 Gain [dB] Gain [dB] SUB COLOR 3 0 –1 0 –1 –2 –2 –3 –3 –4 –4 0 2 4 6 8 10 12 14 16 0 2 4 6 B-DRIVE, G-DRIVE 3 2 Gain [dB] 1 0 –1 –2 –3 –4 0 10 20 30 40 50 60 70 DATA 12 14 16 BRIGHT control characteristics 0.25 0 –0.5 SUB-BRIGHT = 3F SUB-BRIGHT = 1F SUB-BRIGHT = 0 –1.0 0 07 0F 17 1F 27 2F 37 3F DATA SUB-BRIGHT control characteristics GAMMA control characteristics 0 5.0 –0.1 4.5 4.0 –0.2 Rch output [V] Potential difference between Rch reference pulse level and black level [Vp-p] 10 8 DATA Potential difference between Rch reference pulse level and black level [Vp-p] DATA –0.3 –0.4 –0.5 3.5 3.0 2.5 2.0 1.5 –0.6 0 07 0F 17 1F 27 2F 37 3F GAMMA 0 GAMMA 1 GAMMA 2 GAMMA 3 0 10 20 30 40 50 60 70 80 90 100110 120 DATA YIN input amplitude [IRE] – 35 – CXA2025AS Cut-off control characteristics IKIN reference pulse voltage [V] 4.0 3.5 Rch Gch, Bch IK clamp level 3.0 2.5 0 3 5 7 9 B D F DATA R, G and B output reference pulse potential [V] AKB open loop characteristics 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 Voltage applied to Rch, Gch and Bch sample-and-hold capacitance pins [V] – 36 – CXA2025AS Package Outline Unit: mm + 0.1 5 0.0 0.25 – 48PIN SDIP (PLASTIC) 600mil + 0.4 43.2 – 0.1 25 15.24 + 0.3 13.0 – 0.1 48 1 0° to 15° 24 0.5 ± 0.1 0.9 ± 0.15 + 0.4 4.6 – 0.1 3.0 MIN 0.5 MIN 1.778 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE SDIP-48P-02 LEAD TREATMENT EIAJ CODE SDIP048-P-0600-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 5.1g JEDEC CODE – 37 –