SONY CXD3521GG

CXD3521GG
Interface and Driver IC for LCD
Description
The CXD3521GG is an interface and driver IC for
the color LCD module ACX704AKM/BKM.
Features
• Generates the color LCD module ACX704AKM/BKM
drive pulse.
• Supports standby mode
• Built-in 9-channel reference voltage driver
• Built-in common voltage driver
Applications
PDA, compact LCD monitor, etc.
128 pin TFBGA (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage 1 VDD1
VSS – 0.3 to +4.6
•
•
•
•
Structure
Silicon gate CMOS IC
Supply voltage 2 VDD2
Input voltage
VI
Output voltage
VO
Storage temperature
Tstg
V
VSS – 0.3 to +6.0
V
VSS – 0.3 to VDD + 0.3 V
VSS – 0.3 to VDD + 0.3 V
–55 to +125
Recommended Operating Conditions
3.0 to 3.6
• Supply voltage 1 VDD1
• Supply voltage 2 VDD2
4.7 to 5.3
• Operating temperature
Topr
–25 to +75
°C
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01408-PS
CXD3521GG
Block Diagram
VDD1 (3.3V)
C10, J6,
L11, M1
VSS1 (GND)
B11, G9,
L2
Serial/Parallel Transform Block
M11, L10, M10, M9
J7, M6, L6, K6
R3 H12
F12, F11, E12, E11
R2 H11
D10, A9, B9, C9
R1 H10
R31, R21, R11, R01
XR31, XR21, XR11, XR01
R32, R22, R12, R02
XR32, XR22, XR12, XR02
L9, M8, L8, K8
G31, G21, G11, G01
M5, L5, K5, J5
XG31, XG21, XG11, XG01
R0 H9
G3 J12
B12, C12, D12, A11
G2 J11
G32, G22, G12, G02
G1 J10
D9, A8, B8, C8
XG32, XG22, XG12, XG02
G0 J9
J8, M7, L7, K7
B31, B21, B11, B01
M4, L4, M3, L3
XB31, XB21, XB11, XB01
B3 K12
B2 K11
C11, D11, A10, B10
B32, B22, B12, B02
B1 K10
D8, A7, B7, C7
B0 K9
XB32, XB22, XB12, XB02
MCK L12
E9 PCO
PCI G11
Power CTR.
H4, H3 HST1, XHST1
Delay
Hsync/DENB G12
H2, H1 HST2, XHST2
H Counter
SLIN E10
Delay
TESTP M12
H Timing Pulse GEN.
TEST A12
V Counter
Vsync G11
K2, K1 HCK1, XHCK1
J2, J1
HCK2, XHCK2
G4, G3, OE1, XOE1,
G2, G1 OE2, XOE2
M2, L1 VST, XVST
CLR F9
V Timing Pulse GEN.
J4, J3
VCK, XVCK
K4, K3 ENB, XENB
Timing Generator Block
VDD2 (5.0V)
B2, D2,
D7
VSS1 (GND)
B4, D3,
F4
F10 TESTO
F3 V0
E2 V1
VH1 F2
VL1 F1
E4 V2
VH2 E1
D1 V3
VL2 E3
VRFSTB A1
Resistor
Array
Block
C1 V4
D4 V5
C3 V6
VH6 C2
VL6 B1
B3 V7
VH8 A2
D5 V8
VL8 C4
A3 VCOM
Reference Voltage Driver Block
–2–
CXD3521GG
Pin Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
VRFSTB
VH8
VCOM
TESTL1
TESTL7
TESTL5
XB22
XG22
XR22
B12
G02
TEST1
VL6
VDD2
V7
VSS2
TESTL8
TESTL4
XB12
XG12
XR12
B02
VSS1
G32
V4
VH6
V6
VL8
TESTL2
TESTL6
XB02
XG02
XR02
VDD1
B32
G22
V3
VDD2
VSS2
V5
V8
TESTL3
VDD2
XB32
XG32
XR32
B22
G12
VH2
V1
VL2
V2
PCO
SLIN
R02
R12
VL1
VH1
V0
VSS2
CLR
TESTO
R22
R32
XOE2
OE2
XOE1
OE1
VSS1
PCI
Vsync
Hsync/
DENB
XHST2
HST2
XHST1
HST1
R0
R1
R2
R3
XHCK2
HCK2
XVCK
VCK
XG01
VDD1
XR31
B31
G0
G1
G2
G3
XHCK1
HCK1
XENB
ENB
XG11
XR01
B01
G01
B0
B1
B2
B3
XVST
VSS1
XB01
XB21
XG21
XR11
B11
G11
G31
R21
VDD1
MCK
VDD1
VST
XB11
XB31
XG31
XR21
B21
G21
R01
R11
R31
TESTP
A
B
C
D
E
F
G
H
J
K
L
M
–3–
CXD3521GG
Pin Description
Pin
No.
Symbol
I/O
Description
Input pin for
open status
B11
VSS1
—
GND (Logic)
—
G9
VSS1
—
GND (Logic)
—
L2
VSS1
—
GND (Logic)
—
C10
VDD1
—
Power supply (3.3V)
—
J6
VDD1
—
Power supply (3.3V)
—
L11
VDD1
—
Power supply (3.3V)
—
M1
VDD1
—
Power supply (3.3V)
F9
CLR
I
System reset (Cleared at 0V)
—
UP∗
H12
R3
I
Red signal input (MSB)
—
H11
R2
I
Red signal input
—
H10
R1
I
Red signal input
—
H9
R0
I
Red signal input (LSB)
—
J12
G3
I
Green signal input (MSB)
—
J11
G2
I
Green signal input
—
J10
G1
I
Green signal input
—
J9
G0
I
Green signal input (LSB)
—
K12
B3
I
Blue signal input (MSB)
—
K11
B2
I
Blue signal input
—
K10
B1
I
Blue signal input
—
K9
B0
I
Blue pulse input (LSB)
—
G12
Hsync/DENB
I
Hsync pulse input/Data enable signal input
—
G11
Vsync
I
Vsync pulse input
—
L12
MCK
I
Dot clock input
—
G10
PCI
I
Power control signal input
—
E10
SLIN
I
Sync input signal mode selector switch
—
F10
TESTO
O
Test output (Leave it open.)
—
E9
PCO
O
Power control signal output
—
M11
R31
O
Red signal output
—
L10
R21
O
Red signal output
—
M10
R11
O
Red signal output
—
M9
R01
O
Red signal output
—
L9
G31
O
Green signal output
—
M8
G21
O
Green signal output
—
L8
G11
O
Green signal output
—
K8
G01
O
Green signal output
—
J8
B31
O
Blue signal output
—
∗ UP: Pull-up (typ. 160kΩ)
–4–
CXD3521GG
Pin
No.
Symbol
I/O
Description
Input pin for
open status
M7
B21
O
Blue signal output
—
L7
B11
O
Blue signal output
—
K7
B01
O
Blue signal output
—
J7
XR31
O
R31 signal inversion output
—
M6
XR21
O
R21 signal inversion output
—
L6
XR11
O
R11 signal inversion output
—
K6
XR01
O
R01 signal inversion output
—
M5
XG31
O
G31 signal inversion output
—
L5
XG21
O
G21 signal inversion output
—
K5
XG11
O
G11 signal inversion output
—
J5
XG01
O
G01 signal inversion output
—
M4
XB31
O
B31 signal inversion output
—
L4
XB21
O
B21 signal inversion output
—
M3
XB11
O
B11 signal inversion output
—
L3
XB01
O
B01 signal inversion output
—
M12
TESTP
I
Test input (Connect to GND.)
—
A12
TEST
I
Test input (Connect to GND.)
DWN∗
M2
VST
O
VST pulse output
—
L1
XVST
O
VST pulse inversion output
—
K4
ENB
O
ENB pulse output
—
K3
XENB
O
ENB pulse inversion output
—
J4
VCK
O
VCK pulse output
—
J3
XVCK
O
VCK pulse inversion output
—
K2
HCK1
O
HCK1 pulse output
—
K1
XHCK1
O
HCK1 pulse inversion output
—
J2
HCK2
O
HCK2 pulse output
—
J1
XHCK2
O
HCK2 pulse inversion output
—
H4
HST1
O
HST1 pulse output
—
H3
XHST1
O
HST1 pulse inversion output
—
H2
HST2
O
HST2 pulse output
—
H1
XHST2
O
HST2 pulse inversion output
—
G4
OE1
O
OE1 pulse output
—
G3
XOE1
O
OE1 pulse inversion output
—
G2
OE2
O
OE2 pulse output
—
G1
XOE2
O
OE2 pulse inversion output
—
D8
XB32
O
B32 signal inversion output
—
A7
XB22
O
B22 signal inversion output
—
∗ DWN: Pull-down (typ. 180kΩ)
–5–
CXD3521GG
Pin
No.
Symbol
I/O
Description
Input pin for
open status
B7
XB12
O
B12 signal inversion output
—
C7
XB02
O
B02 signal inversion output
—
D9
XG32
O
G32 signal inversion output
—
A8
XG22
O
G22 signal inversion output
—
B8
XG12
O
G12 signal inversion output
—
C8
XG02
O
G02 signal inversion output
—
D10
XR32
O
R32 signal inversion output
—
A9
XR22
O
R22 signal inversion output
—
B9
XR12
O
R12 signal inversion output
—
C9
XR02
O
R02 signal inversion output
—
C11
B32
O
Blue signal output
—
D11
B22
O
Blue signal output
—
A10
B12
O
Blue signal output
—
B10
B02
O
Blue signal output
—
B12
G32
O
Green signal output
—
C12
G22
O
Green signal output
—
D12
G12
O
Green signal output
—
A11
G02
O
Green signal output
—
F12
R32
O
Red signal output
—
F11
R22
O
Red signal output
—
E12
R12
O
Red signal output
—
E11
R02
O
Red signal output
—
B4
VSS2
—
GND (Analog)
—
D3
VSS2
—
GND (Analog)
—
F4
VSS2
—
GND (Analog)
—
B2
VDD2
—
Power supply (5.0V)
—
D2
VDD2
—
Power supply (5.0V)
—
D7
VDD2
—
Power supply (5.0V)
—
A4
TESTL1
O
Test output (Leave it open.)
—
C5
TESTL2
O
Test output (Leave it open.)
—
D6
TESTL3
I
Test input (Connect to GND.)
DWN∗
B6
TESTL4
I
Test input (Connect to GND.)
—
A6
TESTL5
O
Test output (Leave it open.)
—
A5
TESTL6
I
Test input (Connect to GND.)
—
C6
TESTL7
I
Test input (Connect to GND.)
—
B5
TESTL8
I
Test input (Connect to GND.)
—
F3
V0
O
V0 output
—
∗ DWN: Pull-down (typ. 180kΩ)
–6–
CXD3521GG
Pin
No.
Symbol
I/O
Description
Input pin for
open status
E2
V1
O
V1 output
—
E4
V2
O
V2 output
—
D1
V3
O
V3 output
—
C1
V4
O
V4 output
—
D4
V5
O
V5 output
—
C3
V6
O
V6 output
—
B3
V7
O
V7 output
—
D5
V8
O
V8 output
—
A3
VCOM
O
VCOM output
—
A1
VRFSTB
I
Reference voltage driver on/off selector switch
F2
VH1
I
VH1 input
—
F1
VL1
I
VL1 input
—
E1
VH2
I
VH2 input
—
E3
VL2
I
VL2 input
—
C2
VH6
I
VH6 input
—
B1
VL6
I
VL6 input
—
A2
VH8
I
VH8 input
—
C4
VL8
I
VL8 input
—
∗ DWN: Pull-down (typ. 180kΩ)
–7–
DWN∗
CXD3521GG
Electrical Characteristics (Serial/parallel conversion block, timing generator block)
DC Characteristics
Item
(VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Symbol
Applicable pins
Conditions
Min.
Typ.
Max.
Unit
Supply voltage
VDD1
VDD1
—
3.0
3.3
3.6
V
Current
consumption
IDD1
VDD1
No load, Ta = 25°C
VDD1 = 3.3V,
MCK: 5.62MHz
—
1.5
—
mA
VIH1
MCK, VRFSTB,
TESTL1, TESTL2,
TESTL3, TESTL4
0.7VDD1
—
—
CMOS input cell
—
—
0.2VDD1
All input pins excluding
MCK, VRFSTB,
TESTL1, TESTL2,
TESTL3, TESTL4
CMOS
Schmitt trigger
input cell
—
—
0.75VDD1
0.15VDD1
—
—
VI = 0V
—
—
1.0
VI = VDD
—
—
1.0
VI = 0V
10
—
100
VI = VDD
—
—
3.0
VI = 0V
—
—
3.0
VI = VDD
10
—
100
—
—
0.2
Input voltage 1
VIL1
Vt+
Input voltage 2
Vt–
| IIL1 |
Input current 1
| IIH1 |
Input current 2
Input current 3
| IIL2 |
| IIH2 |
| IIL3 |
R0, R1, R2, R3, G0, G1,
G2, G3, B0, B1, B2, B3,
Hsync/DENB, Vsync,
MCK, PCI
CLR
TEST, TESTP, SLIN
| IIH3 |
VOL1
Output voltage 1
VOH1
VOL2
Output voltage 2
VOH2
VOL3
Output voltage 3
VOH3
V
V
µA
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32, IOL1 = 4.0mA
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32, IOH1 = –4.0mA
VST, XVST, ENB, XENB,
OE1, XOE1, OE2, XOE2,
TESTO
µA
µA
V
VDD – 0.8
—
—
—
—
0.2
HST1, XHST1, HST2,
XHST2, VCK, XVCK,
PCO
IOL2 = 6.0mA
IOH2 = –6.0mA
VDD – 0.8
—
—
HCK1, XHCK1,
HCK2, XHCK2
IOL3 = 10.0mA
—
—
0.4
—
—
V
IOH3 = –10.0mA VDD – 0.8
–8–
V
CXD3521GG
AC Characteristics
Item
HCK/HST time
difference
Data output
rise time
(VDD = 3.0 to 3.6V, Ta = –25 to +75°C)
Symbol
∆tHST-HCKU
∆tHST-HCKD
tRD
Data output
fall time
tFD
Horizontal pulse
output rise time
tRHP
Horizontal pulse
output fall time
tFHP
Vertical pulse
output rise time
tRVP
Vertical pulse
output fall time
tFVP
Applicable pins
Conditions∗1
Min.
Typ.
Max.
Unit
—
—
—
15∗2
ns
GND – VDD
(0 – 90%)
—
—
35
HCK1, HCK2, XHCK1,
XHCK2, HST1, HST2,
XHST1, XHST2
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
ns
VDD – GND
(100 – 10%)
—
—
35
HCK1, HCK2,
XHCK1, XHCK2,
HST1, HST2,
XHST1, XHST2
GND – VDD
(0 – 90%)
—
—
35
VDD – GND
(100 – 10%)
—
—
35
VCK, XVCK, VST, XVST,
ENB, XENB, OE1, OE2,
XOE1, XOE2, PCO,
TESTO
GND – VDD
(0 – 90%)
—
—
50
VDD – GND
(100 – 10%)
—
—
50
∗3
35
55
100
ns
∗4
48
50
52
%
HCK1, HCK2,
XHCK1, XHCK2/
DATA setup time
tSTP
HCK1, HCK2,
XHCK1, XHCK2,
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
HCK, VCK duty
dHCK
dVCK
HCK1, HCK2, XHCK1,
XHCK2, VCK, XVCK
ns
ns
∗1 Load capacitance CL of each output pin is shown below.
• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01,
G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01,
B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, OE1, XOE1,
OE2, XOE2, TESTO, ENB, XENB
: CL = 70pF
• HCK1, HCK2, XHCK1, XHCK2
: CL = 180pF
• VCK, XVCK
: CL = 150pF
• HST1, HST2, XHST1, XHST2, VST, XVST, PCO : CL = 100pF
∗2 Absolute value of the time difference of the change point at HST1, XHST1, HCK1 and XHCK1 (50%) is
within 15ns.
Similarly, absolute value of the time difference of the change point at HST2, XHST2, HCK2 and XHCK2
(50%) is within 15ns.
∗3 tSTP: tST1D, tST1U, tST2D, tST2U
∗4 dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100
–9–
CXD3521GG
Timing Definition
Horizontal System
tHL
tHH
VDD1
HCK1
50%
50%
50%
GND
VDD1
50%
XHCK1
50%
GND
∆tH
∆tH
VDD1
HCK2
50%
50%
GND
VDD1
50%
XHCK2
50%
GND
∆tH
∆tH
VDD1
HST1
(HST2)
50%
GND
VDD1
50%
XHST1
(XHST2)
GND
VDD1
HCK1
(HCK2)
50%
GND
VDD1
50%
XHCK1
(XHCK2)
GND
∆tHST-HCKU
∆tHST-HCKD
– 10 –
CXD3521GG
Vertical System
tVL
tVH
VDD1
VCK
50%
50%
50%
GND
VDD1
XVCK
50%
50%
GND
∆tV
∆tV
DATA
VDD1
HCK1
50%
50%
GND
VDD1
50%
XHCK1
50%
GND
VDD1
HCK2
50%
50%
GND
VDD1
50%
XHCK2
50%
GND
VDD1
DATA
GND
tST1D
tST2D
tST1U
tST2U
tSTX1U
tSTX2U
tSTX1D
tSTX2D
– 11 –
CXD3521GG
PCI, PCO
These pins control to turn power on/off of the ACX704AKM/BKM when the LCD is turned on/off. Connect PCO
to DC-DC converter that can control power on/off of the ACX704AKM/BKM.
Power-on Sequence
• Raise and fall VDD1 and VDD2 simultaneously (within 10ms)
• Input the input signal∗1 for 1 field (Min.), and then raise PCI.
• After PCI becomes high, latch is performed twice at Vsync. When both of them are high, PCO output is
changed from low to high.
(Turn the power on of the ACX704AKM/BKM at this timing.)
Also, effective screen is displayed after two fields of entire white display from this timing.
±10ms
VDD1
VDD1
0
VDD2
VDD2
0
VDD1
CLR
0
PCI
Low
PCO
Low
High
Pulse∗2
Low
Active
DATA (out)
Low
Vsync
Low
DENB
MCK
Hsync
DATA (in)
1
2
High
White Data
Valid
Low
Low
Active
1 field (min.)
1 field (min.)
2 fields
∗1 Hsync, Vsync, DENB, MCK, DATA
∗2 HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,
OE1, XOE1, OE2, XOE2, TESTO, (FRP)
– 12 –
CXD3521GG
Power-off Sequence (Standby)
• When LCD is off, LCD is turned off after entire white display.
±10ms
Standby Mode
PCI
High
Low
High
PCO
Low
VDD1
VDD1
0
VDD2
VDD2
0
DATA
Valid
Pulse∗1
Active
All Data: High (XDATA: Low)
Low
Low
Vsync
Low
DENB
Low
3 fields
MCK
Hsync
DATA (in)
10 fields
Low
Active
∗1 HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,
OE1, XOE1, OE2, XOE2, TESTO, (FRP)
SLIN
This is a selector switch for sync input signal mode.
SLIN: Low → Hsync + Vsync Mode.
SLIN: High → DENB ONLY Mode. (Vsync is invalid.)
– 13 –
Horizontal Direction Input Signal Timing Chart
352 dots
310
315
320
325
335
330
340
345
350
0
5
MCK
Hsync∗1
4 dots (min.)
16 dots
16 dots
DENB∗1
32 dots
DATA
307 308 309 310 311 312 313 314 315 316 317 318 319 320
1
2
3
4
5
6
tch
7
8
9 10 11
tcl
MCK
tclk
thss
Hsync∗1
– 14 –
DENB∗1
thsw
tdes
DATA
tdeh
1
tds
∗1 Input either Hsync + Vsync or DENB as sync input signal.
2
320
tdh
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Item
Symbol
ftch
MCK low, high pulse width
tch, tcl
tds
tdh
tdes
tdeh
thss
thsw
DATA setup time
DATA hold time
DENB setup time
DENB hold time
Hsync setup time
Hsync low pulse width
Typ.
Max.
3MHz
5.58MHz
8MHz
—
0.5tclk
—
10ns
—
—
15ns
—
—
10ns
—
—
15ns
—
—
10ns
—
—
4tclk
—
16tclk
CXD3521GG
MCK frequency
Min.
Vertical Direction Input Signal Timing Chart
264 lines
230
235
240
245
250
255
260
0
5
10
15
Hsync∗1
Vsync∗1
10 lines
14 lines
DENB∗1
Hsync∗1
(2)
(1)
(14)
(15)
– 15 –
tvhde
Vsync∗1
tvsw
DENB∗1
1st Line
DATA
∗1 Input either Hsync + Vsync or DENB as sync input signal.
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Item
Min.
Typ.
Max.
Hsync falling edge
→ Vsync falling edge
tvhde
3tclk
—
352tclk
Vsync low pulse width
tvsw
2 lines
—
14 lines
CXD3521GG
Symbol
Horizontal Direction Timing Chart
280
352 dots
290
300
310
320
330
340
0
10
20
MCK
16 dots
Hsync
16 dots
32 dots
R/G/B
01 to 31
1 23 4 5 6 7 8 9
316
317
318
319
320
Input
DATA
Output
DENB
R/G/B
02 to 32
HST1
270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320
269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 315 317 319
344
4 dots
2
4
6
8
10 12 14 16 18 20 22 24
1
3
5
7
9
11 13 15 17 19 21 23
348
XHST1
HCK1
XHCK1
342 4 dots 346
HST2
– 16 –
XHST2
HCK2
XHCK2
328
OE1
340
XOE1
320
OE2
0
XOE2
304
0
ENB
XENB
350
VST
XVST
334
VCK
334
FRP
CXD3521GG
334
XVCK
Vertical Direction Timing Chart
264 lines
240
245
250
255
260
0
5
10
15
20
Hsync
Vsync
Input
Output
10 lines
DENB
VST
14 lines
XVST
VCK
XVCK
– 17 –
ENB
XENB
OE1
XOE1
OE2
XOE2
FRP (O)∗1
FRP (E)∗1
CXD3521GG
∗1 FRP (O): FRP pulse at odd field. FRP (E): FRP pulse at even field.
CXD3521GG
Reference Voltage Driver Block
Block Diagram
VDD2 (5.0V)
VDD2
VH0
V0
VL0
VH1
V1
VL1
VH2
V2
VL2
VH3
V3
VL3
VH4
V4
VL4
VH5
V5
VL5
VH6
V6
VL6
VH7
V7
VL7
VH8
V8
VL8
VCOM
VSS2
Resistor array
VRFSTB
Level Shift
FRP∗1
Level Shift
VSS2
∗1 Internal pulse of the logic block
Electrical Characteristics (Reference voltage driver block)
Resistor array output voltage
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = 25°C)
Item
Min.
Typ.
Max.
VH0
—
4.800
VH1
—
VH2
Unit
Item
Min.
Typ.
Max.
—
VL0
—
0.200
—
3.900
—
VL1
—
1.100
—
—
3.325
—
VL2
—
1.675
—
VH3
—
2.950
—
VL3
—
2.050
—
VH4
—
2.600
—
VL4
—
2.400
—
VH5
—
2.250
—
VL5
—
2.750
—
VH6
—
1.950
—
VL6
—
3.050
—
VH7
—
1.500
—
VL7
—
3.500
—
VH8
—
0.500
—
VL8
—
4.500
—
V
– 18 –
Unit
V
CXD3521GG
AC, DC Characteristics
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = –25 to +75°C)
Conditions
Min.
Typ.
Max.
Unit
—
4.7
5.0
5.3
V
Input voltage = 2.5V,
During no load
—
3.4
6.0
mA
VH, VL input current high IIH
Input voltage = 4.8V
–0.15
—
0.15
µA
VH, VL input current low
IIL
Input voltage = 0.2V
–0.15
—
0.15
µA
Voltage gain
AV
Input voltage = 0.2 to 4.8V
0.985
—
—
V/V
Output voltage high
VOH
ISOURCE = 10mA
VDD2 – 1.0
—
—
V
Output voltage low
VOL
ISINK = 10mA
—
—
GND + 1.0
V
COM output voltage high
VCOH
ISOURCE = 10mA
VDD2 – 0.1
—
—
V
COM output voltage low
VCOL
ISINK = 10mA
—
—
GND + 0.1
V
Offset voltage
VOFF
Rs = 10kΩ
—
—
20
mV
Load regulation
∆VO
Input voltage = 0.2 to 4.8V
ISOURCE = 10mA
ISINK = 10mA
—
±5
±10
mV
Output impedance
RIMP
V0 to V8
—
15
—
Ω
Settling time 1
ts 1
ts 2
ts 3
ts 4
Measurement circuit 1
—
—
10
µs
Measurement circuit 1
—
—
10
µs
Measurement circuit 2
—
—
6
µs
Measurement circuit 2
—
—
6
µs
Item
Symbol
Supply voltage
VDD2
Current consumption
IDD2
Settling time 2
Settling time 3
Settling time 4
– 19 –
CXD3521GG
Measurement Circuit
Measurement circuit 1
4.8V
0.2V
15Ω
VH
Measuring point
V0 to V8
30nF
VL
Measurement circuit 2
5.0V
0V
Measuring point
VCOM
30nF
FRP (internal pulse)
50%
50%
ts1
ts2
90%
Output (V0 to V8)
10%
90%
Output (VCOM)
10%
ts4
ts3
VRFSTB
This is a selector switch for reference voltage driver output on/off.
VRFSTB: Low → V0 to V8 and VCOM are GND level.
VRFSTB: High → V0 to V8 and VCOM are active.
– 20 –
CXD3521GG
To DC-DC Converter∗1
Application Circuit
To ACX704AKM/BKM
VDD2
VDD1
VDD1
B22
B32
B12
B02
XR32
XR22
XR12
XR02
XG32
XG22
XG12
XB32
XG02
XB22
XB12
VDD2
XB02
TESTL5
TESTL7
TESTL6
TESTL3
TESTL4
VSS2
TESTL8
TESTL2
V8
TESTL1
V7
VL8
VH8
VCOM
A2 A3 B3 C4 D5 A4 C5 B4 B5 B6 D6 A5 C6 A6 D7 C7 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9 D10 B10 A10 D11 C11 C10
TEST A12
B1 VL7
VSS1 B11
B2 VDD2
G02 A11
C1 V4
G12 D12
C2 VH7
G22 C12
C3 V6
G32 B12
D1 V3
R02 E11
D2 VDD2
R12 E12
D3 VSS2
R22 F11
D4 V5
R32 F12
E1 VH2
PCO E9
E2 V1
SLIN E10
E3 VL2
CLR
E4 V2
F9
TESTO F10
F1 VL0
VSS1 G9
F2 VH0
PCI G10
F3 V0
Vsync G11
Hsync/DENB G12
R0 H9
G2 OE2
R1 H10
G3 XOE1
R2 H11
G4 OE1
R3 H12
H1 XHST2
G0
H2 HST2
G1 J10
H3 XHST1
G2 J11
H4 HST1
G3 J12
J1 XHCK2
B0 K9
J2 HCK2
B1 K10
J3 XVCK
B2 K11
J4 VCK
J9
Input
F4 VSS2
G1 XOE2
B3 K12
K1 XHCK1
MCK L12
K2 HCK1
VDD1 L11
TESTP
R31
R21
R11
R01
G31
G21
G11
G01
B31
B21
B11
B01
VDD1
XR31
XR21
XR11
XR01
XG31
XG21
XG11
XG01
XB31
XB21
XB11
XB01
XENB
ENB
XVST
VST
VSS1
VDD1
VDD1
To ACX704AKM/BKM
To ACX704AKM/BKM
A1 VRFSTB
M1 L2 M2 L1 K4 K3 L3 M3 L4 M4 J5 K5 L5 M5 K6 L6 M6 J7 J6 K7 L7 M7 J8 K8 L8 M8 L9 M9 M10 L10 M11 M12
To ACX704AKM/BKM
VDD1
∗1 Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM/BKM.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 21 –
CXD3521GG
Package Outline
Unit: mm
128PIN TFBGA (PLASTIC)
11.0
S A
0.3
S B
11.0
0.3
x4
0.20
0.2
S
10.6 ± 0.1
S
0.8
A
1.1
1.1
M
L
K
J
H
G
F
E
D
C
B
A
1.2 MAX
0.1
0.4 ± 0.05
S
0.8
B
1 2 3 4 5 6 7 8 9 10 11 12
128 - φ 0.5 ± 0.05
φ 0.08 M
S A B
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
EIAJ CODE
JEDEC CODE
TFBGA-128P-061
P-TFBGA128-11x11-0.8
ORGANIC SUBSTRATE
TERMINAL TREATMENT
TERMINAL MATERIAL
SOLDER
PACKAGE MASS
0.22g
– 22 –
Sony Corporation