CXL1501M CMOS-CCD Signal Processor For the availability of this product, please contact the sales office. Description The CXL1501M is a CMOS-CCD signal processor designed for 8-mm VCR video signal processing. In combination with the 8-mm VCR video Y/C signal processing IC CXA1200Q, this IC configures a comb filter for Y/C separation in recording an image and elimination of crosstalk in playing back. Features • Single power supply 5V • Low power consumption 225mW (Typ.) • Built-in peripheral circuits • Completely adjustment free • Built-in quadruple progression PLL circuit • For NTSC signals 30 pin SOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage VDD 5 ± 5% V Functions • 1H comb filter output • Dropout compensation (D.O.C) output • Delay time matching through output (THR) • PLL circuit (quadruple progression) • Clock driver • Autobias circuit • Sync tip clamp circuit • Sample and hold circuit Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.4 to 1.0 Vp-p (0.5Vp-p Typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform sine wave Input Signal Amplitude VSIG Structure CMOS-CCD 571 mVp-p (Max.) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E71050-PS 29 CCD1 CLK 22 NC 20 18 19 NC 16 15 14 13 12 11 10 ABP 9 NC 8 VSS 7 VDD 6 NC 5 CCD3 4 ABN 3 ADJC 2 CCD2 VSS Bias circuit (B) Bias circuit (A) 17 VGGA Output circuit, S/H circuit Output circuit, S/H circuit Output circuit, S/H circuit 21 ADJY YD IH + D VCO OUT 23 VDD VSS 1 D D φ1 φ2 24 Clock driver VCO IN Phase comparator 25 VSS 1/4 divider 26 PC OUT 27 VSS VGGB VCO VDD 28 VSS Y-YD –2– Autobias circuit (P) Autobias circuit (N) VSS 30 TH Block Diagram and Pin Configuration (Top View) CXL1501M CXL1501M Pin Description Pin No. Symbol Description I/O Impedance (Ω) 1 VSS 2 CCD2 I Signal input 2 (Reverse phase signal) > 100k (at no clamp) 3 ADJC O Forward phase CCD bias DC output 600 to 2k 4 ABN O Reverse phase autobias DC output 2k to 20k 5 CCD3 I Signal input 3 (Forward phase signal) > 100k (at no clamp) 6 NC — 7 VDD — 5V power supply (For clock driver) 8 VSS — GND 9 NC — 10 ABP O Forward phase autobias DC output 2k to 20k 11 VGGA O Gate bias (A) DC output 2k to 10k 12 YD O D.O.C signal output (Reverse phase signal) 40 to 500 13 VSS — GND 14 VGGB O Gate bias (B) DC output 2k to 10k 15 Y-YD O Comb filter signal output 40 to 500 16 VSS — GND 17 VSS — GND 18 TH O THR signal output (Forward phase signal) 19 VDD — 5V power supply (For analog) 20 ADJY O Reverse phase CCD bias DC output 21 NC — 22 VCO OUT O 23 NC — 24 VSS — 25 CLK I 26 VDD — 5V power supply (For digital) 27 PC OUT O Phase comparator output 2k to 5k 28 VCO IN I VCO input > 100k 29 VSS 30 CCD1 — — I GND 40 to 500 600 to 2k VCO output GND 4k to 40k Clock input GND Signal input 1 (Reverse phase signal) –3– > 100k (at no clamp) –4– S/N ratio S/H pulse coupling Differential phase Differential gain Frequency response High frequency gain Low frequency gain Supply current Item 196.678kHz a a a a b→ ←c a a a a a f DPT b b b — VPT b b b b b b b b b b b b b b b — — — No-signal input∗9 — — VPD SNT SNC SND No-signal input a a a f DPD VPC a a a f DPC a a a f DGD 5-staircase wave∗7 a a f a a a a b→ ←c a b→ ←c a a a a c a 5-staircase wave∗7 150mVp-p sine wave a a a a a c a a a a a c a a a a a a a a a a a a 4 3 2 1 a a a b b b a a a a a a b b b b b b a a a a 5 a a a b b b a a a a a a b b b b b b a a a a 6 a a a b b b a a a a a a b b b b b b a a a a 7 c b a c b a c b a c b a c b a c b a c b a — 8 d d d a a a c c c c c c b b b b b b b b b — 9 — — — — –5.0 35 Min. — VIT — — — VIC — — — VID +0.5 — — — — 0 0 VIT VIC VID –2.5 –0.25 –0.25 +0.25 VIT VIC VID –6.5 –0.25 –0.25 +0.25 — — VBIAS1 VBIAS2 VBIAS3 Bias conditions∗2 (V) –56 — 3 3 –1.5 –4.5 –3.0 45 degree % dB dB dB mA Unit –52 dB 350 mVp-p 7 7 –0.5 –2.5 –1.0 55 Typ. Max. ∗9 ∗8 ∗7 ∗7 ∗6 ∗5 ∗4 ∗3 Note See the Electrical Characteristics Test Circuit. (Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave) SW conditions f DGC DGT fD fc → ← 3.579545MHz fT GHD GHC 196.678kHz 500mVp-p sine wave — 3.579545MHz 150mVp-p sine wave GHT GLD GLC GLT IDD Symbol Test conditions∗1 Electrical Characteristics CXL1501M Chroma comb depth min. gain Item C-CD 3.587412MHz 200mVp-p sine wave → ← 3.579545MHz 200mVp-p sine wave Symbol Test conditions∗1 2 d→ ←e a 1 a 3 a 4 b 5 b 6 SW conditions b 7 b 8 b 9 ∗10 ∗10 ∗10 VBIAS1 VBIAS2 VBIAS3 Bias conditions∗2 (V) — Min. — –27 Typ. Max. dB Unit ∗10 Note CXL1501M –5– CXL1501M Notes) ∗1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an equal value, as well as the phase difference to a precise 180°. Also set the clock and input signal frequency accurately. ∗2 VIT, VIC and VID are defined as follows: VIT, VIC and VID are input signal clamp levels. They clamps the Video signal sync tip level. They are the pin voltages at no-input signal for pins 30, 2 and 5, respectively. VIT Input (CCD1) 30 L1501 5 2 Input (CCD2) VIC VID Input (CCD3) Testing of VIT, VIC and VID is executed with a voltmeter under the following SW conditions: SW conditions 1 2 3 4 5 6 7 8 9 10 11 Test point VIT — b b b a a a — — — — V1 VIC — b b b a a a — — — — V2 VID — b b b a a a — — — — V3 Item As VIT, VIC and VID differ with each IC, they are to be tested respectively. ∗3 This is the IC supply current value during clock and signal input. ∗4 GLT, GLC and GLD are output gains of TH, Y-YD, and YD pins when a 500mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. (Example of calculation) GLT = 20 log TH pin output voltage [mVp-p] 500 [mVp-p] [dB] –6– CXL1501M ∗5 GHT, GHC, and GHD are output gains of TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. Bias at input (VBIAS1, VBIAS2 and VBIAS3) is tested respectively at VIT – 0.25V, VIC – 0.25V and VID + 0.25V. (Example of calculation) GHT = 20 log TH pin output voltage [mVp-p] 150 [mVp-p] [dB] ∗6 Indicates the dissipation at 3.579545MHz in relation to 196.678kHz. From the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins, and from the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to same, calculation is made according to the following formula. The input block bias for VBIAS1, VBIAS2 and VBIAS3 is tested at VIT – 0.25V, VIC – 0.25V and VID + 0.25V, respectively. (Example of calculation) fT = 20 log TH pin output voltage (3.579545MHz) [mVp-p] TH pin output voltage (196.678kHz) [mVp-p] [dB] ∗7 The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 143mV 357mV 500mV 143mV 1H 63.56µs CCD3 pin input waveform (the input waveform of CCD1 and CCD2 pins is the inverted waveform of the figure above.) ∗8 The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input block bias is tested at VITV, VICV, and VID + 0.5V. Test value [mVp-p] –7– CXL1501M ∗9 The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 4MHz. Vn [Vrms] The signal component is determined either by testing the output voltage (the same test system as that of noise level) at input of 357mVp-p, 196.678kHz, or by performing calculation from the values of GLT, GLC, and GLD in accordance with the following formula. Vs [Vp-p] (Example of Vs calculation) VS-T = 0.357 × 10 GLT 20 (VS-T: TH output voltage) (Example of S/N ratio calculation) SNT = 20 log Vn-T (noise component) [Vrms] [dB] VS-T (signal component) [Vp-p] ∗10 C-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a 200mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins and from the YCD pin output voltage when a 200mVp-p, 3.587412MHz sine wave is simultaneously fed to same. The input block bias is set to VIT – 0.3V, VIC – 0.3V and VID + 0.3V, respectively. C-CD = 20 log Y-YD pin output voltage (3.587412MHz) [mVp-p] [dB] Y-YD pin output voltage (3.579545MHz) [mVp-p] CLOCK fsc (3.579545MHz) sine wave 0.4Vp-p to 1.0Vp-p (0.5Vp-p Typ.) –8– CXL1501M Electrical Characteristics Test Circuit 9V CLK fSC (3.579545MHz) 0.5Vp-p a SW2 sine wave b 1µ SW5 2.2µ 120 19 18 17 16 VDD TH VSS VSS 0.01µ 20 NC VCO OUT a SW3 3.3µ 21 ADJY 22 NC CCD1 23 a Oscilloscope SW8 a SW9 b b 3 4 5 6 1µ 7 8 9 10 11 Y-YD 2 VGGB 1 a YD b 1M VSS SW6 VGGA 1µ ABP b SW1 NC c NC f 24 CCD3 5-staircase wave 25 ABN e 1µ 0.01µ 26 ADJC 3.587412MHz 200mVp-p sine wave 27 CCD2 d 28 NC –1 29 VSS 3.3µ 30 3.579545MHz 200mVp-p sine wave 82k VDD c 0.1µ 4.7µ VDD 3.579545MHz 150mVp-p sine wave 1M CLK b a PC OUT 196.678kHz 150mVp-p sine wave b VSS a VCO IN 196.678kHz 500mVp-p sine wave VSS –1 1.2k 12 13 14 15 c 9V d 1.2k Spectrum analyzer ∗1 ×3 Vector LPF scope ×3 Noise BPF meter ∗2 1µ 1µ 1µ 1µ 9V 0.01µ 3.3µ 1.2k –1 a SW4 b 1µ SW7 51k ∗1) LPF frequency response 1M b 51k 5V a 51k VBIAS1 VBIAS3 V1 V2 ∗ 2) BPF frequency response [dB] 0 –3 [dB] 0 –3 V3 –50 –50 VBIAS2 0 6M Frequency [Hz] 0 200 14.3M 6M Frequency [Hz] 14.3M Application Circuit fSC 0.5Vp-p sine wave 1.2k 1µ 2.2µ 4.7µ 120 CCD1 input (Reverse phase signal) TH output (Forward phase signal) 0.1µ 1M 82k 3.3µ 1µ 0.01µ 3.3µ 0.01µ 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1µ CCD2 input (Reverse phase signal) 1.2k Y-YD output 1µ 1µ 1M 1µ 1µ 1µ 3.3µ 0.01µ 9V 1µ CCD3 input (Forward phase signal) 1M 1.2k 9V 5V 1.8k 2SC403 Transistor used PNP : 2SA1175 YD output (Reverse phase signal) 22 Composite video signal input 4fsc Signal output 1.8k When using pin 22 (4 × fsc output) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXL1501M Low frequency gain vs. Supply voltage High frequency gain vs. Supply voltage High frequency gain [dB] Low frequency gain [dB] –1 –2 –3 –4 –3 –4 –5 –6 –5 4.75 5.0 VDD – Supply voltage [V] 4.75 5.25 Frequency response vs. Supply voltage 5.0 VDD – Supply voltage [V] 5.25 Differential gain vs. Supply voltage 8 0 Differential gain [%] Frequency response [dB] 10 –1 –2 4 2 –3 4.75 6 5.0 VDD – Supply voltage [V] 0 4.75 5.25 5.0 VDD – Supply voltage [V] High frequency gain vs. Ambient temperature Low frequency gain vs. Ambient temperature High frequency gain [dB] Low frequency gain [dB] –1 –2 –3 –4 5.25 –3 –4 –5 –6 –5 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] – 10 – CXL1501M Frequency response vs. Ambient temperature Differential gain vs. Ambient temperature 0 8 Differential gain [%] Frequency response [dB] 10 –1 –2 –3 6 4 2 20 40 60 0 Ta – Ambient temperature [°C] Chroma comb depth min. gain vs. Supply voltage Chroma comb depth min. gain vs. Ambient temperature –10 Chroma comb depth min. gain [dB] Chroma comb depth min. gain [dB] 0 40 60 0 20 Ta – Ambient temperature [°C] –20 –30 –40 –10 –20 –30 –40 –50 –50 4.75 5.00 VDD – Supply voltage [V] 5.25 0 20 40 60 Ta – Ambient temperature [°C] Frequency response (TH, YD Output) Chroma comb response (Y-YD Output) 0 0 –10 Gain [dB] Gain [dB] –2 –4 –6 –20 –30 –8 10k 100k f – Frequency [Hz] –40 1M 3.57 – 11 – 3.58 f – Frequency [MHz] 3.59 CXL1501M Package Outline Unit: mm 30PIN SOP (PLASTIC) + 0.4 2.3 – 0.15 + 0.4 18.8 – 0.1 16 15 1 1.27 0.45 ± 0.1 0.24 + 0.2 0.1 – 0.05 0.5 ± 0.2 9.3 ± 0.3 10.3 ± 0.4 0.15 + 0.3 7.6 – 0.1 30 + 0.1 0.15 – 0.05 M PACKAGE STRUCTURE SONY CODE EIAJ CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING SOP-30P-L01 SOP030-P-0375 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.7g JEDEC CODE – 12 –