CXL1502M CMOS-CCD Signal Processor For the availability of this product, please contact the sales office. Description The CXL1502M is a CMOS-CCD signal processor designed for 8-mm video signal processing. In combination with the 8-mm video Y/C signal processing IC CXA1200Q, this IC configures a comb filter for Y/C separation in recording an image, elimination of line crawling and crosstalk in playing back. Features • Single power supply 5V • Low power consumption • Built-in peripheral circuits • Completely adjustment free • Built-in triple progression PLL circuit • For PAL signals 30 pin SOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage VDD 5 ± 5% V Functions • 1H comb filter, 2H comb filter output • Dropout compensation • PLL circuit (triple progression) • Clock driver • Autobias circuit • Sync tip clamp circuit • Sample and hold circuit • Delay time matching through output (THR) Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.4Vp-p Typ.) • Clock frequency fCLK 4.433619 MHz • Input clock waveform sine wave Input Signal Amplitude VSIG Structure CMOS-CCD 575 mVp-p (Max.) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E80334-PS 29 CCD3 CLK 18 19 15 14 13 12 11 10 9 8 7 6 5 4 ADJC 3 CCD2-C 2 CCDY 1 VSS Bias circuit (B) CCD1 Output circuit, S/H circuit Output circuit, S/H circuit Output circuit, S/H circuit 16 Bias circuit (A) 17 NC VSS VDD VCO OUT VSS D D D 20 Output circuit, S/H circuit 21 VSS NC 22 ADJY ABN 23 YD TH 2H + D φ1 φ2 24 Clock driver VCO IN Phase comparator 25 VSS 1/3 divider 26 PC OUT 27 VDD VGGA VCO VDD 28 VSS VGGB Autobias circuit (N) Autobias circuit (P) ABP 30 Y-YD C-CD –2– VSS Block Diagram CXL1502M CXL1502M Pin Description Pin No. Symbol Description I/O Impedance (Ω) 1 VSS 2 CCDY I Signal input 4 (Reverse phase signal) > 100k (at no clamp) 3 CCD2-C I Signal input 2 (Reverse phase signal) > 100k (at no clamp) 4 ADJC O Forward CCD bias DC output 600 to 2k 5 CCD1 I Signal input 1 (Reverse phase signal) > 100k (at no clamp) 6 NC — 7 VDD — 5V power supply 8 VSS — GND 9 NC — 10 ABN O Reverse phase autobias DC output 2k to 200k 11 TH O THR signal output (Forward phase signal) 40 to 500 12 VGGA O Gate bias (A) DC output 2k to 10k 13 VGGB O Gate bias (B) DC output 2k to 10k 14 C-CD O 2H comb filter signal output 40 to 500 15 VSS — GND 16 Y-YD O 1H comb filter signal output 17 VSS — GND 18 VDD — 5V power supply 19 YD O DOC signal output (Reverse phase signal) 40 to 500 20 ADJY O Reverse phase CCD bias DC output 600 to 2k 21 VSS — GND 22 VCO OUT O VCO output 23 VSS — GND 24 VSS — GND 25 CLK I 26 VDD — 5V power supply 27 PC OUT O Phase comparator output 2k to 5k 28 VCO IN I VCO input > 100k 29 ABP O Forward phase autobias DC output 2k to 200k 30 CCD3 I Signal input 3 (Forward phase signal) > 100k (at no clamp) — GND 40 to 500 4k to 40k Clock input –3– –4– Differential phase Differential gain Frequency response High frequency gain Low frequency gain Supply current Item a a c a a a a a a a a a a a a a a a a a a a a b← →c b← →c b← →c h h h h h h h h DGC DGY DGT DPC DPY DPT DPD DGD fT fD fY 5-staircase wave∗7 5-staircase wave∗7 a a a a 203.126kHz ← → 4.437525MHz 150mVp-p sine wave b← →c fc GHT a a a c GHD GHY a a a c GHC c a a a GLT 4.437525MHz 150mVp-p sine wave a a GLD GLY a a a a a a a a a 203.126kHz 500mVp-p sine wave — 3 2 1 a GLC IDD Symbol Test conditions∗1 Electrical Characteristics a a a a a a a a a a a a a a a a a a a a a 4 a a a a a a a a a a a a a a a a a a a a a 5 a a a a a a a a b b b b b b b b a a a a a 6 a a a a a a a a b b b b b b b b a a a a a 7 a a a a a a a a b b b b b b b b a a a a a 8 SW conditions a a a a a a a a b b b b b b b b a a a a d a b c d a b c d a b c d a b c d a b c c c c c c c c c b b b b b b b b b b b b a — — 9 10 11 — — VBIAS 2 — — VBIAS 3 — — VBIAS 4 — — — — — — — — VID VIY VIC VIT +0.25 –0.25 –0.25 –0.25 VID VIY VIC VIT +0.25 –0.25 –0.25 –0.25 — — VBIAS 1 Bias conditions∗2 (V) 0 0 –3.0 –7.0 –5.0 50 Min. 3 3 –2.0 –5.0 –3.0 60 7 7 –1.0 –3.0 –1.0 70 Typ. Max. deg deg dB dB dB mA ∗7 ∗7 ∗6 ∗5 ∗4 ∗3 Unit Note (Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave) See the Electrical Characteristics Test Circuit. CXL1502M –5– Y-comb depth min. gain Chroma comb depth min. gain S/H pulse coupling S/N ratio Item b b b — b No-signal input — b — b VPY VPD VPT YCD CCD 2.000011MHz ← → 1.992198MHz 200mVp-p sine wave 4.437525MHz ← → 4.441431MHz 200mVp-p sine wave f← →g a a a b — b VPC a b b — b SNT d← →e b b — b SND b — b No-signal input∗8 SNY a a b b b b b b b — b SNC 4 3 1 a a b b b b b b b b 5 b b b b b b a a a a 6 b b a a a a a a a a 7 b b a a a a a a a a 8 SW conditions 2 Symbol Test conditions∗1 b b a a a a a a a a b c d a b c d a b c b b a a a a d d d d 9 10 11 VID +0.3 VID +0.3 VID +0.5 — VBIAS 1 VIY –0.3 VIY –0.3 — — VBIAS 2 VIC –0.3 VIC –0.3 — — VBIAS 3 VIT –0.3 VIT –0.3 — — VBIAS 4 Bias conditions∗2 (V) — — — — Min. — — — –56 dB –15 –24 dB dB ∗11 ∗10 ∗9 ∗8 Unit Note 350 mVp-p –52 Typ. Max. CXL1502M –6– 4.433619MHz 500mVp-p sine wave 5-staircase wave 1.992198MHz 150mVp-p sine wave 2.000011MHz 150mVp-p sine wave 4.441431MHz 150mVp-p sine wave 4.437525MHz 150mVp-p sine wave h g f –1 –1 b 1µ 1µ 1µ 51k 51k 51k 51k a SW5 b a SW4 b VBIAS1 VBIAS3 VBIAS2 VBIAS4 e SW1 d c –1 a SW3 V1 b SW7 V2 b SW8 a 1M a V3 b SW9 1M a 30 V4 2 3 22 4 5V 3.3µ 0.01µ 8 9 7 23 6 24 5 25 0.01µ 26 3.3µ 27 1µ 100 28 1k 29 1 1M 1µ ADJC b CCD3 0.1µ CCD1 1M CCD2-C 0.1µ CLK NC SW6 a VSS VDD 203.126kHz 150mVp-p sine wave b ABP VSS VSS 1µ VCO IN VSS PC OUT CCDY VDD VCOOUT NC a 1µ 21 VSS 10 ABN b –50 [dB] 0 –3 20 1µ ADJY 1µ 17 0.01µ 18 12 14 1µ 3.3µ 13 19 0 6M 13.3M Frequency [Hz] NOTE 1) LPF frequency response 11 TH 203.126kHz 500mVp-p sine wave YD VGGA CLK fSC (4.43619MHz) 400mVp-p sine wave VDD VGGB a SW2 VSS C-CD –1 16 Y-YD Fig. 1 –50 [dB] 0 –3 15 VSS Electrical Characteristics Test Circuit 9V 9V 9V 9V c b SW10 d 0 200 6M 13.3M Frequency [Hz] a Oscilloscope Spectrum analyzer NOTE 1) ×3 c Vector LPF scope ×3 d Noise BPF meter NOTE 2) SW11 b a NOTE 2) BPF frequency response 1.2k 1.2k 1.2k 1.2k CXL1502M CXL1502M Notes) ∗1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an equal value, as well as the phase difference to a precise 180°. Also set the clock and input signal frequency accurately. ∗2 VIC, VIY, VID and VIT are defined as follows: VIC, VIY, VID and VIT are input signal clamp levels. They clamps the Video signal sync tip level. They are the pin voltages at no-input signal for pins 3, 2, 30 and 5, respectively. VID Input (CCD3) 30 L1502 2 5 3 Input (CCDY) VIY VIT Input (CCD2-C) VIC Input (CCD1) Testing of VIC, VIY, VID and VIT is executed with a voltmeter under the following SW conditions: SW conditions 1 2 3 4 5 6 7 8 9 10 11 Test point VIC — b b b b a a a a — — V3 VIY — b b b b a a a a — — V2 VID — b b b b a a a a — — V1 VIT — b b b b a a a a — — V4 Item ∗3 This is the IC supply current value during clock and signal input. ∗4 GLC, GLY, GLD and GLT are output gains of C-CD, Y-YD, YD and TH pins when a 500mVp-p, 203.126kHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively. (Example of calculation) GLC = 20 log C-CD pin output voltage [mVp-p] 500 [mVp-p] [dB] –7– CXL1502M ∗5 GHC, GHY, GHD and GHT are output gains of C-CD, Y-YD, YD and TH pins when a 150mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively. Bias at input (VBIAS1, VBIAS2, VBIAS3 and VBIAS4) is tested respectively at VID + 0.25V, VIY – 0.25V, VIC – 0.25V and VIT – 0.25V. (Example of calculation) C-CD pin output voltage [mVp-p] 150 [mVp-p] GHC = 20 log [dB] ∗6 Indicates the dissipation at 4.437525MHz in relation to 203.126kHz. From the output voltage at TH, C-CD, Y-YD and YD pins when a 150mVp-p, 203.126kHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins, and from the output voltage at TH, C-CD, Y-YD and YD pins when a 150mVp-p, 4.437525MHz sine wave is simultaneously fed to same, calculation is made according to the following formula. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is tested at VID + 0.25V, VIY – 0.25V, VIC – 0.25V and VIT – 0.25V, respectively. (Example of calculation) fT = 20 log TH pin output voltage (4.437525MHz) [mVp-p] TH pin output voltage (203.126kHz) [mVp-p] [dB] ∗7 The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 150mV 275mV 500mV 150mV 1H 64µs CCD3 pin input waveform (the input waveform of CCD1, CCD2-C and CCDY pins is the inverted waveform of the figure above.) ∗8 The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 5MHz. Vn [Vrms] The signal component is determined either by testing the output voltage (the same test system as that of noise level) at input of 350mVp-p, 203.126kHz, or by performing calculation from the values of GLT, GLC, GLY and GLD in accordance with the following formula. Vs [Vp-p] (Example of VS calculation) VS-T = 0.35 × 10 GLT 20 (VS-T: TH output voltage) (Example of S/N ratio calculation) SNT = 20 log VN-T (noise component) [Vrms] [dB] VS-T (signal component) [Vp-p] –8– CXL1502M ∗9 The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input block bias for VBIAS1 is tested at VID + 0.5V and VIC – 0.25V. Test value [mVp-p] ∗10 C-CD is calculated in accordance with the following formula from the C-CD pin output voltage when a 200mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and from the C-CD pin output voltage when a 200mVp-p, 4.441431MHz sine wave is simultaneously fed to same. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is set to VID + 0.3V, VIY – 0.3V, VIC – 0.3V and VIT – 0.3V, respectively. C-CD = 20 log C-CD pin output voltage (4.437525MHz) [dB] C-CD pin output voltage (4.441431MHz) ∗11 Y-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a 200mVp-p, 2.000011MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and from the Y-YD pin output voltage when a 200mVp-p, 1.992198MHz sine wave is simultaneously fed to same. The input block bias is set to the same conditions as in testing CCD. Y-CD = 20 log Y-YD pin output voltage (1.992198MHz) [dB] Y-YD pin output voltage (2.000011MHz) CLOCK fsc (4.433619MHz) sine wave 0.3Vp-p to 1.0Vp-p (0.4Vp-p Typ.) –9– – 10 – 1M 1 30 1µ 2 29 1M 1k 3 28 1M 1µ 100 4 27 0.1µ 3.3µ 5 26 1M 3.3µ 6 25 0.01µ 7 24 0.1µ 23 5V 0.01µ 8 CXL1502M fSC 0.4Vp-p sine wave 9 22 1µ 10 21 11 20 1µ 1.8k 1µ 13 18 3fsc 1.8k 2SC403 5V 14 17 0.01µ 15 16 THR output (forward phase signal) 1.2k C-CD output 1.2k Y-YD output 1.2k YD output (Reverse phase signal) 1.2k Signal output Transistor used : 2SA1175 9V When using pin 22 (3 fsc output) 22 1µ 12 19 3.3µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CCD1 input (Reverse phase signal) 1µ CCD2-C input (Reverse phase signal) 1µ CCDY input (Reverse phase signal) 1µ CCD3 input (forward phase signal) 1µ Composite video signal input Application Circuit CXL1502M CXL1502M Low frequency gain vs. Ambient temperature High frequency gain vs. Ambient temperature High frequency gain [dB] Low frequency gain [dB] –1 –2 –3 –4 –3 –4 –5 –6 –5 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] Frequency response vs. Ambient temperature Differential gain vs. Ambient temperature 8 0 Differential gain [%] Frequency response [dB] 10 –1 –2 6 4 2 –3 0 0 20 40 60 Ta – Ambient temperature [°C] Chroma comb depth min. gain vs. Ambient temperature Y comb depth min. gain vs. Ambient temperature –10 –10 Y comb depth min. gain [dB] Chroma comb depth min. gain [dB] 0 20 40 60 Ta – Ambient temperature [°C] –20 –30 –40 –50 –20 –30 –40 –50 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] – 11 – CXL1502M Low frequency gain vs. Supply voltage High frequency gain vs. Supply voltage High frequency gain [dB] Low frequency gain [dB] –1 –2 –3 –4 –3 –4 –5 –6 –5 4.75 5.00 VDD – Supply voltage [V] 5.25 4.75 Frequency response vs. Supply voltage 5.00 VDD – Supply voltage [V] 5.25 Differential gain vs. Supply voltage 8 0 Differential gain [dB] Frequency response [dB] 10 –1 –2 5.00 VDD – Supply voltage [V] 0 4.75 5.25 5.00 VDD – Supply voltage [V] 5.25 Y comb depth min. gain vs. Supply voltage –10 –10 Y comb depth min. gain [dB] Chroma comb depth min. gain [dB] Chroma comb depth min. gain vs. Supply voltage –20 –30 –40 –50 4.75 4 2 –3 4.75 6 –20 –30 –40 –50 5.00 VDD – Supply voltage [V] 5.25 4.75 – 12 – 5.00 VDD – Supply voltage [V] 5.25 CXL1502M Y comb response (Y-YD output) 0 –10 –10 Gain [dB] 0 –20 –20 –30 –30 –40 –40 4.4285M 4.4385M 4.4335M f – Frequency [Hz] 1.982M 1.992M f – Frequency [Hz] Frequency response (TH, YD output) 0 –2 Gain [dB] Gain [dB] Chroma comb response (C-CD output) –4 –6 –8 10k 100k f – Frequency [Hz] – 13 – 1M 2.002M CXL1502M Package Outline Unit: mm 30PIN SOP (PLASTIC) + 0.4 2.3 – 0.15 + 0.4 18.8 – 0.1 16 15 1 1.27 0.45 ± 0.1 0.24 + 0.2 0.1 – 0.05 0.5 ± 0.2 9.3 ± 0.3 10.3 ± 0.4 0.15 + 0.3 7.6 – 0.1 30 + 0.1 0.15 – 0.05 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE SOP-30P-L01 EIAJ CODE SOP030-P-0375 EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.7g JEDEC CODE – 14 –