CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Features ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C ■ Very high speed: 55 ns ■ Wide voltage range: 2.20 V–3.60 V ■ Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 ■ Ultra-low active power ❐ Typical active current: 1.5 mA @ f = 1 MHz ❐ Typical active current: 12 mA @ f = fmax ■ Ultra-low standby power ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Available in Pb-free and non Pb-free 48-ball fine ball grid array (FBGA), and Pb-free 44-pin thin small outline package (TSOPII) package Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. Functional Description For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. Logic Block Diagram 512K × 16 RAM Array SENSE AMPS ROW DECODER DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE OE CE2 CE1 BLE Power-down Circuit Cypress Semiconductor Corporation Document #: 38-05392 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 25, 2010 [+] Feedback CY62157DV30 MoBL® Contents Product Portfolio .............................................................. 3 Pin Configuration .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform................................................. 5 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Document #: 38-05392 Rev. *J Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY62157DV30 MoBL® Product Portfolio Power Dissipation Product VCC Range (V) Range Min Typ[1] Max 2.2 3.0 3.6 CY62157DV30LL Industrial Speed (ns) 55, 70 Operating ICC, (mA) f = 1MHz f = fmax Standby ISB2, (A) Typ[1] Max Typ[1] Max Typ[1] Max 1.5 3 12 15 2 8 Pin Configuration[2, 3, 4] 48-Ball FBGA Pinout 44-pin TSOP II Pinout Top View Top View 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C 1 A7 I/O3 Vcc D I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 VSS I/O11 VCC A17 NC H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating. 4. The 44-TSOPII package device has only one chip enable pin (CE). Document #: 38-05392 Rev. *J Page 3 of 15 [+] Feedback CY62157DV30 MoBL® Maximum Ratings Output current into outputs (LOW) .............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA Operating Range Ambient temperature with power applied .......................................... –55 °C to + 125 °C Supply voltage to ground potential .......................................... –0.3 V to VCC(max) + 0.3 V Device Range Ambient Temperature (TA) DC voltage applied to outputs in High-Z State[5, 6] ......................... –0.3 V to VCC(max) + 0.3 V CY62157DV30LL Industrial –40 °C to +85 °C VCC[7] 2.20 V to 3.60 V DC input voltage[5, 6] ....................... –0.3 V to VCC(max) + 0.3 V Electrical Characteristics Over the Operating Range Parameter Description -55 Test Conditions Min Typ[8] Max – Unit VOH Output HIGH voltage IOH = –0.1 mA VCC = 2.20 V 2.0 – IOH = –1.0 mA VCC = 2.70 V 2.4 – – V VOL Output LOW voltage IOL = 0.1 mA VCC = 2.20 V – – 0.4 V IOL = 2.1 mA VCC = 2.70 V VIH Input HIGH voltage VCC = 2.2 V to 2.7 V VIL VCC = 2.7 V to 3.6 V IIX Input leakage current GND < VI < VCC IOZ Output leakage current ICC V – – 0.4 V 1.8 – VCC + 0.3 V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 V Input LOW voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 V –0.3 – 0.8 V Ind’l –1 – +1 A GND < VO < VCC, Output disabled Ind’l –1 – +1 A VCC Operating supply current f = fMAX = 1/tRC VCC = VCCmax LL IOUT = 0 mA LL CMOS levels – 12 15 mA 1.5 3 mA ISB1 Automatic Power-down current — CMOS inputs Ind’l LL – 2 8 A ISB2 Automatic Power-down current -CMOS inputs CE1 > VCC 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V f = fMAX (Address and Data Only), f = 0 (OE, WE), VCC = 3.60V CE1 > VCC– 0.2 V or CE2 < 0.2 V, (BHE and BLE) > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V Ind’l LL – 2 8 A f = 1 MHz Capacitance Parameter[9, 10] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 5. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max)= VCC+0.75 V for pulse duration less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 9. Tested initially and after any design or process changes that may affect these parameters. 10. The input capacitance on the CE2 pin of the FBGA package and on the BHE pin of the 44TSOPII package is 15 pF. Document #: 38-05392 Rev. *J Page 4 of 15 [+] Feedback CY62157DV30 MoBL® Thermal Resistance Parameter[11] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions FBGA TSOP II Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 39.3 35.62 C / W 9.69 9.13 C / W AC Test Loads and Waveforms VCC OUTPUT R1 30 pF / 50 pF VCC GND R2 Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Parameters 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 2.50 V 3.0 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min Typ[12] Max Unit 1.5 – – V – – 4 A VDR VCC for data retention ICCDR Data retention current tCDR[11] Chip deselect to data retention time 0 – – ns tR[13] Operation recovery time 55 – – ns VCC= 1.5 V CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Ind’l Data Retention Waveform[14] VCC VCC, min. tCDR DATA RETENTION MODE VDR > 1.5 V VCC, min. tR CE1 or BHE.BLE or CE2 Notes 11. Tested initially and after any design or process changes that may affect these parameters 12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05392 Rev. *J Page 5 of 15 [+] Feedback CY62157DV30 MoBL® Switching Characteristics Over the Operating Range Parameter[15] Description 55 ns Unit Min Max 55 – ns Read Cycle tRC Read cycle time tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to LOW Z 5 – ns tHZOE OE HIGH to High Z[16, 17] – 20 ns tLZCE CE1 LOW and CE2 HIGH to Low Z[16] 10 – ns tHZCE CE1 HIGH and CE2 LOW to High Z – 20 ns tPU CE1 LOW and CE2 HIGH to Power-up 0 – ns tPD CE1 HIGH and CE2 LOW to Power-down – 55 ns tDBE BLE/BHE LOW to data valid – 55 ns tLZBE BLE/BHE LOW to Low Z 10 – ns tHZBE BLE/BHE HIGH to HIGH Z – 20 ns [16] [16, 17] [16] [16, 17] Write Cycle[18] tWC Write cycle time 55 – ns tSCE CE1 LOW and CE2 HIGH to write end 40 – ns tAW Address set-up to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 40 – ns tBW BLE/BHE LOW to write end 40 – ns tSD Data set-up to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High-Z – 20 ns tLZWE WE HIGH to Low-Z 10 – ns [16, 17] [16] Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 18. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05392 Rev. *J Page 6 of 15 [+] Feedback CY62157DV30 MoBL® Switching Waveforms Figure 1. Read Cycle 1 (Address Transition Controlled)[19, 20] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Figure 2. Read Cycle 2 (OE Controlled)[20, 21] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE HIGH IMPEDANCE DATA VALID tLZCE SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 19. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05392 Rev. *J Page 7 of 15 [+] Feedback CY62157DV30 MoBL® Switching Waveforms (continued) Figure 3. Write Cycle 1 (WE Controlled)[22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See note 25 tHZOE Figure 4. Write Cycle 2 (CE1 or CE2 Controlled)[22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See note 25 tHZOE Notes 22. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 23. Data I/O is high-impedance if OE = VIH. 24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05392 Rev. *J Page 8 of 15 [+] Feedback CY62157DV30 MoBL® Switching Waveforms (continued) Figure 5. Write Cycle 3 (WE Controlled, OE LOW)[26] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tHA tAW tPWE tSA WE tSD DATA I/O See note 27 tHD VALID DATA tLZWE tHZWE Figure 6. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[26] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O See note 27 tHD VALID DATA Notes 26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state 27. During this period, the I/Os are in output state and input signals should not be applied Document #: 38-05392 Rev. *J Page 9 of 15 [+] Feedback CY62157DV30 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X High Z Deselect/Power-down Standby (ISB) X X X X H H High Z Deselect/Power-down Standby (ISB) L H H L L L Data out (I/O0–I/O15) Read (upper byte and Lower byte) Active (ICC) L H H L H L Data out (I/O0–I/O7); High Z (I/O8–I/O15) Read (lower byte only) Active (ICC) L H H L L H High Z (I/O0–I/O7); Data out (I/O8–I/O15) Read (upper byte only) Active (ICC) L H H H L H High Z Output disabled Active (ICC) L H H H H L High Z Output disabled Active (ICC) L H H H L L High Z Output disabled Active (ICC) L H L X L L Data in (I/O0–I/O15) Write (upper byte and Lower byte) Active (ICC) L H L X H L Data in (I/O0–I/O7); High Z (I/O8–I/O15) Write (lower byte only) Active (ICC) L H L X L H High Z (I/O0–I/O7); Data in (I/O8–I/O15) Write (upper byte only) Active (ICC) Document #: 38-05392 Rev. *J Inputs/Outputs High Z Mode Deselect/Power-down Power Standby (ISB) Page 10 of 15 [+] Feedback CY62157DV30 MoBL® Ordering Information Speed (ns) 55 Ordering Code CY62157DV30LL-55BVI CY62157DV30LL-55BVXI CY62157DV30LL-55ZSXI Package Diagram 51-85150 51-85087 Package Type 48-ball (6 x 8 x 1 mm) FBGA 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) 44-pin TSOP II (Pb-free) Operating Range Industrial Ordering Code Definition CY 621 5 7D V30 LL 55 XXX X Tem perature Grade I = Industrial Package Type : ZSX : TSOP II (Pb-free) BVX : VFBGA (Pb-free) BV : VFBGA Speed Grade Low Power Voltage = 3.0 Bus W idth = X16 D = 130nm Technology Density = 8M bit M oBL SRAM Fam ily Com pany ID: CY = Cypress Document #: 38-05392 Rev. *J Page 11 of 15 [+] Feedback CY62157DV30 MoBL® Package Diagram Figure 7. 48-Pin VFBGA (51-85150) 51-85150 *F Figure 8. 44-pin TSOP II (51-85087) 51-85087 *C Document #: 38-05392 Rev. *J Page 12 of 15 [+] Feedback CY62157DV30 MoBL® Acronyms Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor Symbol I/O input/output SRAM Acronym Unit of Measure °C degrees Celsius static random access memory A microamperes VFBGA very fine ball grid array mA milliampere TSOP thin small outline package MHz megahertz Document #: 38-05392 Rev. *J ns nanoseconds pF picofarads V volts ohms W watts Page 13 of 15 [+] Feedback CY62157DV30 MoBL® Document History Page Document Title: CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM Document Number: 38-05392 REV. ECN NO. Issue Date ** 126316 05/22/03 *A 131013 11/19/03 Orig. of Change HRT Description of Change New Data Sheet CBD/LDZ Change from Advance to Preliminary *B 133115 01/24/04 CBD Minor Change: Change MPN and upload. *C 211601 See ECN AJU Change from Preliminary to Final Changed Marketing part number from CY62157DV to CY62157DV30 in the title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section *D 236628 See ECN SYT/AJU *E 257349 See ECN PCI Added test condition for 45 ns part (footnote #13 on page 4) *F 372074 See ECN SYT Added Pb-Free Automotive Part in the Ordering Information Removed ‘Preliminary’ tag from Automotive Information *G 433838 See ECN ZSD Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Updated the thermal resistance table Updated the ordering information table and changed the package name column to package diagram *H 488954 See ECN VKN Added Automotive-A product Updated ordering Information table *I 2897932 03/23/2010 VKN Removed 45ns speed bin Removed Auto-A/Auto-E information Removed 48-Pin TSOP I information Updated ordering Information table Updated package diagrams. *J 3068300 10/25/2010 RAME Document #: 38-05392 Rev. *J Added 45-ns and 70-ns Speed Bins Added Automotive product information Removed CY62157DV30LL-70BVXI part related info Updated ISB1/ISB2/ICCDR test conditions to reflect byte power down feature Updated datasheet as per new template Added Acronyms and Units of Measure table Added Ordering Code Definition Updated Package Diagram to 51-85150 *F Converted all tablenotes into footnotes Page 14 of 15 [+] Feedback CY62157DV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks Optical & Image Sensing PSoC Touch Sensing cypress.com/go/USB Wireless/RF cypress.com/go/wireless cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory USB Controllers cypress.com/go/memory PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch © Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05392 Rev. *J Revised October 25, 2010 Page 15 of 15 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback