ETC DM8108

DM8108
8 port 10/100M Fast Ethernet Switching Controller
General Description
The DM8108 is an 8 port 10/100Mbit/s nonblocking
Ethernet switch with on-chip address-lookup engine. The
DM8108 provides a low-cost, high-performance switch
solution with PHYs and single SGRAM.
The DM8108 provides eight 10/100Mbit/s Fast Ethernet
interface. In half-duplex mode, all ports support backpressure capability to reduce the risk of data loss for a long
burst of activity. In the full-duplex mode of operation, the
device uses IEEE std. 802.3 frame-based pause protocol
for flow control. With full-duplex capability, port 0 – 7 support
1.6Gbit/s aggregate bandwidth connections. The DM8108
also supports port trunking/load balancing on the
10/100Mbit ports. This can be used to group ports on interswitch links to increase the effective bandwidth between the
systems.
The internal address-lookup engine supports up to 16.25K
unicast and unlimited multicast and broadcast addresses.
This engine performs destination and source addresses
book-keeping and comparison which also forwards
unknown destination address packets to all ports.
The DM8108 is fabricated with a .35um technology.
Working at 3.3V, the inputs are 5V tolerant and the outputs
are capable of directly driving at TTL levels.
Block Diagram
Control &
Status
Address
Learning
Expansion
MEM
Controller
Switching
Engine
Preliminary
Version: DM8108-DS-P02
November 25, 1999
LED Control
Unit
1
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Features
T
Low cost Fast Ethernet Switching Controller.
O Provide packet switching functions between
eight
10/100Mbps, auto-negotiated on-chip Fast
Ethernet ports and a proprietary Full-duplex
Expansion port.
O Cascade max. 8 DM8108s without extra glue
logic for 64-port configuration.
T Incorporates three 802.3 compliant 10/100Mbps
Media Access Controllers
O Direct interface to MII (Media Independent
Interface)
O Half/Full Duplex Support for individual port (upto
200Mbps/port)
O IEEE 802.3 100Base-TX, T4.FX compatible
T Auto-negotiation supported through Serial MII
interface
T High-performance Distributed Switching Engine
O Performs packet forwarding and filtering at full
wire-speed
O 148,800 packets/sec. on each Ethernet port
T Direct support for packet buffering
O Glue-less interface with 1 or 2 Mbytes of SDRAM
(SGRAM)
O 32 bit memory bus configuration
O 66 Mhz – 90Mhz memory bus speed
O Up-to 1.1K buffers, 1536-byte each, allocated to
receive ports
T Support Store and Forward switching approach
2
T
O Low last-bit to first-bit out delay
O Allow mixed speed Ethernet packet switching
O Allow conversion between different protocols
Flow control
O Support partitioning function
O Support back-pressure while lack of internal
resources
O Support 802.3x PAUSE function in full duplex
mode
O Support up to 4-port trunking for 800Mbps
bandwidth
Advanced Address Learning and Searching
O Self learning mechanism
O Cache 128 address entries internally
O Record up-to 16K Uni-cast MAC addresses and
unlimited Multicast and Broadcast addresses
O Automatic aging scheme
O Broadcast filtering rate control
T Expansion Bus
O Up-to 8 SW devices can be cascaded via
expansion bus without extra logic
O Full duplex mode transfer
O Less Bus overhead
O Automatic flow control
T Complete status report to a simple LED interface
T Suitable for low cost Switch market to replace
Hub
T 0.35 m process, 3.3V with 5V tolerant I/O
T 208-pin PQFP package
T
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Application Example:
Low cost 8 to 64 ports 10/100 Mbps auto-sensing switch
MEM
MEM
DM8108
MEM
DM8108
DM8108
PHY
PHY
PHY
8
8
8
10/100 BaseTx
Cascaded up-to 64 10/100Mbps Fast Ethernet ports
Application Example: Low cost auto-sensing switching hub implementation
MEM
MII
MII
DM8108
PHY with
repeater
#1
PHY with
repeater
PHY with
repeater
Hub Module
PHY with
repeater
#4 Hub Module
10/100 BaseTx
Preliminary
Version: DM8108-DS-P02
November 25, 1999
3
DM8108
8 port 10/100M Fast Ethernet Switching Controller
High density mixed switching and hub ports with 8 collision domains
4
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
RXD8[3]
RXD8[2]
RXD8[1]
RXD8[0]
RXCLK8
VSS
TXD8[3]
TXD8[2]
TXD8[1]
TXD8[0]
VDD
TXCLK8
VSS
DMA0
DMA1
DMA2
DMA3
DMA4
VSS
DMA5
DMA6
DMA7
DMA8
VDD
DMA9
SBA
SDDQM#
VSS
DWE#
SDCS#
CAS#
RAS#
VSS
SCLK
VSS
DMD0
DMD1
DMD2
DMD3
DMD4
DMD5
DMD6
DMD7
VSS
DMD8
DMD9
DMD10
DMD11
DMD12
DMD13
DMD14
DMD15
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDD
DMD16
DMD17
DMD18
DMD19
DMD20
DMD21
DMD22
DMD23
VSS
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
VSS
TXD7[3]
TXD7[2]
TXD7[1]
TXD7[0]
TXEN7
TXCLK7
RXD7[3]
RXD7[2]
RXD7[1]
RXD7[0]
RXCLK7
CRS7
COL7
RXDV7
RXER7
VDD
TXD6[3]
TXD6[2]
TXD6[1]
TXD6[0]
TXEN6
TXCLK6
RXD6[3]
RXD6[2]
RXD6[1]
RXD6[0]
RXCLK6
CRS6
COL6
RXDV6
RXER6
VSS
TXD5[3]
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
DM8108
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
TXD2[2]
TXD2[3]
VDD
RXER3
RXDV3
COL3
CRS3
RXCLK3
RXD3[0]
RXD3[1]
RXD3[2]
RXD3[3]
TXCLK3
TXEN3
TXD3[0]
TXD3[1]
TXD3[2]
TXD3[3]
VSS
MIICLK
MIID
VSS
RXER4
RXDV4
COL4
CRS4
RXCLK4
RXD4[0]
RXD4[1]
RXD4[2]
RXD4[3]
TXCLK4
TXEN4
TXD4[0]
TXD4[1]
TXD4[2]
TXD4[3]
VDD
RXER5
RXDV5
COL5
CRS5
RXCLK5
RXD5[0]
RXD5[1]
RXD5[2]
RXD5[3]
TXCLK5
TXEN5
TXD5[0]
TXD5[1]
TXD5[2]
VSS
LEDCLK
LEDSTB
LEDD
RST#
TESTEN
VSS
RXER0
RXDV0
COL0
CRS0
RXCLK0
RXD0[0]
RXD0[1]
RXD0[2]
RXD0[3]
TXCLK0
TXEN0
TXD0[0]
TXD0[1]
TXD0[2]
TXD0[3]
VDD
RXER1
RXDV1
COL1
CRS1
RXCLK1
RXD1[0]
RXD1[1]
RXD1[2]
RXD1[3]
TXCLK1
TXEN1
TXD1[0]
TXD1[1]
TXD1[2]
TXD1[3]
VSS
RXER2
RXDV2
COL2
CRS2
RXCLK2
RXD2[0]
RXD2[1]
RXD2[2]
RXD2[3]
TXCLK2
TXEN2
TXD2[0]
TXD2[1]
Preliminary
Version: DM8108-DS-P02
November 25, 1999
5
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Pin Description
Pin Assignment
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
6
NAME
VSS
LEDCLK
LEDSTB
LEDD
RST*
TESTEN*
VSS
RXER0
RXDV0
COL0
CRS0
RXCLK0
RXD0(0)
RXD0(1)
RXD0(2)
RXD0(3)
TXCLK0
TXEN0
TXD0(0)
TXD0(1)
TXD0(2)
TXD0(3)
VDD
RXER1
RXDV1
COL1
CRS1
RXCLK1
RXD1(0)
RXD1(1)
RXD1(2)
RXD1(3)
TXCLK1
TXEN1
TXD1(0)
TXD1(1)
TXD1(2)
TXD1(3)
VSS
RXER2
RXDV2
COL2
#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NAME
CRS2
RXCLK2
RXD2(0)
RXD2(1)
RXD2(2)
RXD2(3)
TXCLK2
TXEN2
TXD2(0)
TXD2(1)
TXD2(2)
TXD2(3)
VDD
RXER3
RXDV3
COL3
CRS3
RXCLK3
RXD3(0)
RXD3(1)
RXD3(2)
RXD3(3)
TXCLK3
TXEN3
TXD3(0)
TXD3(1)
TXD3(2)
TXD3(3)
VSS
MDCLK
MDIO
VSS
RXER4
RXDV4
COL4
CRS4
RXCLK4
RXD4(0)
RXD4(1)
RXD4(2)
RXD4(3)
TXCLK1
#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NAME
TXEN4
TXD4(0)
TXD4(1)
TXD4(2)
TXD4(3)
VDD
RXER5
RXDV5
COL5
CRS5
RXCLK5
RXD5(0)
RXD5(1)
RXD5(2)
RXD5(3)
TXCLK5
TXEN5
TXD5(0)
TXD5(1)
TXD5(2)
TXD5(3)
VSS
RXER6
RXDV6
COL6
CRS6
RXCLK6
RXD6(0)
RXD6(1)
RXD6(2)
RXD6(3)
TXCLK6
TXEN6
TXD6(0)
TXD6(1)
TXD6(2)
TXD6(3)
VDD
RXER7
RXDV7
COL7
CRS7
#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
RXCLK7
RXD7(0)
RXD7(1)
RXD7(2)
RXD7(3)
TXCLK7
TXEN7
TXD7(0)
TXD7(1)
TXD7(2)
TXD7(3)
VSS
MD(31)
MD(30)
MD(29)
MD(28)
MD(27)
MD(26)
MD(25)
MD(24)
VSS
MD(23)
MD(22)
MD(21)
MD(20)
MD(19)
MD(18)
MD(17)
MD(16)
VDD
MD(15)
MD(14)
MD(13)
MD(12)
MD(11)
MD(10)
MD(9)
MD(8)
VSS
MD(7)
MD(6)
MD(5)
#
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NAME
MD(4)
MD(3)
MD(2)
MD(1)
MD(0)
VSS
SCLK
VSS
SRAS*
SDCAS*
SDCS*
SDWE*
VSS
SDQM*
MA(10) – SBA
MA(9)
VDD
MA(8)
MA(7)
MA(6)
MA(5)
VSS
MA(4)
MA(3)
MA(2)
MA(1)
MA(0)
VSS
TXENCLK
VDD
TXD8(0)
TXD8(1)
TXD8(2)
TXD8(3)
VSS
RXDVCLK
RXD8(0)
RXD8(1)
RXD8(2)
RXD8(3)
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Pin Description (continued)
Please refer to the “Strap pin default value after reset section” for the detail description of the
Strap pins.
DRAM Interface
Pin No.
139 – 146,
148 – 155,
157 – 164,
166 – 173
183 – 184,
186 – 189,
191 – 195
Pin Name
MD(31:0)
I/O
I/O
Description
MA(10:0)
I/O
177
178
180
182
179
SRAS*
SDCAS*
SDWE*
SDQM
SDCS*
O
O
O
O
O
Pin Name
RXDVCLK
RXD8[3:0]
TXENCLK
TXD8[3:0]
I/O
I/O
I/O
I/O
I/O
Description
Expansion port’s receiving data valid
Expansion port’s receive data input
Expansion port’s transmit enable output
Expansion port’s transmit data output
Strap pins during reset:
TXD8[2:0] = device # setting
TXD8[3]
= dram timing
Pin No.
2
4
Pin Name
LEDCLK
LEDD
I/O
O
O
3
LDSTB
I/O
Description
LED data clock
LED data: active low. Data stream that contains LED indicators per
port. The data is shifted out and should be qualified by LDSTB* to
clock into external registers to drive LEDs.
Strap pin during reset:
0: expansion port with fast speed
1: expansion port with lower apees
LED data strobe: active high. Used to strobe the LD into an external
register
Strap pin during reset:
0: force link
1: link detection through serial MII
DRAM data lines 31 – 0
DRAM address lines 10-0; strap pins during reset
MA9: 0= enable limit4, 1=disbale limit 4
MA8: DRAM size selection; 0= 1M, 1=2M
MA7-0: Auto-negotiation enable for port 7-0; 0= enabled
Row address strobe for SDRAM
Column address strobe for SDRAM
Write cycle indication, internally pulled up
Data Mask for SDRAM
Chip select for SDRAM
Expansion Bus
Pin No.
204
208 – 205
197
202 – 199
LED Interface
Preliminary
Version: DM8108-DS-P02
November 25, 1999
7
DM8108
8 port 10/100M Fast Ethernet Switching Controller
MII Interface
8
Pin No.
133,117,101,
85,66,50,34,18
Pin Name
TXEN(7:0)
I/O
B
132,116,100,84,
65,49,33,17
TXCLK(7:0)
I
22 – 19
TXD0(3:0)
B
38 – 36
TXD1(3:0)
B
54 – 51
TXD2(3:0)
B
70 – 67
TXD3(3:0)
B
89 – 86
TXD4(3:0)
O
105 –102
TXD5(3:0)
O
121 –118
137 –134
16 – 13
32 – 29
48 – 45
64 – 61
83 – 80
TXD6(3:0)
TXD7(3:0)
RXD0(3:0)
RXD1(3:0)
RXD2(3:0)
RXD3(3:0)
RXD4(3:0)
O
O
I
I
I
I
I
Description
Transmit Enable: Active high, synchronous to TXCLK; indicate that
the transmission data is valid.
Strap function during reset-TXEN(7:0): 0 = port 7-0 full duplex
Transmit Clock: Provides the timing reference for the transfer of
TXEN, TXD signals. It is 25MHz for 100Mbps and 2.5MHz for
10Mbps.
Transmit data for port 0; synchronous to TXCLK0.
Strap function during reset-TDX0[0]: 0=80Mhz, 1=66Mhz CLOCK operation
TXD0[1]: 0=enable partition mode, 1=disable partition mode
TXD0[2]: 0=enable expansion port, 1=disable expansion port
TXD0[3]: 0=init only, 1= enable BIST
Transmit data for port 1; synchronous to TXCLK1.
Strap function during reset -TXD1[2:0]: test mode
TXD1[3]: 0=enable CRC, 1=disbale CRC
Transmit data for port 2; synchronous to TXCLK2.
Strap function during reset -TXD2[2:0]: device # setting
TXD2[3]: DRAM timing 0=fast, 1=slow
Transmit data for port 3; synchronous to TXCLK3.
Strap function during reset -TXD3[0]: 0=max. packet size 1536, 1=max. packet size 1518(default)
TXD3[1]: 0=enable back_pressure, 1= disable (default)
TXD3[3:2]: age strap pins
00= 64 sec. 01= 128 sec.
10= 256 sec. 11= disbale
Transmit data for port 4; synchronous to TXCLK4.
Strap function during reset –
TXD4[0]: 0= port 0 trunking enable 1= port 0 no trunking (default)
TXD4[1]: 0= port 1 trunking enable 1= port 1 no trunking (default)
TXD4[2]: 0= port 2 trunking enable 1= port 2 no trunking (default)
TXD4[3]: 0= port 3 trunking enable 1= port 3 no trunking (default)
Transmit data for port 5; synchronous to TXCLK5.
Strap function during reset –
TXD5[1:0]: broadcast filtering rate selection
00 = 8k/sec 01 = 16k/sec
10 = 64k/sec 11= disable
Transmit data for port 6; synchronous to TXCLK6.
Transmit data for port 7; synchronous to TXCLK7.
Receive data for port 0; synchronous to RXCLK0.
Receive data for port 1; synchronous to RXCLK1.
Receive data for port 2; synchronous to RXCLK2.
Receive data for port 3; synchronous to RXCLK3.
Receive data for port 4; synchronous to RXCLK4.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
99 – 96
115 - 112
137 - 128
127,111,95,79,
60,44,28,12
124,108,92,76,
57,41,25,9
123,107,91,75,
56,40,24,8
126,110,94,78,
59,43,27,11
125,109,93,77,
58,42,26,10
RXD5(3:0)
RXD6(3:0)
RXD7(3:0)
RXCLK(7:0)
I
I
I
I
RXDV(7:0)
I
Receive data for port 5; synchronous to RXCLK5.
Receive data for port 6; synchronous to RXCLK6.
Receive data for port 7; synchronous to RXCLK7.
Receive clock for port 7 – 0; synchronous to RXD, RXDV,RXER; has
same clock rate as TXCLK.
Receive data valid indication for port 7 – 0.
RXER(7:0)
I
Receive data error indication for port 7 – 0.
CRS(7:0)
I
COL(7:0)
I
72
MDCLK
I/O
73
MDIO
I/O
Carrier sense; active high. Indicates that either the transmit or
receive medium is not Idle. CRS is not synchronous to any clock.
Collision Detect; active high. Indicates a collision has been detected
on the wire.
This input is ignored during full duplex operation and in the half duplex
mode while TXEN of the same port is low.
Serial MII management interface clock signal: 1MHz clock for MDIO
data reference. Connected to all PHY ports; It is an input pin if the
device # is not 0 in SDRAM mode; else, it is an output pin.
Serial MII management interface data; this bi-direction line is used to
transfer control Information and status between the PHY and the
DM8108. It conforms to the IEEE-802.3 specifications.
This signal may be connected to the PHY devices of all ports.
Pulled down if not used.
Miscellaneous Interface pins
Pin No.
175
5
6
Pin Name
SCLK
RST*
TESTEN*
I/O
I
I
I
Description
Memory clock: used by the DRAM state machine.
Reset signal for the chip.
Test pin to enable test functions
Pin Name
VCC
I/O
Power
Description
Connected to 3.3V Power plane
GND
Ground
Connected to Ground plane
Power pins
Pin No.
23,55,90,122,
156,185,198
1,7,39,71,74,
106,138,147,
165,174,176,
181,190,196,
203
Preliminary
Version: DM8108-DS-P02
November 25, 1999
9
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Functional Description
Fast Ethernet Ports Functional Overview
Fast Ethernet Ports
The DM8108 is a high-performance, low-cost Fast
Ethernet Switching Controller which provides packet
switching between eight on-chip, 10/100 Mbps ports
and one optional expansion port. It is suitable for the
auto-sensing 10/100Mbps switch application.
The DM8108 integrates eight Fast Ethernet ports, working
at 10/100Mbps (half-duplex) or 20/200Mbps (full-duplex)
with off-the-shelf PHY chips. The interface is glue-less
through Media Independent Interfaces (MII). The autonegotiation function determines the port’s operating mode.
With auto-negotiation disabled, the ports can be forced to
operate at a certain mode, if so desired. Each port includes
the Media Access Control function (MAC), LED signals for
Link, Collision, Receive/Transmit, Half/Full duplex and
Receive Buffer Full indications.
Switching Architecture
The switching architecture is based on the shared memory
and handshaking signals to switch packets between on-chip
ports hard-wired.
For an incoming packet, the receiving port’s MAC stores it in
the receiving buffers if it is a good packet. At the same
time, the switching engine determines which port the packet
will forward to and update the address table which will be
used for future packet forwarding reference.
Address Recognition
The DM8108 in a system can recognize up to 16K Uni-cast
MAC addresses and unlimited Multicast/Broadcast MAC
addresses. An intelligent address recognition mechanism
enables filtering and forwarding packets at full Ethernet wire
speed. The DM8108 provides an address self-learning
mechanism. As each DM8108 learns new address, it
updates the address table in the storage.
Fig.1: Typical 10/100 Mbps auto-sensing switching hub application
MEM
MEM
optional
DM8108
DM8108
10/100 Mbps PHY
10/100 Mbps PHY
Switch Ports
10
Switch Ports
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Packet Routing
As any port in the DM8108 receives a packet, the DM8108
will put the received data in the receiving buffer and start the
address recognition at same time.
1.
2.
If the destination address is pointed to a local port
other than receiving port, the DM8108 will update the
Transmit Descriptor of the target port with the buffer
location and byte count information and wait for
transmission.
If the destination address is pointed to a port located in
other devices, the DM8108 will update the
Transmit Descriptor of the expansion port with the
receiving buffer location and byte count information
and wait for transmission.
3.
4.
5.
6.
f the destination address is not found in the Address
Table, the DM8108 will update all the Transmit
Descriptors, except the one of the receiving port, for
transmission.
For the Multicast/Broadcast addresses, the DM8108
simply updates all the Transmit Descriptors, except
the one of the receiving port or the ports that are
disabled, for Transmission.
For bad packet, the DM8108 simply discards it.
If the receiving buffer or the Transmit Descriptor for a
particular port is full, the packet will be lost.
Network Management Features
Preliminary
Version: DM8108-DS-P02
November 25, 1999
The DM8108 is targeted for the non-managed Ethernet
Switching application. No management functions provided.
DRAM Interface
The DM8108 interfaces to 1M or 2M bytes of SGRAM or
SDRAM. The DRAM is used to store incoming packets as
well as he address table and Transmit Descriptors. The
DRAM can operate at up to 90MHz. One 256kx32 or
512kx16 SGRAM are required respectively for 1M or 2M
shared memory size.
Expansion Bus
The expansion bus contains Receive Port and Transmit
Port. Each port is 4-bit wide.
The Receive Port takes the incoming packet into a FIFO
that has to be distributed to the Receiving Buffer
immediately. At the same time, the DM8108 will check the
destination and source addresses to determine the target
port and update the Address Table if necessary.
The Transmit Port is dedicated for transferring packets out
to other switching members if the Transmit Descriptor for
this port saying the transmission is pending.
Total of 8-DM8108 can be cascaded for a 64-port switching
system.
11
I
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Operation Overview
The SW Architecture Family of switching devices has
been defined as low cost, high performance and
scalable architecture for a small switching system of
packetized data. Various devices will be developed.
The OEMs will be able to design robust switching
configurations based on the SW architecture.
The DM8108 automatically learns the port number of
attached network devices by examining the Source
MAC address of all incoming packets. If the Source
Address is not found in the Address Table, the device
adds it to the table (with source port and device
information). The Address Table is managed by
DM8108 individually.
The SW Architecture Family uses a “store-andforward’ switching approach. This approach has the
following advantages:
Address Learning
•
The DM8108 can learn up to 16K unique MAC addresses.
Addresses are stored in the Address Table located in the
DRAM which will be initialized after RESET.
•
•
•
Store-and-forward switches allow switching
between differing speed media (e.g. 10Mbps and
100Mbps).
Store-and-forward switches improve overall
network performance by acting as a ‘network
cache’,
effectively buffering packets during
times of heavy congestion.
Store-and-forward switches prevent the
erroneous packets from forwarding by analyzing
the frame check sequence (FCS) before
forwarding to the destination port.
Store-and-forward switches prevent illegal
frames (runt or oversized) from being forwarded
and
thereby reduce the congestion caused
by bad packets.
The basic operation of DM8108 is very simple. The
DM8108 receives the incoming packets from the
Ethernet ports, searches in the Address Table for the
destination MAC address, and forwards the packet to
the appropriate port, which could be either local (one
of the DM8108’s port) or in a different DM8108
device that resides on the expansion bus. If the
destination address is not found, the packet will be
treated as a multicast packet and sent to every port
(other than the source port) and other devices on the
expansion bus.
12
Packet Buffering
Incoming packets are buffered in the DRAM array. These
buffers provide elastic storage for transferring data between
low-speed and high speed segments. The packet buffers
are managed automatically by the DM8108.
Packet Forwarding Protocol
The DM8108 updates the Transmit Descriptor of the target
port, which is learned from Address Table, with the received
packet buffer location and packet length. The MAC of
target port will fetch the packet for transmission once the
memory bus is available.
Expansion Bus
The Expansion Bus is defined as a special case of a normal
Fast Ethernet MII port except running at much higher data
rate.
The designer can link several DM8108s within a switching
box or can link several switching boxes.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Theory of Operation
Block Diagram
Expansion
MAC
MAC
Switching
Engine
DRAM
Controller
Control
Registers
Status
Registers
MII
Management
Preliminary
Version: DM8108-DS-P02
November 25, 1999
LED Control
Unit
13
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Media Access Control
The MAC Engine incorporates the essential protocol
requirement for an Ethernet IEEE-802.3 compliant
node, and provides the interface between the FIFO
subsystem and the MII. The MAC has two primary
attributes:
If the frame terminates or suffers a collision before
64-bytes (after SFD) have been received, the MAC
will automatically delete the frame from FIFO.
T
Addressing (source and destination address
handling)
Transmit and receive message data
encapsulation
The MAC intercepts the source and destination
address from the incoming frame and send them
to switching engine for the following purposes:
The MAC will discard the illegally short (less than 64
bytes of frame data) or oversized (greater than 1536
bytes) messages to be transmitted or received.
.
.
.
T
Framing (frame boundary delimitation, frame
synchronization)
The MAC engine will automatically handle the
construction of the transmit frame. Once the
transmit FIFO has been filled to the predetermined
threshold and access of the channel is permitted, the
MAC will commence the following for transmission:
The receiving section of the MAC will detect an
incoming preamble sequence when the RXDV signal
is activated by the external PHY. The MAC will
discard the preamble and begin searching for the SFD.
Once the SFD is detected, all the subsequent nibbles
are treated as part of the frame. The MAC will discard
the message if it is shorter than 64-bytes or longer
than 1518 (1536) bytes. The received frame will be
sent to Receiving Buffer for switching.
Preamble
1010…1010
7
Bytes
14
SFD
10101011
1
Bytes
Destination
Address
6
Bytes
T
To update the address table
To learn the switching target
To detect the DM8108 predefined address for
the device control functions.
Error detection (physical medium transmission
errors)
During transmission, if the switching engine
failed to keep the transmit FIFO filled sufficiently,
cause an underflow, the MAC engine will
guarantee the message is either sent as runt
packet (which will be detected by the receiving
station) or as an invalid FCS (which will cause
the receiver to reject the packet).
During reception, the FCS is generated on every
nibble (including the dribbling bits) coming from
the cable, although the internally saved FCS
value is only updated on the eighth bit (on each
byte boundary). The MAC engine will ignore up
to 7 additional bits at the end of a message
(dribbling bits), that can occur under normal
network operating conditions.
Source
Address
6
Bytes
Length
2
Bytes
Data
FCS
40 – 1500
Bytes
4
Bytes
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Media access management
IEEE 802.3 protocols define a media access
mechanism that permits all stations to access the
channel with equality. Any node can attempt to
connect for the channel by waiting a predefined period
of time (Inter Packet Gap) after the last activity before
transmitting on the media. If two nodes
simultaneously contend for the channel, their signals
will interact causing loss of data, defined as collision.
It is the responsibility of the MAC to attempt to avoid
and recover from the end-to-end transmission to the
receiving station.
T
Medium allocation (collision avoidance, except
in full-duplex operation)
The MAC will monitor the medium for traffic by
watching for carrier activity. When the carrier is
detected, the media is considered as busy, and the
MAC should defer to the existing message.
The MAC implements the IEEE-802.3 defined two
part deferral algorithm, with Inter-Frame-SpacngPart1 (IFS1) time for 64-bit time (6.4 us for10-BASE
and 640 ns for 100-BASE). The Inter-FrameSpacing-Part2 (IFS2) interval is, therefore, 32-bit time.
The Inter Packet Gap (IPG) timer will start timing the
96-bit time Inter-Frame-Spacing after the receiving
carrier is de-asserted. During the IFS1, the MAC will
defer any pending transmit frame and respond to the
receive message. The IPG counter will be cleared to
0 continuously until the carrier de-asserts, at which
point the IPG will resume the 96-bit time count again.
Once the IFS1 period has completed and the IFS2
has commenced, the MAC will not defer to the
receiving frame if a transmit frame pending. The MAC
will not attempt to receive the receiving frame, since it
will start transmit and generate a collision at 96-bit
Preliminary
Version: DM8108-DS-P02
November 25, 1999
time. The MAC will complete the preamble (64-bit)
and JAM (32-bit) sequence before ceasing
transmission and invoking the random back-off
algorithm.
T
Contention resolution (collision handling,
except in full-duplex mode)
If a collision is detected through COL pin before the
complete preamble/SFD sequence has been
transmitted, the MAC engine will complete the
preamble/SFD before appending the JAM sequence.
If a collision is detected after the preamble/SFD has
been completed, but prior to 512 bits being
transmitted, the MAC will abort the transmission and
append the JAM sequence immediately. The JAM
sequences is a 32-bit all “34” pattern.
The MAC will attempt to transmit a frame a total of 16
times (15-retries) due to normal collisions (those
within the slot time). Detection of collision will cause
the transmission to be re-scheduled to a time
determined by the random back-off algorithm. If 16
attempts experienced collisions, the transmitting
message will be flushed from FIFO.
If a collision is detected after 512-bit times have been
transmitted, the collision is termed “Late” collision.
The MAC will abort the transmission, append the JAM
sequence. No retry attempt will be scheduled on
detection of late collision, and transmit message will
be flushed from the FIFO.
The MAC implements the truncated exponential
back-off algorithm defined by the 802.3 standard.
In full-duplex mode, the MAC transmits
unconditionally.
15
DM8108
8 port 10/100M Fast Ethernet Switching Controller
10/100 Mbps MII Half–duplex Transmission
When the MAC has a frame ready for transmission, it
samples the link activity. If the CRS signal is inacive
(no activity on the link), and the IPG counter has
expired, frame transmission begins. The data is
transmitted through TxD(3:0) of the transmitting port,
clocked on the rising edge of TxCLK. The TxEN is
asserted at same time. In case of collision, the PHY
asserts the COL signal on the MAC, which will then
stop the transmission and will perform contention
resolution. The retry policy is based on the:
Transmit Exception Conditions
T
transmission (including preamble) to be
automatically retried with no switching engine
intervention. The transmit FIFO ensures this by
guaranteeing that the data contained within the
FIFO will not be overwritten until at least 64
bytes (512 bits) of preamble plus address, length,
and data fields have been transmitted onto the
network without encountering a collision. In fullduplex mode, the data in the FIFO can be
overwritten as soon as it is transmitted.
T
Under abnormal operating conditions
.
Under normal operating conditions
The MAC will ensure that the collisions that
occurred within 512 bit times from the start of
Late collision
The MAC will abandon the transmit process for
that frame, and process the next transmit frame
in the ring. Frame experiencing a late collision
will not be retried.
TxCLK
TxEN,
TxD(3:0)
0ns – 25ns
10/100 Mbps MII Half-duplex Reception
Frame reception starts with the assertion of RxDV
(while the MAC is not transmitting) by the PHY.
Once RxDV is asserted, the MAC will begin sampling
the incoming data on pins RxD(3:0) on the rising edge
of RxCLK. Reception ends when the RxDV is de-
asserted by the PHY. The last nibble sampled by the
MAC is the nibble present on RxD(3:0) on the last
RxCLK rising edge in which RxDV is still asserted. If
MAC detected the assertion of RxER while RxDV is
asserted, it will designate this packet as corrupted.
The following figure shows the MII receive signals
timing.
10ns min.
RxCLK
RxDV, RxER, RxD(3:0)
10ns min.
16
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Receive Exceptional Conditions
T
T
Normal network operating conditions
Abnormal network conditions include:
During the reception, the MAC will ensure that if
collision occurs during packet reception, the
packet will be automatically deleted from the
receive FIFO. The Receive FIFO also will delete
any frame that is composed of fewer than 64
bytes (Runt Packet).
32
X
1
+
26
X +
23
X +
22
X +
X
16
+
12
X +
.
Late Collision
Late Collision is the collision being detected
after 512-bit times while receiving.
.
FIFO transfer error
The MAC also monitors FIFO overflow status,
which will force the most recent receiving
packet (not finished) in the FIFO be discarded.
Back-pressure
The DM8108 will generate “jam pattern” to force
collision on the media as far as it finds out that the
internal resources can not meet it demands.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
.
FCS errors
Reception and checking of the received FCS is
performed automatically by the MAC. The
equation is:
11
10
X + X +
If any FCS error occurred, the MAC will discard
the packet.
T
Abnormal network operating conditions
8
X +
7
X
+
5
X +
4
X +
2
X
+
1
X
+
10/100 Mbps Full-Duplex Operation
When operating in the Full-duplex mode, the CRS
signal is associated with the received frames only and
has no effect on the transmitted frames. The COL
signal is ignored by the MAC while in Full-duplex
mode. Transmission starts when TxEN goes active;
regardless the state of RxDV. Reception starts when
the RxDV signal is asserted indicating traffic on the
receiving port. The DM8108 supports IEEE 802.3x
PAUSE function in the full duplex mode operation.
During receiving, the DM8108 will issues PAUSE
command with the largest timer value to stop the
transmitter if the receiving buffer pointer is above the
full threshold value (high water mark). When the
receiving buffer pointer is below the not-full threshold
value (low water mark), it will issue another PAUSE
command with zero timer value to start the transmitter.
The DM8108 is able to monitor the PAUSE command
and stop transmitting accordingly to the timer value
specified in the command packet.
17
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Functional Blocks of the MAC
Collision,
Recovery &
IPG Timing
Protocol
PLA
Address
Recognition
Logic
Command
& Status
Registers
RX
FIFO
Receive
Control
Logic
CRC
Generator
Checker
Transfer
Control
Logic
Transfer
Counters
TX
FIFO
FIFO
Control
Logic
M
U
X
M
U
X
Transmit
Control
Logic
18
Preamble/Synch
JAM Pattern Gen.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
memory configuration mode, the DM8108
acts as Serial MII initiator. In SDRAM
memory configuration, only the DM8108
whose device # equals to 0 is the initiator.
Other devices cascaded will be the listener to
extract the auto-negotiation information from
MID stream.
MII Management
MII Management Registers Serial Access
The MII specification defines a set of 32 16bit status and control registers that are
addressable through the serial data interface
pins MDCLK and MDIO. Please refer to a
PHY device’s spec for the definition
of the registers.
MDCLK has a maximum clock rate of 2.5MHz.
The MDIO line is bi-directional and may be
shared by up to 32 devices. The protocol and
the access waveform are shown below:
The DM8108 will initialize MII management
registers accessing after RESET. In EDO
MDCLK
z
z
MDIO
(DM8108)
z
z
MDIO
(PHY)
z
0
1 1 0 0 1 1 0 0
0 0
0
0 0
z0
0
0
1
1
0
0
0
1
0
0 0
0 00
0
0
z
adle
start
op code
PHY address
Figure
Register address
TR
Register Data
Typical MDIO Read Operation
MDCLK
MDIO z
(DM8108)
z
0
0
1 0 1 0 1 1
0 0 0
0 0 0 0
1
0
0
0
0 0
z
idle
start
op code PHY address
Figure
Protocol
Read Operation
Write Operation
TR
Write Data
Typical MDIO Write Operation
<idle><start><op code><device address><register addr.><Turnaround>< data ><idle>
< z >< 01 >< 10 ><
xxxxx
>< xxxxx
><
z0
><xxxxh><idle>
< z >< 01 >< 01 ><
xxxxx
>< xxxxx
><
10
><xxxxh><idle>
Table
Preliminary
Version: DM8108-DS-P02
November 25, 1999
Register address
MII Management Serial Protocol
19
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Auto-Negotiation
Enabling Partition Mode
Auto-negotiation disabled
Partitioned mode is enabled always.
When ANEG* (MA[7:0]) strap pin is high, autonegotiation is disabled, and the corresponding port
can be selected as half- or full- duplex mode
respectively. Following the RESET the port duplex
mode is set by the state sampled on the TXEN(7:0)
pins.
The speed that each port operates in (10Mbps
or 100Mbps) is determined by the frequency of
TxCLK(7:0) and RxCLK(7:0) generated by PHY. The
PHY generates 25MHz clock for both TxCLK and
RxCLK in 100Mbps operation and 2.5MHz clock in
10Mbps operation.
Entering Partition State
A port will enter the Partition state when PAEN* strap pin
sampled low during reset and when either of the following
conditions occurs:
T
T
The port detects a collision on every one of 64
consecutive re-transmit attempts to the same packet.
The port detects a single collision which occurs for
more than 512 bit times.
Auto-negotiation enabled
While in Partition state:
When ANEG* (MA[7:0]) pins are tied low, the MAC
decodes the duplex mode from the values of the
Auto-Negotiation Advertisement Register and the
Auto-Negotiation Link Partner Ability Register at the
end of Auto-negotiation process. Once the duplex
mode is resolved, the DM8108 updates the port
control registers. The DM8108 will continuously
perform the following operations for each port (PHY
address 0-7 alternatively), implemented as READ
commands issued via the MDCLK/MDIO interface:
T
Link Detection and Link Detection Bypass
(FLNK*)
The DM8108 will continuously query the PHY devices
for their link status associated with Auto-Negotiation
Process. The DM8108 will alternatively read
registers from PHY address 0 to 7 and update the
internal link bits according to the value of bit 2 of
register 1. In case of link down (bit 1.2=0), that port
will enter “link test fail state”. In this state, all the port’s
logic go to a reset state. The port will enter the “link
up state” if the bit 1.2 is “1” or the FLNK* (force link,
LEDSTB* strobed low during reset) pin is sampled low
during reset.
Partition Mode
A port enters partition mode when more than 64
consecutive collisions are seen on the port. In partition
mode the port continuous to transmit but it will not receive.
A port returned to normal operation mode when a good
packet is seen on the wire.
20
The port will continue to transmit its pending packet,
regardless of the collision detection, and will not allow
the usual Back-off Algorithm. Additional packets
pending for transmission, will be transmitted, while
ignoring the internal collision indication. This frees up
the port’s transmit buffers which would otherwise be
filled up at the expense of other ports buffers. The
assumption is that the partition is signifying a system
failure situation (bad connection/cable/station), thus
dropping packets is a small price to pay vs. the cost of
halting the switch due to a buffer full condition. The
partition indication is available via the LED interface.
Exiting from Partition State
The Port exits from Partition State, following the end of a
successful packet transmission. A successful packet
transmission is defined as no collisions were detected on the
first 512 bits of the transmission.
Expansion Bus
The expansion bus operates at Full-Duplex mode that
provides up-to 7200Mbps bandwidth for device to
device connection. Several DM8108 can be
cascaded as a pipe to provide a robust Ethernet
Switching system.
The bus itself is very simple. The transmit and receive ports
contain independent data, valid and handshake signals.
No bus arbitration is involved.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
The receive port utilizes the RDVCLK to clock in the
received data into FIFO and uses RXTOG requests for a
Receiving Buffer block. The switching engine will execute
the similar process as for the Ethernet Ports.
The transmit port appends the Sync. field to a normal
Ethernet packet and sends the packet out through TD(3:0)
at the rising edge of TXENCLK.
TXENCLK
TD(3:0)
Nib n-1
Switching Engine
3)
MAC Address Learning Process
T
1)
Address Recognition
If the packet is from a local port-1) If it is a Unicast address and the address is found
in the Address Table, the DM8108 will:
. If the port number recorded is matched to port
number on which the packet received, the packet
is discarded.
. If the port numbers are different, the packet is
forwarded to the appropriate port.
2) If it is a Unicast address and the address is not
found in the Address Table, the DM8108 acts as if
Preliminary
Version: DM8108-DS-P02
November 25, 1999
If it is a Unicast address specified in the
Destination Address in the Ethernet Packet, the
DM8108 will:
. If the recorded port pointed to a local port, the
packet will be forwarded to that port.
. If the destination address is not found (not
recorded by the Mac address learning process),
the packet will be forwarded to all the local ports
and the Expansion Transmit port.
If the source address was found in the Address Table, the
DM8108 waits for a good packet received indication.
T
If it is a Multicast/Broadcast address, the packet is
forwarded to the Expansion Transmit port and all
local ports (except to the port on which the packet
was received).
If the packet is from Expansion Bus—
If the source address was not found in the Address Table,
the DM8108 waits until the end of the packet (no error) and
updates the Address Table.
The DM8108 forwards the incoming packets to appropriate
port(s) according to the Destination Address as follows:
Nib n+1
the packet is a Multicast packet and forwards it to
the Expansion Transmit port and all the local
ports except the incoming port,
All the packet switching is processed by the Switching
Engine, which has following functions:
The DM8108 has a self-learning mechanism for learning
the MAC addresses of attached Fast Ethernet devices in
real time. The DM8108 searches for the source address of
an incoming packet in the Address Table and acts as
follows:
NIb n
2)
If it is a Multicast/Broadcast address (destination
device # should set invalid), the packet will be
forwarded to all the local ports and the Expansion
Transmit port.
Address Aging
The DM8108 includes hardware to support for automatic
address aging.
Buffers and Queues
The DM8108 incorporates 3 transmit queues and one
common receive buffer area for the two Fast Ethernet ports
and the Expansion Port, The queues and buffers are
located in the DRAM along with Address Table. The
21
DM8108
8 port 10/100M Fast Ethernet Switching Controller
DM8108 data structure components are the following:
T
Receiving Buffer – a common receive buffer is
allocated for each Fast Ethernet Receiving Port and
Expansion Bus Receiving Port. The size of the
receiving buffer is defined as 642KB (448 blocks) or
1728KB (1152 blocks) (depending on the DRAM size)
of 1.5K Bytes each. The DM8108 allocates the buffers
to the 8 Ethernet ports and the Expansion port.
Transmit Descriptors (TxDR) – A set of 9 transmit
descriptor rings. Each ring contains 512 descriptors.
The Descriptor’s size is 32-bit and contains the
Receiving Buffer’s Block Number, the packet length
and the packet type (Multicast or Uni-cast). The
Transmit Descriptors reside in the DRAM.
T
23
M/ -U
Read/Write Pointers – 9 pairs of pointers to the
Transmit Descriptors.
22
Byte Count
1211
0
Block Number
Read Pointer
Write Pointer
Frame # n
Frame # 2
Frame # 1
Frame # 0
Next Empty
Rx Block #
Empty List
22
Tx Descriptors: 1K x 3
Receive Buffer
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
DM8108 DRAM Address Mapping
Queue & Buffers
Receive Buffer
ACC Count
Reserved
TDR queue
Address Table
Description
864KB ( 576 blocks)
1872KB (1248blocks) + unused
8KB
4KB
20KB
128KB
Memory Size
1M Byte
028000 – 0FFFFF
2M Byte
028000 – 1FFFFF
026000 – 027FFF
025000 – 025FFF
020000 – 024FFF
000000 – 01FFFF
027000 – 027FFF
025000 – 025FFF
020000 – 024FFF
000000 – 01FFFF
Address Table
The Address Table structure occupies 128K bytes of
memory and is controlled and initialized by the
DM8108. Following RESET, the DM8108 initializes
Field
V
Address (47:0)
Port #
Reserved
Device #
Time Stamp
Description
Valid – Indicates a valid entry; 0 – Not Valid, 1 – valid.
Source MAC address. Unicast address only
Port Number – indicates which of the 3-port in a DM8108 is associated with this source address.
0h – 1h: Port 0 –Port 1 (2 Ethernet ports); 2h: Expansion Port.
Device number—indicate which device in the switching system is associated with this source address
4-bit Tag—used to identify the update sequence. If the entry-block(4-entry) pointed by a MAC address index are
all occupied, the entry that has oldest time stamp will be replaced.
Packet Forwarding
The following sections describe the procedures for
forwarding packets under different situations:
Forwarding a Uni-cast packet to a local Ethernet
port
The incoming packet is fed to the Rx FIFO and is
transferred to an empty block in the Receive Buffer
area of DRAM. The switching engine will claim the
block by setting the Empty List not empty. In case of
collision or FIFO overflow, transfer error etc . , the
engine has to reset the Empty List associated with the
block.
In parallel, an address recognition cycle will be
performed for both the destination and source address.
The DM8108 will use SA to learn a new or changed
Preliminary
Version: DM8108-DS-P02
November 25, 1999
the Address Table by invalidating the Valid bit of all
entries.
address entry. The DA will point to an entry that
specifies the local port’s number.
At the end of reception of an error-free packet, the
packet information is written to the appropriate port’s
transmit descriptor. This information includes the
Byte Count, Receive block address which points to
the Write Pointer, and the Priority indication.
The Write Pointer of the outgoing port’s transmit
descriptor is incremented. The target port prepare for
transmission whenever the Write Pointer and the
Read pointer are not equal.
The engine resolves the priority issue and fills the Tx
FIFO before starting the transmission. If any Tx
FIFO under run situation happens, the MAC has to
force the packet “Bad” and inform the engine to retry.
At the end of the good transmit process, the target
port increments the Read Pointer. The Engine clears
the appropriate bit in the Empty List.
23
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Forward a Multicast, Broadcast and “Unknown”
packet
If the received packet’s DA is not found in the Address
Table, or the packet is a Multicast or Broadcast packet,
it will be treated as a Multicast packet, the switching
engine will perform most of the steps mentioned
above and forwards the packet to all ports.
Following the RESET, the DRAM controller will
perform DRAM testing by write/read several patterns
and invalidate all the entries in the Address Table. The
DRAM test result is sent out through the LED status
outputs.
LED interface
The DM8108 provides LED data bus, address bus and
strobe signals to:
DRAM Controller
T
The DM8108 includes direct support for Synchronous
DRAM. The DRAM interface is entirely glue-less. All
the accesses are performed as 32-bit. The memory
controller is designed targeting up to 90-MHz.
T
Display the chip or ports’ configuration and
transfer status,
Display the critical state signals for debug
purpose.
LED signals definition
The DM8108 refreshes the DRAM automatically.
The following timing diagram shows the interface of
LED bus while displaying LED signals.
1us
LDCLK
LDSTB
LD
For the LED signals having dynamic characteristics, the
DM8108 will maintain the signal for a minimum of
4ms before sending to the LED bus if the state is triggered.
Dynamic
signal
LD
24
4ms – 8 ms
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
The following table shows the multiplexed LED signals.
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Preliminary
Version: DM8108-DS-P02
November 25, 1999
Signals
Primary_port status 0 (link 0)
Primary_port status 1 (link 1)
Primary_port status 2 (link 2)
Primary_port status 3 (link 3)
Primary_port status 4 (link 4)
Primary_port status 5 (link 5)
Primary_port status 6 (link 6)
Primary_port status 7 (link 7)
Transmit (0)
Receiving (0)
Collision (0)
Rx buffer full (0)
Reserved
Reserved
Full duplex (0)
Port Speed (0)
Transmit (1)
Receiving (1)
Collision (1)
Rx buffer full (1)
Reserved
Reserved
Full duplex (1)
Port Speed (1)
Transmit (2)
Receiving (2)
Collision (2)
Rx buffer full (2)
Reserved
Reserved
Full duplex (2)
Port Speed (2)
Transmit (3)
Receiving (3)
Collision (3)
Rx buffer full (3)
Reserved
Reserved
Full duplex (3)
Port Speed (3)
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signals
Transmit (4)
Receiving (4)
Collision (4)
Rx buffer full (4)
Reserved
Reserved
Full duplex (4)
Port Speed (4)
Transmit (5)
Receiving (5)
Collision (5)
Rx buffer full (5)
Reserved
Reserved
Full duplex (5)
Port Speed (5)
Transmit (6)
Receiving (6)
Collision (6)
Rx buffer full (6)
Reserved
Reserved
Full duplex (6)
Port Speed (6)
Transmit (7)
Receiving (7)
Collision (7)
Rx buffer full (7)
Reserved
Reserved
Full duplex (7)
Port Speed (7)
Partition (0)
Partition (1)
Partition (2)
Partition (3)
Partition (4)
Partition (5)
Partition (6)
Partition (7)
25
DM8108
8 port 10/100M Fast Ethernet Switching Controller
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
26
Runt packet (0)
Runt packet (1)
Runt packet (2)
Runt packet (3)
Runt packet (4)
Runt packet (5)
Runt packet (6)
Runt packet (7)
Jab packet (0)
Jab packet (1)
Jab packet (2)
Jab packet (3)
Jab packet (4)
Jab packet (5)
Jab packet (6)
Jab packet (7)
Under_flow(0)
Under_flow(1)
Under_flow(2)
Under_flow(3)
Under_flow(4)
Under_flow(5)
Under_flow(6)
Under_flow(7)
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Link fail (0)
Link fail (1)
Link fail (2)
Link fail (3)
Link fail (4)
Link fail (5)
Link fail (6)
Link fail (7)
Pure_port_status(0)
Pure_port_status(1)
Pure_port_status(2)
Pure_port_status(3)
Pure_port_status(4)
Pure_port_status(5)
Pure_port_status(6)
Pure_port_status(7)
DRAM test status
Internal SRAM test status
123
124
125-128
Expansion Port RX buf. full
Dynamic allocation buf. full
Reserved
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Strap Pins during Reset
The following table shows the strap pins during RESET.
Symbol
LEDSTB
LEDD
TXD0[3:0]
TXD1[3:0]
TXD2[3:0]
TXD3[3:0]
TXD4[3:0]
TXD5[1:0]
TXEN(7:0)
MA9
MA8
MA(7:0)
Description
Strap pin during reset:
0= force link, 1= link detection through serial MII (default)
Strap pin for TXENCLK frequency of expansion port:
0=fast, 1= slow (default)
TXD0[0]: Strap pin for the operating frequency
0=88Mhz; 1= 66Mhz (default)
TXD0[1]: Strap pin to enable partition mode
0=enable; 1=disable (default)
TXD0[2]: Strap pin to enable expansion port
0=enable; 1=disable (default)
TXD0[3]: Strap pin to enable BIST
0=init only; 1=enable (default)
TXD1[2:0]: test function
TXD1[3]: disable CRC checking
0= disable; 1=enable (default)
Strap pins during reset:
TXD2[2:0] = device # setting
TXD2[3] strapped for DRAM timing: 0=fast, 1= normal (default)
Strap pin during reset:
TXD3[0] Max packet size selection:
0 = 1536 bytes, 1=1518 bytes (default)
TXD3[1] Back pressure and flow control enable:
0 = enable, 1 = disable (default)
TXD3[3:2] aging timing selection:
00 – 64sec. 01 –12 8 sec.
10 – 256 sec. 11 – disable (default)
Strap pin during reset:
TXD4[0] port 0 trunking selection: 0 = enable, 1=disable (default)
TXD4[1] port 1 trunking selection: 0 = enable, 1=disable (default)
TXD4[2] port 2 trunking selection: 0 = enable, 1=disable (default)
TXD4[3] port 3 trunking selection: 0 = enable, 1=disable (default)
Strap pin during reset:
TXD5[1:0] broadcast filtering rate selection:
00 = 8k packets/sec. 01 = 16k packets/sec.
10 = 64k packets/sec. 11 = disable (default)
Strap pins during reset for ports’ operating mode:
0= full duplex, 1=half duplex (default)
Strap pin during reset:
0= limit4 enabled, 1= disabled (default)
Strap pin during reset for memory size selection:
0= 2MB, 1= 1MB (default)
Strap pins during reset:
MA7-0: Auto-negotiation enable for port0:
0= enabled (default), 1 = disabled
Preliminary
Version: DM8108-DS-P02
November 25, 1999
27
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Absolute Maximum Ratings
Absolute Maximum Ratings ( 25°°C )
Symbol
Parameter
Min.
Max.
Unit
Vcc
Vi
Vo
Io
Iik
Iok
Tc
Tstg
ESD
Supply voltage
Input voltage
Output voltage
Output Current
Input protection diode current
Output protection diode current
Operating temperature
Storage temperature
Static Discharge voltage
-0.3
-0.3
-0.3
2
3.6
5.25
Vcc + 0.3
24
0
-40
2000
70
125
V
V
V
mA
mA
MA
C
C
V
Symbol
Parameter
Min.
Max.
Unit
Vcc
Vi
Vo
Tc
Cin
Cout
Supply voltage
Input voltage
Output voltage
Operating temperature
Input Capacitance
Output Capacitance
3.3
0
0
0
3.6
Vcc
Vcc
70
V
V
V
C
pF
pF
Conditions
Operating Conditions
Conditions
Comments
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device.
These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
28
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
DC Electrical Characteristics (0°C<TA<70°C, 3.135<VCC<3.465, unless otherwise noted)
Symbol
Parameter
Min.
Vih
Vil
Voh
Vol
Iih
Iil
Ioz
Icc
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input high current
Input low current
Output high impedence current
Operating Current
2.0
2.4
0
Max.
Unit
0.8
Vcc
0.4
±1
±1
±1
TBD
V
V
V
V
uA
uA
uA
mA
Conditions
Thermal Information
Symbol
Parameter
Value
θja
Thermal resistance: junction to ambient; 0 ft/s
airflow
Thermal resistance: junction to case;
0ft/s airflow
Operating junction temperature
Input Capacitance
42 °C/W
θjc
Tj
Cin
Preliminary
Version: DM8108-DS-P02
November 25, 1999
TBD
125 °C
29
DM8108
8 port 10/100M Fast Ethernet Switching Controller
AC Electrical Characteristics & Timing Waveforms
(Tc = 0 – 70 °C; Vcc = 3.3V ± 5%)
Symbol
t3
t4
t5
t6
t7
Signals
SCLK
SCLK
RST*
MA, MD, CAS*,
RAS*,DWE*,
SDQM,
SCS*,SRAS*,
SCAS*
MD, RXD8 (1)
MD, RXD8 (2)
MD
MD, TXD8 (3)
Parameter
System Clock frequency
Rise/Fall time
Reset pulse width
Delay from SCLK rising or falling
edge
Min.
66
1
2
2
Setup time
Hold time
Float delay
Drive delay
2
2
2
2
Max.
90
4
8
Unit
MHz
ns
SCLK
ns
8
8
ns
ns
ns
ns
Conditions
Notes:
1. MD is related to SCLK; RXD8 is related to RXDVCLK.
2. MD is related to SCLK; TXD8 is related to TXENCLK.
3. All Delays, Setup, and Hold times are referred to SCLK rising edge unless stated otherwise.
4. All outputs are specified for 25 pF load.
5. All inputs and outputs also refer to I/O signal behavior.
Output Delay from Rising Edge
SCLK
t3 min
t3 min
t3 max
30
t3 max
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Setup and Hold time from Rising Edge
SCLK or
RXDVCLK
t4 min
t5 min
Drive or Float Delay from Rising Edge
SCLK or
TXENCLK
t7 min
t6 min
t7 max
Preliminary
Version: DM8108-DS-P02
November 25, 1999
t6 max
31
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Package Information
QFP 208L Outline Dimensions
unit: inches/mm
HD
D
208
157
1
GE
E
F
52
HE
156
105
e
GD
104
A
c
b
~~
53
A2
GD
y
A1
D
See Detail F
Seating Plane
L
L1
DETAIL F
Symbol
Dimensions in inches
Dimensions in mm
3.68 Max.
A
0.145 Max.
A1
0.004 Min.
0.10 Min.
A2
0.127 ± 0.005
3.23 ± 0.13
b
0.008
+0.002
0.20
+0.05
0.15
+0.10
-0.002
c
0.006
+0.004
-0.05
-0.002
-0.05
1.102 ± 0.005
28.00 ± 0.13
E
1.102 ± 0.005
28.00 ± 0.13
e
0.020 ± 0.004
0.50 ± 0.10
F
1.004 NOM.
25.5 NOM.
GD
1.185 NOM.
30.10 NOM.
GE
1.185 NOM.
30.10 NOM.
HD
1.205 ± 0.012
30.60 ± 0.30
HE
1.205 ± 0.012
30.60 ± 0.30
L
0.019 ± 0.008
0.50 ± 0.20
L1
0.051 ± 0.008
1.30 ± 0.20
y
0.004 Max.
0.10 Max.
θ
0° ~ 10°
0° ~ 10°
D
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions F, GD, GE are for PC Board surface mount pad pitch
design reference only.
32
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary
Version: DM8108-DS-P02
November 25, 1999
33
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Appendix:
Cascade Three DM8108s to a 24-port Switch Illustration
SGRAM
DM8108
DM8108
DRAM
rxd2
txd2
PHY
txenclk
DM8108
DRAM
rxd2
txd2
rxdvclk
34
SDRAM
SDRAM
DRAM
rxd2
txd2
rxdvclk
PHY
txenclk
rxdvclk
txenclk
PHY
Preliminary
Version: DM8108-DS-P02
November 25, 1999
DM8108
8 port 10/100M Fast Ethernet Switching Controller
Ordering Information
Part Number
DM8108
Pin Count
208
Package
QFP
Disclaimer
The information appearing in this publication is believed to
be accurate. Integrated circuits sold by DAVICOM
Semiconductor are covered by the warranty and patent
indemnification provisions stipulated in the terms of sale
only. DAVICOM makes no warranty, express, statutory,
implied or by description regarding the information in this
publication or regarding the information in this publication or
regarding the freedom of the described chip(s) from patent
infringement. FURTHER, DAVICOM MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PURPOSE. DAVICOM deserves the right to halt
production or alter the specifications and prices at any time
without notice. Accordingly, the reader is cautioned to verify
that the data sheets and other information in this publication
are current before placing orders. Products described herein
are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without
additional processing by DAVICOM for such applications.
Please note that application circuits illustrated in this
document are for reference purposes only.
DAVICOM’s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms inconsistent with
these unless DAVICOM agrees otherwise in writing.
Acceptance of the buyer’s orders shall be based on these
terms.
Company Overview
DAVICOM Semiconductor, Inc. develops and
manufactures integrated circuits for integration into data
communication products. Our mission is to design and
produce IC products that re the industry’s best value for
Data, Audio, Video, and Internet/Intranet applications. To
achieve this goal, we have built an organization that is able
to develop chipsets in response to the evolving technology
requirements of our customers while still delivering products
that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently available
and soon to be released products are based on our
proprietary designs and deliver high quality, high
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Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Hsin-chu Office:
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits
of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Preliminary
Version: DM8108-DS-P02
November 25, 1999
35